Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 920 1 T6 11 T21 11 T19 28
all_values[1] 920 1 T6 11 T21 11 T19 28
all_values[2] 920 1 T6 11 T21 11 T19 28


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1428 1 T6 15 T21 16 T19 38
auto[1] 1332 1 T6 18 T21 17 T19 46


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 953 1 T6 15 T21 14 T19 28
auto[1] 1807 1 T6 18 T21 19 T19 56


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1568 1 T6 18 T21 19 T19 52
auto[1] 1192 1 T6 15 T21 14 T19 32


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 177 1 T6 2 T21 2 T19 2
all_values[0] auto[0] auto[0] auto[1] 103 1 T6 1 T21 1 T19 7
all_values[0] auto[0] auto[1] auto[0] 140 1 T6 3 T21 1 T19 5
all_values[0] auto[0] auto[1] auto[1] 95 1 T21 1 T19 3 T60 2
all_values[0] auto[1] auto[0] auto[1] 215 1 T6 3 T21 3 T19 8
all_values[0] auto[1] auto[1] auto[1] 190 1 T6 2 T21 3 T19 3
all_values[1] auto[0] auto[0] auto[0] 175 1 T6 2 T21 2 T19 3
all_values[1] auto[0] auto[0] auto[1] 116 1 T21 2 T19 3 T56 2
all_values[1] auto[0] auto[1] auto[0] 151 1 T6 4 T19 6 T56 4
all_values[1] auto[0] auto[1] auto[1] 107 1 T6 2 T19 5 T60 1
all_values[1] auto[1] auto[0] auto[1] 190 1 T6 2 T21 2 T19 6
all_values[1] auto[1] auto[1] auto[1] 181 1 T6 1 T21 5 T19 5
all_values[2] auto[0] auto[0] auto[0] 149 1 T6 1 T21 4 T19 4
all_values[2] auto[0] auto[0] auto[1] 95 1 T60 2 T56 4 T129 2
all_values[2] auto[0] auto[1] auto[0] 161 1 T6 3 T21 5 T19 8
all_values[2] auto[0] auto[1] auto[1] 99 1 T21 1 T19 6 T129 2
all_values[2] auto[1] auto[0] auto[1] 208 1 T6 4 T19 5 T60 3
all_values[2] auto[1] auto[1] auto[1] 208 1 T6 3 T21 1 T19 5


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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