Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4014	1			T1	6		T2	4		T3	2
sha2_none	4137	1			T1	4		T2	2		T3	1
sha2_512	7558	1			T1	8		T3	1		T4	6
sha2_384	7366	1			T1	6		T3	1		T4	14
sha2_256	6178	1			T1	6		T2	2		T3	2

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18513

1

T1

16

T2

1

T3

4

auto[1]

11118

1

T1

14

T2

7

T3

3

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11030

1

T1

18

T2

3

T3

4

auto[1]

18601

1

T1

12

T2

5

T3

3

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

15414

1

T1

11

T2

2

T3

2

disabled

14217

1

T1

19

T2

6

T3

5

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4493	1			T1	6		T2	1		T3	3
key_none	7779	1			T1	5		T3	1		T4	4
key_1024	4316	1			T1	2		T2	3		T4	6
key_512	3651	1			T1	6		T4	10		T5	7
key_384	3384	1			T1	2		T2	1		T4	8
key_256	3032	1			T1	6		T2	1		T3	1
key_128	2891	1			T1	3		T2	2		T3	2

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18578

1

T1

14

T2

6

T3

5

auto[1]

11053

1

T1

16

T2

2

T3

2

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

29463

1

T1

30

T2

8

T3

7

disabled

168

1

T59

1

T19

3

T60

2

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1589

1

T1

1

T4

3

T5

1

enabled

auto[0]

auto[0]

auto[1]

1585

1

T1

2

T4

2

T5

2

enabled

auto[0]

auto[1]

auto[0]

1573

1

T1

2

T3

1

T4

2

enabled

auto[0]

auto[1]

auto[1]

1596

1

T1

2

T2

1

T4

3

enabled

auto[1]

auto[0]

auto[0]

4231

1

T1

1

T2

1

T4

4

enabled

auto[1]

auto[0]

auto[1]

1602

1

T1

2

T3

1

T4

1

enabled

auto[1]

auto[1]

auto[0]

1622

1

T1

1

T5

2

T16

1

enabled

auto[1]

auto[1]

auto[1]

1616

1

T4

5

T5

5

T16

1

disabled

auto[0]

auto[0]

auto[0]

1133

1

T1

5

T3

2

T4

4

disabled

auto[0]

auto[0]

auto[1]

1165

1

T1

1

T5

2

T17

2

disabled

auto[0]

auto[1]

auto[0]

1236

1

T1

1

T2

2

T3

1

disabled

auto[0]

auto[1]

auto[1]

1153

1

T1

4

T4

5

T5

4

disabled

auto[1]

auto[0]

auto[0]

6029

1

T1

1

T4

1

T5

3

disabled

auto[1]

auto[0]

auto[1]

1179

1

T1

3

T3

1

T4

2

disabled

auto[1]

auto[1]

auto[0]

1165

1

T1

2

T2

3

T3

1

disabled

auto[1]

auto[1]

auto[1]

1157

1

T1

2

T2

1

T4

4

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

15348

1

T1

11

T2

2

T3

2

enabled

disabled

66

1

T19

1

T60

2

T7

1

disabled

disabled

102

1

T59

1

T19

2

T129

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

14115

1

T1

19

T2

6

T3

5

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1038	1			T1	1		T2	1		T3	2
key_invalid	sha2_none	841	1			T1	1		T4	1		T6	8
key_invalid	sha2_512	860	1			T1	1		T3	1		T5	3
key_invalid	sha2_384	861	1			T1	1		T4	3		T5	2
key_invalid	sha2_256	803	1			T1	2		T4	1		T5	2
key_none	sha2_invalid	530	1			T1	1		T16	1		T18	1
key_none	sha2_none	537	1			T1	1		T5	1		T18	1
key_none	sha2_512	2556	1			T1	2		T4	1		T6	5
key_none	sha2_384	2540	1			T4	2		T5	2		T15	1
key_none	sha2_256	1561	1			T1	1		T3	1		T4	1
key_1024	sha2_invalid	484	1			T2	1		T6	8		T21	3
key_1024	sha2_none	582	1			T4	1		T17	2		T18	3
key_1024	sha2_512	1709	1			T1	1		T18	1		T6	1
key_1024	sha2_384	922	1			T4	2		T15	1		T6	4
key_512	sha2_invalid	491	1			T1	2		T4	1		T17	2
key_512	sha2_none	518	1			T4	2		T5	2		T17	1
key_512	sha2_512	610	1			T1	2		T4	1		T5	2
key_512	sha2_384	1179	1			T1	1		T4	4		T5	2
key_512	sha2_256	808	1			T1	1		T4	2		T5	1
key_384	sha2_invalid	494	1			T1	1		T4	1		T5	1
key_384	sha2_none	537	1			T2	1		T4	2		T5	1
key_384	sha2_512	635	1			T4	3		T5	3		T15	1
key_384	sha2_384	620	1			T1	1		T16	1		T6	6
key_384	sha2_256	1043	1			T4	2		T5	3		T16	1
key_256	sha2_invalid	488	1			T1	1		T2	1		T5	1
key_256	sha2_none	562	1			T1	1		T4	2		T15	1
key_256	sha2_512	606	1			T1	1		T4	1		T5	2
key_256	sha2_384	610	1			T1	3		T3	1		T5	2
key_256	sha2_256	727	1			T4	1		T18	1		T6	6
key_128	sha2_invalid	465	1			T2	1		T4	1		T5	1
key_128	sha2_none	545	1			T1	1		T2	1		T3	1
key_128	sha2_512	572	1			T1	1		T5	1		T6	11
key_128	sha2_384	617	1			T4	3		T5	3		T17	1
key_128	sha2_256	647	1			T1	1		T3	1		T5	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

573

1

T1

1

T2

2

T4

3

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1038	1			T1	1		T2	1		T3	2
key_invalid	sha2_none	841	1			T1	1		T4	1		T6	8
key_invalid	sha2_512	860	1			T1	1		T3	1		T5	3
key_invalid	sha2_384	861	1			T1	1		T4	3		T5	2
key_invalid	sha2_256	803	1			T1	2		T4	1		T5	2
key_none	sha2_invalid	530	1			T1	1		T16	1		T18	1
key_none	sha2_none	537	1			T1	1		T5	1		T18	1
key_none	sha2_512	2556	1			T1	2		T4	1		T6	5
key_none	sha2_384	2540	1			T4	2		T5	2		T15	1
key_none	sha2_256	1561	1			T1	1		T3	1		T4	1
key_1024	sha2_invalid	484	1			T2	1		T6	8		T21	3
key_1024	sha2_none	582	1			T4	1		T17	2		T18	3
key_1024	sha2_512	1709	1			T1	1		T18	1		T6	1
key_1024	sha2_384	922	1			T4	2		T15	1		T6	4
key_1024	sha2_256	573	1			T1	1		T2	2		T4	3
key_512	sha2_invalid	491	1			T1	2		T4	1		T17	2
key_512	sha2_none	518	1			T4	2		T5	2		T17	1
key_512	sha2_512	610	1			T1	2		T4	1		T5	2
key_512	sha2_384	1179	1			T1	1		T4	4		T5	2
key_512	sha2_256	808	1			T1	1		T4	2		T5	1
key_384	sha2_invalid	494	1			T1	1		T4	1		T5	1
key_384	sha2_none	537	1			T2	1		T4	2		T5	1
key_384	sha2_512	635	1			T4	3		T5	3		T15	1
key_384	sha2_384	620	1			T1	1		T16	1		T6	6
key_384	sha2_256	1043	1			T4	2		T5	3		T16	1
key_256	sha2_invalid	488	1			T1	1		T2	1		T5	1
key_256	sha2_none	562	1			T1	1		T4	2		T15	1
key_256	sha2_512	606	1			T1	1		T4	1		T5	2
key_256	sha2_384	610	1			T1	3		T3	1		T5	2
key_256	sha2_256	727	1			T4	1		T18	1		T6	6
key_128	sha2_invalid	465	1			T2	1		T4	1		T5	1
key_128	sha2_none	545	1			T1	1		T2	1		T3	1
key_128	sha2_512	572	1			T1	1		T5	1		T6	11
key_128	sha2_384	617	1			T4	3		T5	3		T17	1
key_128	sha2_256	647	1			T1	1		T3	1		T5	1