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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.03 95.40 97.17 100.00 97.06 98.27 98.48 99.85


Total test records in report: 657
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T69 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2101338823 Aug 19 05:04:22 PM PDT 24 Aug 19 05:04:24 PM PDT 24 52537716 ps
T70 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3178475240 Aug 19 05:04:32 PM PDT 24 Aug 19 05:04:35 PM PDT 24 700371483 ps
T530 /workspace/coverage/cover_reg_top/47.hmac_intr_test.425763199 Aug 19 05:04:45 PM PDT 24 Aug 19 05:04:45 PM PDT 24 15590080 ps
T531 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.275498778 Aug 19 05:04:22 PM PDT 24 Aug 19 05:04:24 PM PDT 24 456970784 ps
T532 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2427506235 Aug 19 05:04:35 PM PDT 24 Aug 19 05:04:36 PM PDT 24 23644601 ps
T533 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3628231630 Aug 19 05:04:34 PM PDT 24 Aug 19 05:04:34 PM PDT 24 12584086 ps
T534 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.996831619 Aug 19 05:04:26 PM PDT 24 Aug 19 05:04:28 PM PDT 24 26834836 ps
T71 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2446373845 Aug 19 05:04:10 PM PDT 24 Aug 19 05:04:15 PM PDT 24 128191559 ps
T535 /workspace/coverage/cover_reg_top/41.hmac_intr_test.122427211 Aug 19 05:04:34 PM PDT 24 Aug 19 05:04:34 PM PDT 24 13905389 ps
T106 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.293572586 Aug 19 05:04:37 PM PDT 24 Aug 19 05:04:38 PM PDT 24 134964245 ps
T536 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3432689003 Aug 19 05:04:34 PM PDT 24 Aug 19 05:04:35 PM PDT 24 12514358 ps
T133 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2970708748 Aug 19 05:04:12 PM PDT 24 Aug 19 05:04:15 PM PDT 24 573834432 ps
T537 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.847123560 Aug 19 05:04:33 PM PDT 24 Aug 19 05:04:36 PM PDT 24 151154724 ps
T538 /workspace/coverage/cover_reg_top/45.hmac_intr_test.19555433 Aug 19 05:04:52 PM PDT 24 Aug 19 05:04:53 PM PDT 24 43041342 ps
T539 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1799901378 Aug 19 05:04:27 PM PDT 24 Aug 19 05:04:27 PM PDT 24 40722994 ps
T107 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3364618777 Aug 19 05:04:15 PM PDT 24 Aug 19 05:04:16 PM PDT 24 38797612 ps
T540 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2204865689 Aug 19 05:04:24 PM PDT 24 Aug 19 05:04:27 PM PDT 24 153724470 ps
T541 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2892882285 Aug 19 05:04:12 PM PDT 24 Aug 19 05:04:27 PM PDT 24 7505558371 ps
T542 /workspace/coverage/cover_reg_top/2.hmac_intr_test.572333446 Aug 19 05:04:15 PM PDT 24 Aug 19 05:04:16 PM PDT 24 18404610 ps
T543 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3321292035 Aug 19 05:04:35 PM PDT 24 Aug 19 05:04:37 PM PDT 24 68459706 ps
T544 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3579167208 Aug 19 05:04:15 PM PDT 24 Aug 19 05:07:28 PM PDT 24 20764303958 ps
T545 /workspace/coverage/cover_reg_top/11.hmac_intr_test.3296238710 Aug 19 05:04:24 PM PDT 24 Aug 19 05:04:25 PM PDT 24 57346822 ps
T122 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3604909797 Aug 19 05:04:22 PM PDT 24 Aug 19 05:04:24 PM PDT 24 211398310 ps
T546 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2956886228 Aug 19 05:04:11 PM PDT 24 Aug 19 05:04:11 PM PDT 24 13404186 ps
T134 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3341803895 Aug 19 05:04:25 PM PDT 24 Aug 19 05:04:30 PM PDT 24 225568718 ps
T108 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1899925500 Aug 19 05:04:11 PM PDT 24 Aug 19 05:04:12 PM PDT 24 21040047 ps
T547 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2768348352 Aug 19 05:04:22 PM PDT 24 Aug 19 05:04:22 PM PDT 24 50364596 ps
T548 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.440336189 Aug 19 05:04:14 PM PDT 24 Aug 19 05:04:18 PM PDT 24 1259158821 ps
T549 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1331622070 Aug 19 05:04:25 PM PDT 24 Aug 19 05:04:26 PM PDT 24 51965620 ps
T550 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3650941720 Aug 19 05:04:35 PM PDT 24 Aug 19 05:04:35 PM PDT 24 12633142 ps
T551 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3594083537 Aug 19 05:04:12 PM PDT 24 Aug 19 05:04:14 PM PDT 24 554375088 ps
T552 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1182218650 Aug 19 05:04:47 PM PDT 24 Aug 19 05:04:47 PM PDT 24 175337497 ps
T553 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1158403490 Aug 19 05:04:25 PM PDT 24 Aug 19 05:04:27 PM PDT 24 168021270 ps
T554 /workspace/coverage/cover_reg_top/5.hmac_intr_test.966710114 Aug 19 05:04:10 PM PDT 24 Aug 19 05:04:11 PM PDT 24 41494946 ps
T123 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2730200017 Aug 19 05:04:13 PM PDT 24 Aug 19 05:04:15 PM PDT 24 34265874 ps
T555 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.843465550 Aug 19 05:04:25 PM PDT 24 Aug 19 05:04:28 PM PDT 24 376125791 ps
T124 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.502883646 Aug 19 05:04:22 PM PDT 24 Aug 19 05:04:25 PM PDT 24 220804996 ps
T109 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1728393352 Aug 19 05:04:22 PM PDT 24 Aug 19 05:04:23 PM PDT 24 128011561 ps
T110 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.449550643 Aug 19 05:04:27 PM PDT 24 Aug 19 05:04:28 PM PDT 24 116986541 ps
T125 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1470268743 Aug 19 05:04:26 PM PDT 24 Aug 19 05:04:28 PM PDT 24 171530754 ps
T111 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.891997799 Aug 19 05:04:15 PM PDT 24 Aug 19 05:04:16 PM PDT 24 29130308 ps
T112 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1331911972 Aug 19 05:04:15 PM PDT 24 Aug 19 05:04:30 PM PDT 24 1230086187 ps
T556 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3944029355 Aug 19 05:04:33 PM PDT 24 Aug 19 05:04:34 PM PDT 24 61295334 ps
T135 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1794985239 Aug 19 05:04:24 PM PDT 24 Aug 19 05:04:29 PM PDT 24 346783560 ps
T557 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1731095745 Aug 19 05:04:04 PM PDT 24 Aug 19 05:04:08 PM PDT 24 162240996 ps
T558 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3502463066 Aug 19 05:04:35 PM PDT 24 Aug 19 05:04:36 PM PDT 24 14806767 ps
T113 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1440641080 Aug 19 05:04:16 PM PDT 24 Aug 19 05:04:25 PM PDT 24 2497647567 ps
T559 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1973029460 Aug 19 05:04:22 PM PDT 24 Aug 19 05:17:09 PM PDT 24 357573420647 ps
T560 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1509980583 Aug 19 05:04:37 PM PDT 24 Aug 19 05:04:37 PM PDT 24 25573694 ps
T561 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2739950838 Aug 19 05:04:29 PM PDT 24 Aug 19 05:04:30 PM PDT 24 51775055 ps
T562 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1897248766 Aug 19 05:04:24 PM PDT 24 Aug 19 05:04:27 PM PDT 24 168843934 ps
T563 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2575540007 Aug 19 05:04:37 PM PDT 24 Aug 19 05:04:38 PM PDT 24 17884480 ps
T564 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3131496648 Aug 19 05:04:13 PM PDT 24 Aug 19 05:04:17 PM PDT 24 78264064 ps
T565 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1412850677 Aug 19 05:04:23 PM PDT 24 Aug 19 05:04:25 PM PDT 24 193004934 ps
T114 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1198248446 Aug 19 05:04:25 PM PDT 24 Aug 19 05:04:26 PM PDT 24 16658872 ps
T566 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.4205686005 Aug 19 05:04:27 PM PDT 24 Aug 19 05:04:28 PM PDT 24 15185422 ps
T567 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1028759226 Aug 19 05:04:27 PM PDT 24 Aug 19 05:04:29 PM PDT 24 53244569 ps
T568 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1935334350 Aug 19 05:04:21 PM PDT 24 Aug 19 05:04:23 PM PDT 24 165143970 ps
T136 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1764964804 Aug 19 05:04:27 PM PDT 24 Aug 19 05:04:31 PM PDT 24 771788495 ps
T115 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3450134882 Aug 19 05:04:12 PM PDT 24 Aug 19 05:04:15 PM PDT 24 313852251 ps
T137 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1983332385 Aug 19 05:04:05 PM PDT 24 Aug 19 05:04:10 PM PDT 24 1847665100 ps
T569 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3401274410 Aug 19 05:04:10 PM PDT 24 Aug 19 05:21:11 PM PDT 24 120969421941 ps
T116 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2333114903 Aug 19 05:04:20 PM PDT 24 Aug 19 05:04:26 PM PDT 24 560433578 ps
T570 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2975715669 Aug 19 05:04:25 PM PDT 24 Aug 19 05:04:26 PM PDT 24 106475082 ps
T571 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2296477443 Aug 19 05:04:23 PM PDT 24 Aug 19 05:04:26 PM PDT 24 148202503 ps
T572 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3459746070 Aug 19 05:04:45 PM PDT 24 Aug 19 05:04:46 PM PDT 24 29921533 ps
T573 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1243150723 Aug 19 05:04:25 PM PDT 24 Aug 19 05:04:28 PM PDT 24 213715320 ps
T574 /workspace/coverage/cover_reg_top/3.hmac_intr_test.225718234 Aug 19 05:04:13 PM PDT 24 Aug 19 05:04:13 PM PDT 24 13653486 ps
T575 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1713694592 Aug 19 05:04:13 PM PDT 24 Aug 19 05:04:14 PM PDT 24 18405145 ps
T576 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3174857312 Aug 19 05:04:22 PM PDT 24 Aug 19 05:04:25 PM PDT 24 161185991 ps
T577 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3050206761 Aug 19 05:04:12 PM PDT 24 Aug 19 05:04:13 PM PDT 24 159046768 ps
T578 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2590589814 Aug 19 05:04:35 PM PDT 24 Aug 19 05:04:35 PM PDT 24 12561557 ps
T579 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.651904951 Aug 19 05:04:05 PM PDT 24 Aug 19 05:04:06 PM PDT 24 148994269 ps
T580 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2530502190 Aug 19 05:04:22 PM PDT 24 Aug 19 05:04:24 PM PDT 24 266222281 ps
T581 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3221787435 Aug 19 05:04:22 PM PDT 24 Aug 19 05:04:25 PM PDT 24 716455872 ps
T582 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2431442625 Aug 19 05:04:12 PM PDT 24 Aug 19 05:04:15 PM PDT 24 41247797 ps
T117 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2571805382 Aug 19 05:04:06 PM PDT 24 Aug 19 05:04:15 PM PDT 24 215775716 ps
T583 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1398452044 Aug 19 05:04:34 PM PDT 24 Aug 19 05:04:36 PM PDT 24 31802849 ps
T584 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2079264888 Aug 19 05:04:24 PM PDT 24 Aug 19 05:04:26 PM PDT 24 138289782 ps
T585 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2101568361 Aug 19 05:04:12 PM PDT 24 Aug 19 05:16:21 PM PDT 24 211451603697 ps
T586 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3079780345 Aug 19 05:04:34 PM PDT 24 Aug 19 05:04:35 PM PDT 24 16851713 ps
T587 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2562232170 Aug 19 05:04:25 PM PDT 24 Aug 19 05:04:26 PM PDT 24 11392982 ps
T588 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.371982762 Aug 19 05:04:04 PM PDT 24 Aug 19 05:04:05 PM PDT 24 54667864 ps
T589 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1197197393 Aug 19 05:04:11 PM PDT 24 Aug 19 05:04:13 PM PDT 24 188416672 ps
T590 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3199307639 Aug 19 05:04:36 PM PDT 24 Aug 19 05:04:37 PM PDT 24 11246755 ps
T118 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3735382798 Aug 19 05:04:10 PM PDT 24 Aug 19 05:04:16 PM PDT 24 742120318 ps
T591 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1083405892 Aug 19 05:04:15 PM PDT 24 Aug 19 05:04:19 PM PDT 24 72941719 ps
T592 /workspace/coverage/cover_reg_top/33.hmac_intr_test.922525307 Aug 19 05:04:34 PM PDT 24 Aug 19 05:04:35 PM PDT 24 67130745 ps
T119 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2911202733 Aug 19 05:04:26 PM PDT 24 Aug 19 05:04:27 PM PDT 24 91043601 ps
T593 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.4237965662 Aug 19 05:04:19 PM PDT 24 Aug 19 05:04:26 PM PDT 24 970098045 ps
T594 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1527498539 Aug 19 05:04:35 PM PDT 24 Aug 19 05:04:36 PM PDT 24 67434398 ps
T595 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1270046274 Aug 19 05:04:22 PM PDT 24 Aug 19 05:04:25 PM PDT 24 93337190 ps
T596 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.4070166812 Aug 19 05:04:29 PM PDT 24 Aug 19 05:04:31 PM PDT 24 72845827 ps
T597 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1400347169 Aug 19 05:04:23 PM PDT 24 Aug 19 05:04:24 PM PDT 24 95911764 ps
T598 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1819123034 Aug 19 05:04:18 PM PDT 24 Aug 19 05:04:19 PM PDT 24 90707960 ps
T599 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2579961932 Aug 19 05:04:22 PM PDT 24 Aug 19 05:04:26 PM PDT 24 715599155 ps
T140 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2064400590 Aug 19 05:04:10 PM PDT 24 Aug 19 05:04:15 PM PDT 24 1662418647 ps
T600 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3544343120 Aug 19 05:04:25 PM PDT 24 Aug 19 05:04:27 PM PDT 24 67195039 ps
T601 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2621039506 Aug 19 05:04:11 PM PDT 24 Aug 19 05:04:11 PM PDT 24 11785437 ps
T602 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3182794613 Aug 19 05:04:30 PM PDT 24 Aug 19 05:04:31 PM PDT 24 90074496 ps
T603 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1125499414 Aug 19 05:04:34 PM PDT 24 Aug 19 05:04:34 PM PDT 24 36210233 ps
T604 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3363321957 Aug 19 05:04:26 PM PDT 24 Aug 19 05:04:28 PM PDT 24 30177763 ps
T605 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.310307561 Aug 19 05:04:27 PM PDT 24 Aug 19 05:04:31 PM PDT 24 199784037 ps
T606 /workspace/coverage/cover_reg_top/13.hmac_intr_test.352692176 Aug 19 05:04:24 PM PDT 24 Aug 19 05:04:25 PM PDT 24 30535889 ps
T607 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1369286340 Aug 19 05:04:28 PM PDT 24 Aug 19 05:04:31 PM PDT 24 177730734 ps
T608 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3247674573 Aug 19 05:04:25 PM PDT 24 Aug 19 05:04:28 PM PDT 24 172185828 ps
T609 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1474180362 Aug 19 05:04:29 PM PDT 24 Aug 19 05:04:30 PM PDT 24 14791157 ps
T610 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2021776658 Aug 19 05:04:26 PM PDT 24 Aug 19 05:04:27 PM PDT 24 30559880 ps
T611 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2721867693 Aug 19 05:04:22 PM PDT 24 Aug 19 05:04:23 PM PDT 24 47021239 ps
T612 /workspace/coverage/cover_reg_top/17.hmac_intr_test.694312630 Aug 19 05:04:24 PM PDT 24 Aug 19 05:04:25 PM PDT 24 17658351 ps
T613 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1422135131 Aug 19 05:04:22 PM PDT 24 Aug 19 05:04:33 PM PDT 24 1868136036 ps
T614 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.141771573 Aug 19 05:04:22 PM PDT 24 Aug 19 05:04:23 PM PDT 24 37765548 ps
T615 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.330423102 Aug 19 05:04:22 PM PDT 24 Aug 19 05:04:24 PM PDT 24 120808377 ps
T616 /workspace/coverage/cover_reg_top/9.hmac_intr_test.4067785807 Aug 19 05:04:24 PM PDT 24 Aug 19 05:04:25 PM PDT 24 21590994 ps
T617 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3995369643 Aug 19 05:04:15 PM PDT 24 Aug 19 05:04:19 PM PDT 24 1601452840 ps
T618 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4253056965 Aug 19 05:04:26 PM PDT 24 Aug 19 05:04:29 PM PDT 24 146698292 ps
T619 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.484774058 Aug 19 05:04:22 PM PDT 24 Aug 19 05:04:25 PM PDT 24 486803027 ps
T620 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1102286024 Aug 19 05:04:33 PM PDT 24 Aug 19 05:04:33 PM PDT 24 42433302 ps
T621 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.4273968601 Aug 19 05:04:23 PM PDT 24 Aug 19 05:04:25 PM PDT 24 45504555 ps
T622 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2033706427 Aug 19 05:04:46 PM PDT 24 Aug 19 05:04:47 PM PDT 24 14048663 ps
T623 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1047864706 Aug 19 05:04:22 PM PDT 24 Aug 19 05:04:26 PM PDT 24 243212259 ps
T624 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3593182014 Aug 19 05:04:33 PM PDT 24 Aug 19 05:04:34 PM PDT 24 14273916 ps
T625 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1260756898 Aug 19 05:04:16 PM PDT 24 Aug 19 05:04:17 PM PDT 24 21254116 ps
T626 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3455998699 Aug 19 05:04:35 PM PDT 24 Aug 19 05:04:36 PM PDT 24 12178484 ps
T627 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3104809081 Aug 19 05:04:24 PM PDT 24 Aug 19 05:04:25 PM PDT 24 16478577 ps
T628 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3360683816 Aug 19 05:04:20 PM PDT 24 Aug 19 05:04:22 PM PDT 24 36187238 ps
T629 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1616129350 Aug 19 05:04:32 PM PDT 24 Aug 19 05:04:34 PM PDT 24 35258144 ps
T630 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1685008246 Aug 19 05:04:51 PM PDT 24 Aug 19 05:04:52 PM PDT 24 49831338 ps
T631 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3648357817 Aug 19 05:04:26 PM PDT 24 Aug 19 05:04:28 PM PDT 24 139892275 ps
T632 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.4079055709 Aug 19 05:04:30 PM PDT 24 Aug 19 05:04:31 PM PDT 24 78360849 ps
T633 /workspace/coverage/cover_reg_top/30.hmac_intr_test.308596470 Aug 19 05:04:37 PM PDT 24 Aug 19 05:04:38 PM PDT 24 12744727 ps
T634 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3741177357 Aug 19 05:04:50 PM PDT 24 Aug 19 05:04:51 PM PDT 24 19923218 ps
T635 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2195345137 Aug 19 05:04:23 PM PDT 24 Aug 19 05:04:24 PM PDT 24 19739869 ps
T636 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2826322746 Aug 19 05:04:26 PM PDT 24 Aug 19 05:04:27 PM PDT 24 33388932 ps
T637 /workspace/coverage/cover_reg_top/0.hmac_intr_test.965191426 Aug 19 05:04:05 PM PDT 24 Aug 19 05:04:06 PM PDT 24 22960686 ps
T638 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3445844483 Aug 19 05:04:35 PM PDT 24 Aug 19 05:04:36 PM PDT 24 40223057 ps
T639 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2753062049 Aug 19 05:04:26 PM PDT 24 Aug 19 05:04:30 PM PDT 24 58485270 ps
T640 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2933905098 Aug 19 05:04:20 PM PDT 24 Aug 19 05:04:23 PM PDT 24 88306141 ps
T641 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1227712696 Aug 19 05:04:49 PM PDT 24 Aug 19 05:04:50 PM PDT 24 81854678 ps
T642 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2537887258 Aug 19 05:04:12 PM PDT 24 Aug 19 05:04:14 PM PDT 24 28554623 ps
T643 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1967299747 Aug 19 05:04:22 PM PDT 24 Aug 19 05:04:23 PM PDT 24 117837400 ps
T644 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1484529808 Aug 19 05:04:23 PM PDT 24 Aug 19 05:04:25 PM PDT 24 84947385 ps
T645 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1727104786 Aug 19 05:04:25 PM PDT 24 Aug 19 05:04:27 PM PDT 24 167203036 ps
T646 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1303328071 Aug 19 05:04:32 PM PDT 24 Aug 19 05:04:32 PM PDT 24 29218485 ps
T647 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.176577521 Aug 19 05:04:21 PM PDT 24 Aug 19 05:04:23 PM PDT 24 65159170 ps
T648 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1578109741 Aug 19 05:04:12 PM PDT 24 Aug 19 05:04:14 PM PDT 24 161702544 ps
T649 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.969170698 Aug 19 05:04:24 PM PDT 24 Aug 19 05:04:26 PM PDT 24 60265377 ps
T650 /workspace/coverage/cover_reg_top/8.hmac_intr_test.464681273 Aug 19 05:04:25 PM PDT 24 Aug 19 05:04:25 PM PDT 24 22639562 ps
T651 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1848414788 Aug 19 05:04:23 PM PDT 24 Aug 19 05:14:00 PM PDT 24 309132719546 ps
T138 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1218526109 Aug 19 05:04:12 PM PDT 24 Aug 19 05:04:15 PM PDT 24 102060965 ps
T652 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2764614414 Aug 19 05:04:26 PM PDT 24 Aug 19 05:04:27 PM PDT 24 15692542 ps
T653 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2085677808 Aug 19 05:04:34 PM PDT 24 Aug 19 05:04:35 PM PDT 24 12621861 ps
T654 /workspace/coverage/cover_reg_top/26.hmac_intr_test.4069852581 Aug 19 05:04:36 PM PDT 24 Aug 19 05:04:36 PM PDT 24 15570481 ps
T139 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.29171440 Aug 19 05:04:34 PM PDT 24 Aug 19 05:04:37 PM PDT 24 165815296 ps
T655 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3305984576 Aug 19 05:04:21 PM PDT 24 Aug 19 05:04:22 PM PDT 24 19176189 ps
T656 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2972934390 Aug 19 05:04:21 PM PDT 24 Aug 19 05:04:23 PM PDT 24 46651077 ps
T657 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2062885797 Aug 19 05:04:25 PM PDT 24 Aug 19 05:04:28 PM PDT 24 160073612 ps

Test location /workspace/coverage/default/34.hmac_back_pressure.2839361758
Short name T5
Test name
Test status
Simulation time 6072954785 ps
CPU time 92.59 seconds
Started Aug 19 05:11:57 PM PDT 24
Finished Aug 19 05:13:29 PM PDT 24
Peak memory 217100 kb
Host smart-3ea93006-2211-486a-b6d1-3bcd301b64de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2839361758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2839361758
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3077855004
Short name T19
Test name
Test status
Simulation time 91898376202 ps
CPU time 2510.13 seconds
Started Aug 19 05:12:00 PM PDT 24
Finished Aug 19 05:53:50 PM PDT 24
Peak memory 799072 kb
Host smart-a2addc56-2494-4da4-9039-88c2b53b6181
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077855004 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3077855004
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.708754453
Short name T7
Test name
Test status
Simulation time 9503984037 ps
CPU time 223.97 seconds
Started Aug 19 05:11:06 PM PDT 24
Finished Aug 19 05:14:50 PM PDT 24
Peak memory 451668 kb
Host smart-554438a6-b09e-47c8-8b81-47bad0804541
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=708754453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.708754453
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3341803895
Short name T134
Test name
Test status
Simulation time 225568718 ps
CPU time 4.63 seconds
Started Aug 19 05:04:25 PM PDT 24
Finished Aug 19 05:04:30 PM PDT 24
Peak memory 200284 kb
Host smart-3fba3368-3384-4c2a-9055-fca35a4cd900
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341803895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3341803895
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.2485955931
Short name T23
Test name
Test status
Simulation time 36271422517 ps
CPU time 882.75 seconds
Started Aug 19 05:11:06 PM PDT 24
Finished Aug 19 05:25:49 PM PDT 24
Peak memory 683060 kb
Host smart-1b622539-a454-4b23-a72b-baa57c5780ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2485955931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.2485955931
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_stress_all.313247493
Short name T6
Test name
Test status
Simulation time 47106758032 ps
CPU time 1831.78 seconds
Started Aug 19 05:11:39 PM PDT 24
Finished Aug 19 05:42:11 PM PDT 24
Peak memory 784224 kb
Host smart-3ec7a139-16ee-4774-be96-9d34bd0cd608
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313247493 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.313247493
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.297068212
Short name T14
Test name
Test status
Simulation time 144870085 ps
CPU time 0.97 seconds
Started Aug 19 05:11:02 PM PDT 24
Finished Aug 19 05:11:04 PM PDT 24
Peak memory 219028 kb
Host smart-593c7d6b-58fa-44c6-8dd1-19dd16995599
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297068212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.297068212
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.293572586
Short name T106
Test name
Test status
Simulation time 134964245 ps
CPU time 0.8 seconds
Started Aug 19 05:04:37 PM PDT 24
Finished Aug 19 05:04:38 PM PDT 24
Peak memory 199988 kb
Host smart-f07ad0a9-df6a-40ee-a57f-231dd7c122f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293572586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.293572586
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.710648156
Short name T12
Test name
Test status
Simulation time 1384744305 ps
CPU time 82.34 seconds
Started Aug 19 05:11:00 PM PDT 24
Finished Aug 19 05:12:22 PM PDT 24
Peak memory 200636 kb
Host smart-43691068-3f90-445d-9abd-14fba9866e16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=710648156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.710648156
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3508265838
Short name T151
Test name
Test status
Simulation time 105580183603 ps
CPU time 3309.33 seconds
Started Aug 19 05:11:37 PM PDT 24
Finished Aug 19 06:06:46 PM PDT 24
Peak memory 787468 kb
Host smart-c462ccf9-f619-4a6a-a910-e011eb9a1198
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508265838 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3508265838
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1983332385
Short name T137
Test name
Test status
Simulation time 1847665100 ps
CPU time 4.56 seconds
Started Aug 19 05:04:05 PM PDT 24
Finished Aug 19 05:04:10 PM PDT 24
Peak memory 200312 kb
Host smart-c910401b-8356-4e63-b448-495c09e76d55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983332385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1983332385
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3318220628
Short name T62
Test name
Test status
Simulation time 54703535 ps
CPU time 0.6 seconds
Started Aug 19 05:11:30 PM PDT 24
Finished Aug 19 05:11:31 PM PDT 24
Peak memory 196760 kb
Host smart-d87c5b28-4e6d-4f0f-9458-af174aa8335b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318220628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3318220628
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2802611528
Short name T86
Test name
Test status
Simulation time 137671383465 ps
CPU time 1766.63 seconds
Started Aug 19 05:11:28 PM PDT 24
Finished Aug 19 05:40:54 PM PDT 24
Peak memory 742368 kb
Host smart-4dfcda18-a35e-477a-b873-74db95db92a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802611528 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2802611528
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1172939282
Short name T4
Test name
Test status
Simulation time 4308150026 ps
CPU time 46.28 seconds
Started Aug 19 05:11:31 PM PDT 24
Finished Aug 19 05:12:17 PM PDT 24
Peak memory 216940 kb
Host smart-77f9ac2f-f352-46b6-a747-04a681b9cd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172939282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1172939282
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1218526109
Short name T138
Test name
Test status
Simulation time 102060965 ps
CPU time 1.9 seconds
Started Aug 19 05:04:12 PM PDT 24
Finished Aug 19 05:04:15 PM PDT 24
Peak memory 200364 kb
Host smart-a7c8d1e6-53ff-4220-a77c-402699c40046
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218526109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1218526109
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.770587367
Short name T391
Test name
Test status
Simulation time 37675679739 ps
CPU time 701.21 seconds
Started Aug 19 05:10:49 PM PDT 24
Finished Aug 19 05:22:30 PM PDT 24
Peak memory 200664 kb
Host smart-2d01b537-c6e1-4fc8-9f78-eff69bcf1e05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=770587367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.770587367
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2538472952
Short name T56
Test name
Test status
Simulation time 12155803264 ps
CPU time 1908.93 seconds
Started Aug 19 05:11:10 PM PDT 24
Finished Aug 19 05:42:59 PM PDT 24
Peak memory 759360 kb
Host smart-4f9bad68-413e-432c-9d0e-2682c9da4357
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538472952 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2538472952
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.2165217454
Short name T9
Test name
Test status
Simulation time 6439314177 ps
CPU time 157.12 seconds
Started Aug 19 05:10:49 PM PDT 24
Finished Aug 19 05:13:26 PM PDT 24
Peak memory 556848 kb
Host smart-aab9710d-d7ae-4d45-8ce8-2fe24bd75561
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2165217454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.2165217454
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1440641080
Short name T113
Test name
Test status
Simulation time 2497647567 ps
CPU time 8.49 seconds
Started Aug 19 05:04:16 PM PDT 24
Finished Aug 19 05:04:25 PM PDT 24
Peak memory 200396 kb
Host smart-0d44ab29-c88d-4403-9757-dad1074c1c05
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440641080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1440641080
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2571805382
Short name T117
Test name
Test status
Simulation time 215775716 ps
CPU time 9.32 seconds
Started Aug 19 05:04:06 PM PDT 24
Finished Aug 19 05:04:15 PM PDT 24
Peak memory 200264 kb
Host smart-cbed0691-e754-4271-ad97-beed1904d55d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571805382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2571805382
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.651904951
Short name T579
Test name
Test status
Simulation time 148994269 ps
CPU time 1.04 seconds
Started Aug 19 05:04:05 PM PDT 24
Finished Aug 19 05:04:06 PM PDT 24
Peak memory 199948 kb
Host smart-9132470e-ee7e-46b8-9ad3-3c4850ed9f10
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651904951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.651904951
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1197197393
Short name T589
Test name
Test status
Simulation time 188416672 ps
CPU time 1.84 seconds
Started Aug 19 05:04:11 PM PDT 24
Finished Aug 19 05:04:13 PM PDT 24
Peak memory 200432 kb
Host smart-5d06025b-b42e-41ce-9430-459ecc390230
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197197393 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1197197393
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.371982762
Short name T588
Test name
Test status
Simulation time 54667864 ps
CPU time 0.78 seconds
Started Aug 19 05:04:04 PM PDT 24
Finished Aug 19 05:04:05 PM PDT 24
Peak memory 199284 kb
Host smart-0228bc2b-a768-4470-9993-e702247377e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371982762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.371982762
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.965191426
Short name T637
Test name
Test status
Simulation time 22960686 ps
CPU time 0.61 seconds
Started Aug 19 05:04:05 PM PDT 24
Finished Aug 19 05:04:06 PM PDT 24
Peak memory 195352 kb
Host smart-91cbe07b-f5e8-46a7-ad9f-02bd44bada57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965191426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.965191426
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1578109741
Short name T648
Test name
Test status
Simulation time 161702544 ps
CPU time 1.06 seconds
Started Aug 19 05:04:12 PM PDT 24
Finished Aug 19 05:04:14 PM PDT 24
Peak memory 200292 kb
Host smart-cd377279-aafc-44af-b995-ffd77c622bec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578109741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1578109741
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1731095745
Short name T557
Test name
Test status
Simulation time 162240996 ps
CPU time 3.63 seconds
Started Aug 19 05:04:04 PM PDT 24
Finished Aug 19 05:04:08 PM PDT 24
Peak memory 200320 kb
Host smart-a183dc8d-4d73-4aea-b007-f0b0648c2811
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731095745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1731095745
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.4237965662
Short name T593
Test name
Test status
Simulation time 970098045 ps
CPU time 6.36 seconds
Started Aug 19 05:04:19 PM PDT 24
Finished Aug 19 05:04:26 PM PDT 24
Peak memory 200252 kb
Host smart-1bf4359d-3830-40e8-aa2a-6a758bc4c6b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237965662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.4237965662
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1331911972
Short name T112
Test name
Test status
Simulation time 1230086187 ps
CPU time 14.31 seconds
Started Aug 19 05:04:15 PM PDT 24
Finished Aug 19 05:04:30 PM PDT 24
Peak memory 200160 kb
Host smart-2919a347-c916-47bf-a7b5-97c3c1c6fa1f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331911972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1331911972
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1260756898
Short name T625
Test name
Test status
Simulation time 21254116 ps
CPU time 0.74 seconds
Started Aug 19 05:04:16 PM PDT 24
Finished Aug 19 05:04:17 PM PDT 24
Peak memory 198412 kb
Host smart-809a203c-98b8-43d1-8535-80deb1bee930
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260756898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1260756898
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3579167208
Short name T544
Test name
Test status
Simulation time 20764303958 ps
CPU time 192.94 seconds
Started Aug 19 05:04:15 PM PDT 24
Finished Aug 19 05:07:28 PM PDT 24
Peak memory 216820 kb
Host smart-d0246927-5246-4a21-bf76-bf7f1cdd4488
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579167208 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3579167208
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1713694592
Short name T575
Test name
Test status
Simulation time 18405145 ps
CPU time 0.9 seconds
Started Aug 19 05:04:13 PM PDT 24
Finished Aug 19 05:04:14 PM PDT 24
Peak memory 199848 kb
Host smart-61692f4b-d158-4c69-ba6e-2367486797ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713694592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1713694592
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2956886228
Short name T546
Test name
Test status
Simulation time 13404186 ps
CPU time 0.58 seconds
Started Aug 19 05:04:11 PM PDT 24
Finished Aug 19 05:04:11 PM PDT 24
Peak memory 195276 kb
Host smart-9c6464af-da1f-4e99-ae6c-59b77ba3db72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956886228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2956886228
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.330423102
Short name T615
Test name
Test status
Simulation time 120808377 ps
CPU time 1.72 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:04:24 PM PDT 24
Peak memory 200332 kb
Host smart-085b7cb9-fa56-4595-af17-9c13575a4b14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330423102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.330423102
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.440336189
Short name T548
Test name
Test status
Simulation time 1259158821 ps
CPU time 4.17 seconds
Started Aug 19 05:04:14 PM PDT 24
Finished Aug 19 05:04:18 PM PDT 24
Peak memory 200288 kb
Host smart-d8f56f44-d582-4df2-a7d4-838e8a7a789b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440336189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.440336189
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1727104786
Short name T645
Test name
Test status
Simulation time 167203036 ps
CPU time 2.48 seconds
Started Aug 19 05:04:25 PM PDT 24
Finished Aug 19 05:04:27 PM PDT 24
Peak memory 200384 kb
Host smart-9483f5a1-7482-404b-b664-0211cbe09446
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727104786 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1727104786
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.4205686005
Short name T566
Test name
Test status
Simulation time 15185422 ps
CPU time 0.7 seconds
Started Aug 19 05:04:27 PM PDT 24
Finished Aug 19 05:04:28 PM PDT 24
Peak memory 198656 kb
Host smart-e55e0a4d-979c-43b6-a9f0-ec7d2e2eb6fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205686005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.4205686005
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2562232170
Short name T587
Test name
Test status
Simulation time 11392982 ps
CPU time 0.59 seconds
Started Aug 19 05:04:25 PM PDT 24
Finished Aug 19 05:04:26 PM PDT 24
Peak memory 195464 kb
Host smart-8b663156-b2dc-462b-a4be-b3f972319d8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562232170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2562232170
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2062885797
Short name T657
Test name
Test status
Simulation time 160073612 ps
CPU time 2.08 seconds
Started Aug 19 05:04:25 PM PDT 24
Finished Aug 19 05:04:28 PM PDT 24
Peak memory 200276 kb
Host smart-0798296f-881d-449c-8052-21881aa10777
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062885797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2062885797
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1158403490
Short name T553
Test name
Test status
Simulation time 168021270 ps
CPU time 1.82 seconds
Started Aug 19 05:04:25 PM PDT 24
Finished Aug 19 05:04:27 PM PDT 24
Peak memory 200368 kb
Host smart-3bf96a44-9dda-4b99-9e90-385e6288c0c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158403490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1158403490
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2101338823
Short name T69
Test name
Test status
Simulation time 52537716 ps
CPU time 1.84 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:04:24 PM PDT 24
Peak memory 200236 kb
Host smart-2707ba16-9a67-4f97-a666-f8111428cbc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101338823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2101338823
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.4273968601
Short name T621
Test name
Test status
Simulation time 45504555 ps
CPU time 1.48 seconds
Started Aug 19 05:04:23 PM PDT 24
Finished Aug 19 05:04:25 PM PDT 24
Peak memory 200332 kb
Host smart-b8cb59ee-92d5-4d41-97e6-2725b4897db2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273968601 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.4273968601
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2911202733
Short name T119
Test name
Test status
Simulation time 91043601 ps
CPU time 0.82 seconds
Started Aug 19 05:04:26 PM PDT 24
Finished Aug 19 05:04:27 PM PDT 24
Peak memory 199688 kb
Host smart-379736e7-0d0f-48fd-b659-09af7e8ce157
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911202733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2911202733
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3296238710
Short name T545
Test name
Test status
Simulation time 57346822 ps
CPU time 0.59 seconds
Started Aug 19 05:04:24 PM PDT 24
Finished Aug 19 05:04:25 PM PDT 24
Peak memory 195268 kb
Host smart-7901febb-8591-4fb0-86f0-3700af95c820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296238710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3296238710
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1470268743
Short name T125
Test name
Test status
Simulation time 171530754 ps
CPU time 1.71 seconds
Started Aug 19 05:04:26 PM PDT 24
Finished Aug 19 05:04:28 PM PDT 24
Peak memory 200216 kb
Host smart-7021ac77-74fa-4e61-aca7-656c05ed7f39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470268743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1470268743
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1897248766
Short name T562
Test name
Test status
Simulation time 168843934 ps
CPU time 1.89 seconds
Started Aug 19 05:04:24 PM PDT 24
Finished Aug 19 05:04:27 PM PDT 24
Peak memory 200300 kb
Host smart-87d18c56-d8cf-4c4d-a2af-79b9b62c2f27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897248766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1897248766
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1935334350
Short name T568
Test name
Test status
Simulation time 165143970 ps
CPU time 1.84 seconds
Started Aug 19 05:04:21 PM PDT 24
Finished Aug 19 05:04:23 PM PDT 24
Peak memory 200348 kb
Host smart-52501a3b-f853-47a9-8cde-1635a1412585
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935334350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1935334350
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1243150723
Short name T573
Test name
Test status
Simulation time 213715320 ps
CPU time 3.5 seconds
Started Aug 19 05:04:25 PM PDT 24
Finished Aug 19 05:04:28 PM PDT 24
Peak memory 200316 kb
Host smart-978d2c6c-d662-4c37-8f96-56f1df4004ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243150723 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1243150723
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2975715669
Short name T570
Test name
Test status
Simulation time 106475082 ps
CPU time 0.92 seconds
Started Aug 19 05:04:25 PM PDT 24
Finished Aug 19 05:04:26 PM PDT 24
Peak memory 199612 kb
Host smart-d7a9e234-5beb-48d0-8429-fa1fb0a8280b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975715669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2975715669
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2721867693
Short name T611
Test name
Test status
Simulation time 47021239 ps
CPU time 0.62 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:04:23 PM PDT 24
Peak memory 195424 kb
Host smart-b9c9dade-c515-4566-a505-5c1db4c64fdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721867693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2721867693
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1549416823
Short name T121
Test name
Test status
Simulation time 216451245 ps
CPU time 1.81 seconds
Started Aug 19 05:04:24 PM PDT 24
Finished Aug 19 05:04:26 PM PDT 24
Peak memory 200316 kb
Host smart-3fcc40b3-c4ba-48f5-ac05-7290800abeea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549416823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1549416823
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1270046274
Short name T595
Test name
Test status
Simulation time 93337190 ps
CPU time 2.14 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:04:25 PM PDT 24
Peak memory 200256 kb
Host smart-c66ade07-601a-4f09-b377-043715cdea01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270046274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1270046274
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1794985239
Short name T135
Test name
Test status
Simulation time 346783560 ps
CPU time 4.34 seconds
Started Aug 19 05:04:24 PM PDT 24
Finished Aug 19 05:04:29 PM PDT 24
Peak memory 200364 kb
Host smart-6e77977c-f8c8-417d-9bc6-cdfa1450968b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794985239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1794985239
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2079264888
Short name T584
Test name
Test status
Simulation time 138289782 ps
CPU time 2.33 seconds
Started Aug 19 05:04:24 PM PDT 24
Finished Aug 19 05:04:26 PM PDT 24
Peak memory 208428 kb
Host smart-71a2301e-deac-401b-9bc4-4ec146db7f83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079264888 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2079264888
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1331622070
Short name T549
Test name
Test status
Simulation time 51965620 ps
CPU time 0.7 seconds
Started Aug 19 05:04:25 PM PDT 24
Finished Aug 19 05:04:26 PM PDT 24
Peak memory 198168 kb
Host smart-03797d79-9692-4e5f-9501-b3b412334712
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331622070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1331622070
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.352692176
Short name T606
Test name
Test status
Simulation time 30535889 ps
CPU time 0.58 seconds
Started Aug 19 05:04:24 PM PDT 24
Finished Aug 19 05:04:25 PM PDT 24
Peak memory 195248 kb
Host smart-87ab3c59-6931-4ae5-b481-3a8ff23b7dbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352692176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.352692176
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2296477443
Short name T571
Test name
Test status
Simulation time 148202503 ps
CPU time 2.34 seconds
Started Aug 19 05:04:23 PM PDT 24
Finished Aug 19 05:04:26 PM PDT 24
Peak memory 200252 kb
Host smart-65c5f2d7-3752-471c-94cd-216d040e1049
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296477443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2296477443
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.843465550
Short name T555
Test name
Test status
Simulation time 376125791 ps
CPU time 2.46 seconds
Started Aug 19 05:04:25 PM PDT 24
Finished Aug 19 05:04:28 PM PDT 24
Peak memory 200324 kb
Host smart-3424bb64-1666-497f-bd2b-9af80dc29d87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843465550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.843465550
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1412850677
Short name T565
Test name
Test status
Simulation time 193004934 ps
CPU time 1.65 seconds
Started Aug 19 05:04:23 PM PDT 24
Finished Aug 19 05:04:25 PM PDT 24
Peak memory 200296 kb
Host smart-17259005-7fa9-41ed-b7b3-80898caf34e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412850677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1412850677
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2753062049
Short name T639
Test name
Test status
Simulation time 58485270 ps
CPU time 3.68 seconds
Started Aug 19 05:04:26 PM PDT 24
Finished Aug 19 05:04:30 PM PDT 24
Peak memory 208464 kb
Host smart-ca7163dc-eee9-4faa-92c9-34205bd58d6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753062049 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2753062049
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.449550643
Short name T110
Test name
Test status
Simulation time 116986541 ps
CPU time 0.94 seconds
Started Aug 19 05:04:27 PM PDT 24
Finished Aug 19 05:04:28 PM PDT 24
Peak memory 200056 kb
Host smart-49057ab9-6343-43d7-887e-ea63aa0d5950
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449550643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.449550643
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1799901378
Short name T539
Test name
Test status
Simulation time 40722994 ps
CPU time 0.56 seconds
Started Aug 19 05:04:27 PM PDT 24
Finished Aug 19 05:04:27 PM PDT 24
Peak memory 195284 kb
Host smart-c2091f07-65eb-49a8-a378-e822cc2ecbd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799901378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1799901378
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3648357817
Short name T631
Test name
Test status
Simulation time 139892275 ps
CPU time 1.58 seconds
Started Aug 19 05:04:26 PM PDT 24
Finished Aug 19 05:04:28 PM PDT 24
Peak memory 200332 kb
Host smart-f4c65a7e-8418-42f7-b6d0-d9c4f0ffc24d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648357817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3648357817
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1047864706
Short name T623
Test name
Test status
Simulation time 243212259 ps
CPU time 4.31 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:04:26 PM PDT 24
Peak memory 200264 kb
Host smart-bf6e01a4-9ac6-457e-9acb-a935dd058ac5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047864706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1047864706
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1764964804
Short name T136
Test name
Test status
Simulation time 771788495 ps
CPU time 4.09 seconds
Started Aug 19 05:04:27 PM PDT 24
Finished Aug 19 05:04:31 PM PDT 24
Peak memory 200240 kb
Host smart-daa4c7e8-0f37-4022-bc73-d738cea5c40f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764964804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1764964804
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1973029460
Short name T559
Test name
Test status
Simulation time 357573420647 ps
CPU time 766.39 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:17:09 PM PDT 24
Peak memory 216852 kb
Host smart-358c4b35-c320-498f-b3fd-daf8da7b66f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973029460 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1973029460
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1198248446
Short name T114
Test name
Test status
Simulation time 16658872 ps
CPU time 0.89 seconds
Started Aug 19 05:04:25 PM PDT 24
Finished Aug 19 05:04:26 PM PDT 24
Peak memory 199940 kb
Host smart-cebfef23-e7ca-466d-80fe-a058592b0951
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198248446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1198248446
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1474180362
Short name T609
Test name
Test status
Simulation time 14791157 ps
CPU time 0.58 seconds
Started Aug 19 05:04:29 PM PDT 24
Finished Aug 19 05:04:30 PM PDT 24
Peak memory 195312 kb
Host smart-74baa971-5dfc-41ed-83ff-8ab755c7daa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474180362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1474180362
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4253056965
Short name T618
Test name
Test status
Simulation time 146698292 ps
CPU time 2.54 seconds
Started Aug 19 05:04:26 PM PDT 24
Finished Aug 19 05:04:29 PM PDT 24
Peak memory 200236 kb
Host smart-c266ef80-3ec8-4a43-bb81-afb9d309db6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253056965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.4253056965
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.310307561
Short name T605
Test name
Test status
Simulation time 199784037 ps
CPU time 4.13 seconds
Started Aug 19 05:04:27 PM PDT 24
Finished Aug 19 05:04:31 PM PDT 24
Peak memory 200276 kb
Host smart-3f2c51f1-2b8c-44d1-8dd3-0701926568d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310307561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.310307561
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4004696530
Short name T99
Test name
Test status
Simulation time 89699445 ps
CPU time 2.95 seconds
Started Aug 19 05:04:32 PM PDT 24
Finished Aug 19 05:04:35 PM PDT 24
Peak memory 208496 kb
Host smart-1449e798-71e2-4022-a5d7-65206d96ff84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004696530 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.4004696530
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.4079055709
Short name T632
Test name
Test status
Simulation time 78360849 ps
CPU time 0.83 seconds
Started Aug 19 05:04:30 PM PDT 24
Finished Aug 19 05:04:31 PM PDT 24
Peak memory 200060 kb
Host smart-6ed918e1-9e2c-4871-bbaa-ad15da15102c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079055709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.4079055709
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2826322746
Short name T636
Test name
Test status
Simulation time 33388932 ps
CPU time 0.6 seconds
Started Aug 19 05:04:26 PM PDT 24
Finished Aug 19 05:04:27 PM PDT 24
Peak memory 195368 kb
Host smart-43256da6-636e-4189-8ae1-83a8458d3d09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826322746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2826322746
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1616129350
Short name T629
Test name
Test status
Simulation time 35258144 ps
CPU time 1.63 seconds
Started Aug 19 05:04:32 PM PDT 24
Finished Aug 19 05:04:34 PM PDT 24
Peak memory 200300 kb
Host smart-f873eae8-a625-477a-8a2c-af64f3bb4ade
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616129350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1616129350
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2204865689
Short name T540
Test name
Test status
Simulation time 153724470 ps
CPU time 2.01 seconds
Started Aug 19 05:04:24 PM PDT 24
Finished Aug 19 05:04:27 PM PDT 24
Peak memory 200216 kb
Host smart-968e5a8e-3307-432e-92e9-7e0f2febc248
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204865689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2204865689
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.4070166812
Short name T596
Test name
Test status
Simulation time 72845827 ps
CPU time 1.72 seconds
Started Aug 19 05:04:29 PM PDT 24
Finished Aug 19 05:04:31 PM PDT 24
Peak memory 200272 kb
Host smart-410c7acd-8eff-4a6f-905c-e73437136d9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070166812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.4070166812
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.996831619
Short name T534
Test name
Test status
Simulation time 26834836 ps
CPU time 1.68 seconds
Started Aug 19 05:04:26 PM PDT 24
Finished Aug 19 05:04:28 PM PDT 24
Peak memory 200480 kb
Host smart-cc5ac3a2-5b41-4a48-bc26-f0bcfab00f68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996831619 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.996831619
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2195345137
Short name T635
Test name
Test status
Simulation time 19739869 ps
CPU time 1 seconds
Started Aug 19 05:04:23 PM PDT 24
Finished Aug 19 05:04:24 PM PDT 24
Peak memory 200076 kb
Host smart-f5802309-81af-4dbc-98dd-1e4f6eda587a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195345137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2195345137
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.694312630
Short name T612
Test name
Test status
Simulation time 17658351 ps
CPU time 0.61 seconds
Started Aug 19 05:04:24 PM PDT 24
Finished Aug 19 05:04:25 PM PDT 24
Peak memory 195236 kb
Host smart-593751f2-0d90-4520-8656-1865cd6bedcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694312630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.694312630
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2739950838
Short name T561
Test name
Test status
Simulation time 51775055 ps
CPU time 1.16 seconds
Started Aug 19 05:04:29 PM PDT 24
Finished Aug 19 05:04:30 PM PDT 24
Peak memory 200260 kb
Host smart-7e38200d-ee0c-449f-b664-263a9d2195c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739950838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2739950838
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3247674573
Short name T608
Test name
Test status
Simulation time 172185828 ps
CPU time 2.9 seconds
Started Aug 19 05:04:25 PM PDT 24
Finished Aug 19 05:04:28 PM PDT 24
Peak memory 200324 kb
Host smart-118d61f1-6ee4-458f-882b-b4dc52ca67fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247674573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3247674573
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3178475240
Short name T70
Test name
Test status
Simulation time 700371483 ps
CPU time 3.23 seconds
Started Aug 19 05:04:32 PM PDT 24
Finished Aug 19 05:04:35 PM PDT 24
Peak memory 200252 kb
Host smart-20bfd63d-90ab-4b70-a676-03102a373e52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178475240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3178475240
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3363321957
Short name T604
Test name
Test status
Simulation time 30177763 ps
CPU time 1.92 seconds
Started Aug 19 05:04:26 PM PDT 24
Finished Aug 19 05:04:28 PM PDT 24
Peak memory 200544 kb
Host smart-07dd74bf-253c-4fe3-b12a-09e1c19451b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363321957 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3363321957
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2764614414
Short name T652
Test name
Test status
Simulation time 15692542 ps
CPU time 0.68 seconds
Started Aug 19 05:04:26 PM PDT 24
Finished Aug 19 05:04:27 PM PDT 24
Peak memory 198536 kb
Host smart-854c9199-b55b-4600-82af-fb8736f13b46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764614414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2764614414
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1303328071
Short name T646
Test name
Test status
Simulation time 29218485 ps
CPU time 0.61 seconds
Started Aug 19 05:04:32 PM PDT 24
Finished Aug 19 05:04:32 PM PDT 24
Peak memory 195384 kb
Host smart-abe31514-d99a-4296-9099-1584c76bde97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303328071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1303328071
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3182794613
Short name T602
Test name
Test status
Simulation time 90074496 ps
CPU time 1.12 seconds
Started Aug 19 05:04:30 PM PDT 24
Finished Aug 19 05:04:31 PM PDT 24
Peak memory 198872 kb
Host smart-b6a36f65-e9fd-421e-b82c-b641f4b93226
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182794613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3182794613
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.243839300
Short name T75
Test name
Test status
Simulation time 316624516 ps
CPU time 3.36 seconds
Started Aug 19 05:04:28 PM PDT 24
Finished Aug 19 05:04:31 PM PDT 24
Peak memory 200308 kb
Host smart-ef83a8c1-7227-41bb-9f60-34b7ca048cc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243839300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.243839300
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1369286340
Short name T607
Test name
Test status
Simulation time 177730734 ps
CPU time 3.2 seconds
Started Aug 19 05:04:28 PM PDT 24
Finished Aug 19 05:04:31 PM PDT 24
Peak memory 200332 kb
Host smart-0d8a5e0a-3da2-434c-8e4a-0c4e1e339c39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369286340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1369286340
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3321292035
Short name T543
Test name
Test status
Simulation time 68459706 ps
CPU time 1.93 seconds
Started Aug 19 05:04:35 PM PDT 24
Finished Aug 19 05:04:37 PM PDT 24
Peak memory 200240 kb
Host smart-6392ac1b-b9ee-4887-97de-6c5e15929836
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321292035 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3321292035
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3593182014
Short name T624
Test name
Test status
Simulation time 14273916 ps
CPU time 0.62 seconds
Started Aug 19 05:04:33 PM PDT 24
Finished Aug 19 05:04:34 PM PDT 24
Peak memory 195408 kb
Host smart-cd07a35f-a93f-4332-af03-cbbc98b932ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593182014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3593182014
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1398452044
Short name T583
Test name
Test status
Simulation time 31802849 ps
CPU time 1.56 seconds
Started Aug 19 05:04:34 PM PDT 24
Finished Aug 19 05:04:36 PM PDT 24
Peak memory 200284 kb
Host smart-6985da55-0982-4b35-8658-afbe9ceb3515
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398452044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1398452044
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.847123560
Short name T537
Test name
Test status
Simulation time 151154724 ps
CPU time 2.94 seconds
Started Aug 19 05:04:33 PM PDT 24
Finished Aug 19 05:04:36 PM PDT 24
Peak memory 200288 kb
Host smart-23353122-cc59-4248-b42b-ba40b5a72a6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847123560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.847123560
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.29171440
Short name T139
Test name
Test status
Simulation time 165815296 ps
CPU time 2.98 seconds
Started Aug 19 05:04:34 PM PDT 24
Finished Aug 19 05:04:37 PM PDT 24
Peak memory 200304 kb
Host smart-2343e8c9-1476-486f-84d3-f6a345f13d77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29171440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.29171440
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3995369643
Short name T617
Test name
Test status
Simulation time 1601452840 ps
CPU time 3.47 seconds
Started Aug 19 05:04:15 PM PDT 24
Finished Aug 19 05:04:19 PM PDT 24
Peak memory 200260 kb
Host smart-92f121b5-8eaf-4942-9819-9a8f6cdd0b8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995369643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3995369643
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2892882285
Short name T541
Test name
Test status
Simulation time 7505558371 ps
CPU time 15.82 seconds
Started Aug 19 05:04:12 PM PDT 24
Finished Aug 19 05:04:27 PM PDT 24
Peak memory 200400 kb
Host smart-a063b959-95ce-421f-bedc-d23f134ab274
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892882285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2892882285
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.141771573
Short name T614
Test name
Test status
Simulation time 37765548 ps
CPU time 0.72 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:04:23 PM PDT 24
Peak memory 198036 kb
Host smart-0931cb32-1b1c-46e9-913d-78cd731a24d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141771573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.141771573
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2101568361
Short name T585
Test name
Test status
Simulation time 211451603697 ps
CPU time 728.12 seconds
Started Aug 19 05:04:12 PM PDT 24
Finished Aug 19 05:16:21 PM PDT 24
Peak memory 224996 kb
Host smart-57a7a67b-df7c-4326-b25f-8a7aceb1dda8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101568361 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2101568361
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.891997799
Short name T111
Test name
Test status
Simulation time 29130308 ps
CPU time 0.83 seconds
Started Aug 19 05:04:15 PM PDT 24
Finished Aug 19 05:04:16 PM PDT 24
Peak memory 199760 kb
Host smart-64727712-4b16-4d76-a563-e18ebe04c9bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891997799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.891997799
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.572333446
Short name T542
Test name
Test status
Simulation time 18404610 ps
CPU time 0.63 seconds
Started Aug 19 05:04:15 PM PDT 24
Finished Aug 19 05:04:16 PM PDT 24
Peak memory 195276 kb
Host smart-63aa2578-3f8d-4fb9-a820-305aa0adde58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572333446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.572333446
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2530502190
Short name T580
Test name
Test status
Simulation time 266222281 ps
CPU time 2.15 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:04:24 PM PDT 24
Peak memory 200344 kb
Host smart-b3a1b607-512c-491d-911c-266e51d29332
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530502190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2530502190
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.484774058
Short name T619
Test name
Test status
Simulation time 486803027 ps
CPU time 2.74 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:04:25 PM PDT 24
Peak memory 200248 kb
Host smart-bb62a4e2-6bde-4c16-a3af-66dfaea27667
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484774058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.484774058
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2970708748
Short name T133
Test name
Test status
Simulation time 573834432 ps
CPU time 2.89 seconds
Started Aug 19 05:04:12 PM PDT 24
Finished Aug 19 05:04:15 PM PDT 24
Peak memory 200368 kb
Host smart-d27f3e37-5854-43d5-b55e-6850b3c87068
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970708748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2970708748
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2590589814
Short name T578
Test name
Test status
Simulation time 12561557 ps
CPU time 0.58 seconds
Started Aug 19 05:04:35 PM PDT 24
Finished Aug 19 05:04:35 PM PDT 24
Peak memory 195264 kb
Host smart-cadf889f-28fb-48bb-8579-ee0574a0dda2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590589814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2590589814
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2575540007
Short name T563
Test name
Test status
Simulation time 17884480 ps
CPU time 0.6 seconds
Started Aug 19 05:04:37 PM PDT 24
Finished Aug 19 05:04:38 PM PDT 24
Peak memory 195276 kb
Host smart-7c2784cd-d086-4bdf-865d-d0f1f8cca68a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575540007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2575540007
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3445844483
Short name T638
Test name
Test status
Simulation time 40223057 ps
CPU time 0.59 seconds
Started Aug 19 05:04:35 PM PDT 24
Finished Aug 19 05:04:36 PM PDT 24
Peak memory 195252 kb
Host smart-b8ba6f81-09ab-4e03-a077-5c91f72914da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445844483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3445844483
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3650941720
Short name T550
Test name
Test status
Simulation time 12633142 ps
CPU time 0.58 seconds
Started Aug 19 05:04:35 PM PDT 24
Finished Aug 19 05:04:35 PM PDT 24
Peak memory 195232 kb
Host smart-54462fe8-382e-486e-903b-34b95f37fae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650941720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3650941720
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3079780345
Short name T586
Test name
Test status
Simulation time 16851713 ps
CPU time 0.62 seconds
Started Aug 19 05:04:34 PM PDT 24
Finished Aug 19 05:04:35 PM PDT 24
Peak memory 195196 kb
Host smart-4f23a143-705b-471b-8052-e2d27054a08b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079780345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3079780345
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1509980583
Short name T560
Test name
Test status
Simulation time 25573694 ps
CPU time 0.58 seconds
Started Aug 19 05:04:37 PM PDT 24
Finished Aug 19 05:04:37 PM PDT 24
Peak memory 195260 kb
Host smart-374db23f-d830-4cfb-a8f0-01ecc22cdd21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509980583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1509980583
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.4069852581
Short name T654
Test name
Test status
Simulation time 15570481 ps
CPU time 0.59 seconds
Started Aug 19 05:04:36 PM PDT 24
Finished Aug 19 05:04:36 PM PDT 24
Peak memory 195348 kb
Host smart-b0f266c7-4a74-42a7-9b64-44ccfe01c27b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069852581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.4069852581
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3455998699
Short name T626
Test name
Test status
Simulation time 12178484 ps
CPU time 0.61 seconds
Started Aug 19 05:04:35 PM PDT 24
Finished Aug 19 05:04:36 PM PDT 24
Peak memory 195332 kb
Host smart-f7fb58c1-d16d-41d2-8acd-2e3950a65cb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455998699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3455998699
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1125499414
Short name T603
Test name
Test status
Simulation time 36210233 ps
CPU time 0.66 seconds
Started Aug 19 05:04:34 PM PDT 24
Finished Aug 19 05:04:34 PM PDT 24
Peak memory 195332 kb
Host smart-f3f53d56-f4b6-4e08-8743-4f5013546cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125499414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1125499414
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3199307639
Short name T590
Test name
Test status
Simulation time 11246755 ps
CPU time 0.61 seconds
Started Aug 19 05:04:36 PM PDT 24
Finished Aug 19 05:04:37 PM PDT 24
Peak memory 195248 kb
Host smart-af28eddd-3799-4787-9fd1-edaf0550bf0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199307639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3199307639
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3450134882
Short name T115
Test name
Test status
Simulation time 313852251 ps
CPU time 3.32 seconds
Started Aug 19 05:04:12 PM PDT 24
Finished Aug 19 05:04:15 PM PDT 24
Peak memory 200196 kb
Host smart-485b3131-99a6-491c-974e-ea54431489bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450134882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3450134882
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1422135131
Short name T613
Test name
Test status
Simulation time 1868136036 ps
CPU time 10.75 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:04:33 PM PDT 24
Peak memory 200344 kb
Host smart-856fedcc-997d-439b-8b66-4e6213b6e4d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422135131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1422135131
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1899925500
Short name T108
Test name
Test status
Simulation time 21040047 ps
CPU time 0.97 seconds
Started Aug 19 05:04:11 PM PDT 24
Finished Aug 19 05:04:12 PM PDT 24
Peak memory 200112 kb
Host smart-70b8f37c-9704-459d-b193-bf9dcc93196a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899925500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1899925500
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2431442625
Short name T582
Test name
Test status
Simulation time 41247797 ps
CPU time 2.44 seconds
Started Aug 19 05:04:12 PM PDT 24
Finished Aug 19 05:04:15 PM PDT 24
Peak memory 200356 kb
Host smart-f964b0da-d601-4eb9-9efa-803a29c9fcd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431442625 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2431442625
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1728393352
Short name T109
Test name
Test status
Simulation time 128011561 ps
CPU time 0.98 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:04:23 PM PDT 24
Peak memory 199936 kb
Host smart-d9f9ffa4-7b96-4305-8281-2851388cd327
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728393352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1728393352
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.225718234
Short name T574
Test name
Test status
Simulation time 13653486 ps
CPU time 0.61 seconds
Started Aug 19 05:04:13 PM PDT 24
Finished Aug 19 05:04:13 PM PDT 24
Peak memory 195408 kb
Host smart-a7922447-1c7f-4c88-84de-e922e86121b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225718234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.225718234
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3050206761
Short name T577
Test name
Test status
Simulation time 159046768 ps
CPU time 1.11 seconds
Started Aug 19 05:04:12 PM PDT 24
Finished Aug 19 05:04:13 PM PDT 24
Peak memory 200260 kb
Host smart-388ae705-deb0-4336-9de5-824bf0446b45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050206761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3050206761
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3594083537
Short name T551
Test name
Test status
Simulation time 554375088 ps
CPU time 2.07 seconds
Started Aug 19 05:04:12 PM PDT 24
Finished Aug 19 05:04:14 PM PDT 24
Peak memory 200236 kb
Host smart-d35c76dd-acb7-4098-809f-af6198ce30f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594083537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3594083537
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2064400590
Short name T140
Test name
Test status
Simulation time 1662418647 ps
CPU time 4.01 seconds
Started Aug 19 05:04:10 PM PDT 24
Finished Aug 19 05:04:15 PM PDT 24
Peak memory 200360 kb
Host smart-46b11e2a-406e-4977-8fd1-68d695bc3139
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064400590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2064400590
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.308596470
Short name T633
Test name
Test status
Simulation time 12744727 ps
CPU time 0.63 seconds
Started Aug 19 05:04:37 PM PDT 24
Finished Aug 19 05:04:38 PM PDT 24
Peak memory 195352 kb
Host smart-39734046-fe2f-490a-9c39-499b505799eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308596470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.308596470
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3502463066
Short name T558
Test name
Test status
Simulation time 14806767 ps
CPU time 0.63 seconds
Started Aug 19 05:04:35 PM PDT 24
Finished Aug 19 05:04:36 PM PDT 24
Peak memory 195384 kb
Host smart-19b8de72-ea2d-496f-9512-dbc88c6ecf99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502463066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3502463066
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.2447052214
Short name T529
Test name
Test status
Simulation time 18069328 ps
CPU time 0.64 seconds
Started Aug 19 05:04:35 PM PDT 24
Finished Aug 19 05:04:36 PM PDT 24
Peak memory 195412 kb
Host smart-fdab34e2-9115-4905-971d-5411ff8b6fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447052214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.2447052214
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.922525307
Short name T592
Test name
Test status
Simulation time 67130745 ps
CPU time 0.61 seconds
Started Aug 19 05:04:34 PM PDT 24
Finished Aug 19 05:04:35 PM PDT 24
Peak memory 195264 kb
Host smart-22b4455f-dd16-4a67-8c8b-8680976bf7b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922525307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.922525307
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2085677808
Short name T653
Test name
Test status
Simulation time 12621861 ps
CPU time 0.58 seconds
Started Aug 19 05:04:34 PM PDT 24
Finished Aug 19 05:04:35 PM PDT 24
Peak memory 195264 kb
Host smart-2f19b045-a403-4ffb-920d-8b2cfa1991d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085677808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2085677808
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3944029355
Short name T556
Test name
Test status
Simulation time 61295334 ps
CPU time 0.6 seconds
Started Aug 19 05:04:33 PM PDT 24
Finished Aug 19 05:04:34 PM PDT 24
Peak memory 195264 kb
Host smart-34520c22-3310-4e55-a000-37359245f365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944029355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3944029355
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3628231630
Short name T533
Test name
Test status
Simulation time 12584086 ps
CPU time 0.63 seconds
Started Aug 19 05:04:34 PM PDT 24
Finished Aug 19 05:04:34 PM PDT 24
Peak memory 195420 kb
Host smart-220cb16c-3a3e-43ea-9bf4-6565900e93a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628231630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3628231630
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1527498539
Short name T594
Test name
Test status
Simulation time 67434398 ps
CPU time 0.58 seconds
Started Aug 19 05:04:35 PM PDT 24
Finished Aug 19 05:04:36 PM PDT 24
Peak memory 195276 kb
Host smart-48cb2881-2806-40b9-9634-812255f1f2fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527498539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1527498539
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2427506235
Short name T532
Test name
Test status
Simulation time 23644601 ps
CPU time 0.62 seconds
Started Aug 19 05:04:35 PM PDT 24
Finished Aug 19 05:04:36 PM PDT 24
Peak memory 195344 kb
Host smart-4289a161-cb1f-43e7-8eaf-d2483d2d3724
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427506235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2427506235
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1102286024
Short name T620
Test name
Test status
Simulation time 42433302 ps
CPU time 0.6 seconds
Started Aug 19 05:04:33 PM PDT 24
Finished Aug 19 05:04:33 PM PDT 24
Peak memory 195256 kb
Host smart-e400d4ca-e6cf-4d70-b612-22975585b3d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102286024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1102286024
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3735382798
Short name T118
Test name
Test status
Simulation time 742120318 ps
CPU time 6.08 seconds
Started Aug 19 05:04:10 PM PDT 24
Finished Aug 19 05:04:16 PM PDT 24
Peak memory 200256 kb
Host smart-82e410db-ca0e-47ba-8fb2-01a981f559ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735382798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3735382798
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2333114903
Short name T116
Test name
Test status
Simulation time 560433578 ps
CPU time 6.04 seconds
Started Aug 19 05:04:20 PM PDT 24
Finished Aug 19 05:04:26 PM PDT 24
Peak memory 198804 kb
Host smart-308905df-94ba-4aa8-a539-6437692416c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333114903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2333114903
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3364618777
Short name T107
Test name
Test status
Simulation time 38797612 ps
CPU time 0.83 seconds
Started Aug 19 05:04:15 PM PDT 24
Finished Aug 19 05:04:16 PM PDT 24
Peak memory 199168 kb
Host smart-605bab12-9d77-489e-8178-3ae9da330bfd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364618777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3364618777
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3401274410
Short name T569
Test name
Test status
Simulation time 120969421941 ps
CPU time 1020.72 seconds
Started Aug 19 05:04:10 PM PDT 24
Finished Aug 19 05:21:11 PM PDT 24
Peak memory 224984 kb
Host smart-9a2a7560-51a9-4a05-8afc-6e753d8d3d90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401274410 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3401274410
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1819123034
Short name T598
Test name
Test status
Simulation time 90707960 ps
CPU time 0.86 seconds
Started Aug 19 05:04:18 PM PDT 24
Finished Aug 19 05:04:19 PM PDT 24
Peak memory 199864 kb
Host smart-24e56995-c3f5-4c80-b863-46d955fca948
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819123034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1819123034
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2621039506
Short name T601
Test name
Test status
Simulation time 11785437 ps
CPU time 0.57 seconds
Started Aug 19 05:04:11 PM PDT 24
Finished Aug 19 05:04:11 PM PDT 24
Peak memory 195208 kb
Host smart-06be28a7-6c86-4c11-b64e-6d92ad9e6554
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621039506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2621039506
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2730200017
Short name T123
Test name
Test status
Simulation time 34265874 ps
CPU time 1.53 seconds
Started Aug 19 05:04:13 PM PDT 24
Finished Aug 19 05:04:15 PM PDT 24
Peak memory 200300 kb
Host smart-971112c1-0af6-4e44-8c82-532fc1ca7287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730200017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2730200017
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3131496648
Short name T564
Test name
Test status
Simulation time 78264064 ps
CPU time 3.79 seconds
Started Aug 19 05:04:13 PM PDT 24
Finished Aug 19 05:04:17 PM PDT 24
Peak memory 200280 kb
Host smart-421218ea-d019-45be-a89d-dcbc091d2669
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131496648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3131496648
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2446373845
Short name T71
Test name
Test status
Simulation time 128191559 ps
CPU time 4.07 seconds
Started Aug 19 05:04:10 PM PDT 24
Finished Aug 19 05:04:15 PM PDT 24
Peak memory 200372 kb
Host smart-cd120e96-92de-4c1b-ac51-84f922540c87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446373845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2446373845
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3432689003
Short name T536
Test name
Test status
Simulation time 12514358 ps
CPU time 0.61 seconds
Started Aug 19 05:04:34 PM PDT 24
Finished Aug 19 05:04:35 PM PDT 24
Peak memory 195372 kb
Host smart-12caedbc-8e74-4329-a02d-a7ad770666ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432689003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3432689003
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.122427211
Short name T535
Test name
Test status
Simulation time 13905389 ps
CPU time 0.66 seconds
Started Aug 19 05:04:34 PM PDT 24
Finished Aug 19 05:04:34 PM PDT 24
Peak memory 195376 kb
Host smart-c10abe9a-7136-43e1-bb61-8cae377c4970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122427211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.122427211
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1227712696
Short name T641
Test name
Test status
Simulation time 81854678 ps
CPU time 0.59 seconds
Started Aug 19 05:04:49 PM PDT 24
Finished Aug 19 05:04:50 PM PDT 24
Peak memory 195252 kb
Host smart-99897d4d-a741-4816-9392-01e301cb8017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227712696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1227712696
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3741177357
Short name T634
Test name
Test status
Simulation time 19923218 ps
CPU time 0.6 seconds
Started Aug 19 05:04:50 PM PDT 24
Finished Aug 19 05:04:51 PM PDT 24
Peak memory 195380 kb
Host smart-bec8d8c1-b4d3-440a-ba52-7b01f3d42081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741177357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3741177357
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3459746070
Short name T572
Test name
Test status
Simulation time 29921533 ps
CPU time 0.65 seconds
Started Aug 19 05:04:45 PM PDT 24
Finished Aug 19 05:04:46 PM PDT 24
Peak memory 195268 kb
Host smart-267284a9-7323-4241-bbf6-52c3b6a426a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459746070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3459746070
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.19555433
Short name T538
Test name
Test status
Simulation time 43041342 ps
CPU time 0.61 seconds
Started Aug 19 05:04:52 PM PDT 24
Finished Aug 19 05:04:53 PM PDT 24
Peak memory 195220 kb
Host smart-d97e8cb9-d1b1-436e-9dda-d04df3924c82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19555433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.19555433
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2033706427
Short name T622
Test name
Test status
Simulation time 14048663 ps
CPU time 0.63 seconds
Started Aug 19 05:04:46 PM PDT 24
Finished Aug 19 05:04:47 PM PDT 24
Peak memory 195300 kb
Host smart-96fe0174-fca9-4edd-9e3a-3962aef917e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033706427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2033706427
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.425763199
Short name T530
Test name
Test status
Simulation time 15590080 ps
CPU time 0.6 seconds
Started Aug 19 05:04:45 PM PDT 24
Finished Aug 19 05:04:45 PM PDT 24
Peak memory 195324 kb
Host smart-68a72d86-23ca-4103-b23d-7a2091ca3f22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425763199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.425763199
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1685008246
Short name T630
Test name
Test status
Simulation time 49831338 ps
CPU time 0.61 seconds
Started Aug 19 05:04:51 PM PDT 24
Finished Aug 19 05:04:52 PM PDT 24
Peak memory 195244 kb
Host smart-8389e0db-b0d7-487c-b8ea-03c33997bdfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685008246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1685008246
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1182218650
Short name T552
Test name
Test status
Simulation time 175337497 ps
CPU time 0.63 seconds
Started Aug 19 05:04:47 PM PDT 24
Finished Aug 19 05:04:47 PM PDT 24
Peak memory 195316 kb
Host smart-cc6ba00e-d7e4-42db-a8d0-81f2eb6917dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182218650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1182218650
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2537887258
Short name T642
Test name
Test status
Simulation time 28554623 ps
CPU time 1.85 seconds
Started Aug 19 05:04:12 PM PDT 24
Finished Aug 19 05:04:14 PM PDT 24
Peak memory 200268 kb
Host smart-87e0d4fc-4c04-4bf7-bfac-1e8e877a6066
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537887258 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2537887258
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1967299747
Short name T643
Test name
Test status
Simulation time 117837400 ps
CPU time 1 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:04:23 PM PDT 24
Peak memory 200104 kb
Host smart-c4d2578a-8c7e-4756-b91f-4e3dd4f09385
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967299747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1967299747
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.966710114
Short name T554
Test name
Test status
Simulation time 41494946 ps
CPU time 0.59 seconds
Started Aug 19 05:04:10 PM PDT 24
Finished Aug 19 05:04:11 PM PDT 24
Peak memory 195280 kb
Host smart-cd344e31-a2a1-451b-96ab-b7c940d9262d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966710114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.966710114
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.502883646
Short name T124
Test name
Test status
Simulation time 220804996 ps
CPU time 2.12 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:04:25 PM PDT 24
Peak memory 200272 kb
Host smart-3c71f5f0-06f3-4c12-ade0-7591826f74f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502883646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.502883646
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1083405892
Short name T591
Test name
Test status
Simulation time 72941719 ps
CPU time 3.71 seconds
Started Aug 19 05:04:15 PM PDT 24
Finished Aug 19 05:04:19 PM PDT 24
Peak memory 200208 kb
Host smart-2f85db0f-507c-47ce-84a7-6f18c46f8e37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083405892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1083405892
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3174857312
Short name T576
Test name
Test status
Simulation time 161185991 ps
CPU time 2.72 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:04:25 PM PDT 24
Peak memory 200252 kb
Host smart-27291762-8268-4ee2-81ff-99e5550307fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174857312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3174857312
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3544343120
Short name T600
Test name
Test status
Simulation time 67195039 ps
CPU time 2 seconds
Started Aug 19 05:04:25 PM PDT 24
Finished Aug 19 05:04:27 PM PDT 24
Peak memory 200324 kb
Host smart-b44cb353-c58a-40cd-94c2-0c12a9fb9b4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544343120 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3544343120
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2021776658
Short name T610
Test name
Test status
Simulation time 30559880 ps
CPU time 0.95 seconds
Started Aug 19 05:04:26 PM PDT 24
Finished Aug 19 05:04:27 PM PDT 24
Peak memory 200096 kb
Host smart-cc272d7f-4132-412b-b93c-da0c420754ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021776658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2021776658
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3104809081
Short name T627
Test name
Test status
Simulation time 16478577 ps
CPU time 0.64 seconds
Started Aug 19 05:04:24 PM PDT 24
Finished Aug 19 05:04:25 PM PDT 24
Peak memory 195328 kb
Host smart-8248c0a7-e38f-4bdc-b24a-b11f36dee6d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104809081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3104809081
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.176577521
Short name T647
Test name
Test status
Simulation time 65159170 ps
CPU time 1.28 seconds
Started Aug 19 05:04:21 PM PDT 24
Finished Aug 19 05:04:23 PM PDT 24
Peak memory 200280 kb
Host smart-a6cad33d-f69c-4ec8-a1cc-c440bc79bc5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176577521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.176577521
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2129226799
Short name T528
Test name
Test status
Simulation time 1188549362 ps
CPU time 3.34 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:04:25 PM PDT 24
Peak memory 200268 kb
Host smart-40f6cb8a-90b3-4f18-ba0b-e35058556c32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129226799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2129226799
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1028759226
Short name T567
Test name
Test status
Simulation time 53244569 ps
CPU time 1.72 seconds
Started Aug 19 05:04:27 PM PDT 24
Finished Aug 19 05:04:29 PM PDT 24
Peak memory 200324 kb
Host smart-fe64bf32-d641-47df-ac72-60d9ca8eaf21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028759226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1028759226
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2972934390
Short name T656
Test name
Test status
Simulation time 46651077 ps
CPU time 1.32 seconds
Started Aug 19 05:04:21 PM PDT 24
Finished Aug 19 05:04:23 PM PDT 24
Peak memory 200336 kb
Host smart-7591443d-68d2-412f-a45e-867c5267af76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972934390 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2972934390
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3305984576
Short name T655
Test name
Test status
Simulation time 19176189 ps
CPU time 0.73 seconds
Started Aug 19 05:04:21 PM PDT 24
Finished Aug 19 05:04:22 PM PDT 24
Peak memory 198712 kb
Host smart-dee5c990-560d-4b19-99c3-04c1e426b665
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305984576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3305984576
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2768348352
Short name T547
Test name
Test status
Simulation time 50364596 ps
CPU time 0.61 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:04:22 PM PDT 24
Peak memory 195376 kb
Host smart-5589cc67-a389-47b8-8f3c-34483a908d98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768348352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2768348352
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2466882058
Short name T120
Test name
Test status
Simulation time 984121587 ps
CPU time 1.19 seconds
Started Aug 19 05:04:25 PM PDT 24
Finished Aug 19 05:04:26 PM PDT 24
Peak memory 199996 kb
Host smart-8ad0b5ce-9604-47d2-bb19-5a9934285af0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466882058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2466882058
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3360683816
Short name T628
Test name
Test status
Simulation time 36187238 ps
CPU time 1.81 seconds
Started Aug 19 05:04:20 PM PDT 24
Finished Aug 19 05:04:22 PM PDT 24
Peak memory 200284 kb
Host smart-f9b79741-5adc-4cb5-b88b-a28beed48055
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360683816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3360683816
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3221787435
Short name T581
Test name
Test status
Simulation time 716455872 ps
CPU time 3.22 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:04:25 PM PDT 24
Peak memory 200304 kb
Host smart-4355b8b3-bd98-4029-9a4f-4119e27cb931
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221787435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3221787435
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1848414788
Short name T651
Test name
Test status
Simulation time 309132719546 ps
CPU time 576.61 seconds
Started Aug 19 05:04:23 PM PDT 24
Finished Aug 19 05:14:00 PM PDT 24
Peak memory 216672 kb
Host smart-d7fb6c22-35c4-4069-b785-6af266485cd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848414788 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1848414788
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3937870974
Short name T527
Test name
Test status
Simulation time 75872594 ps
CPU time 0.73 seconds
Started Aug 19 05:04:25 PM PDT 24
Finished Aug 19 05:04:26 PM PDT 24
Peak memory 198320 kb
Host smart-bc9b935e-c7e1-49e1-a890-b8d4a8e83344
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937870974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3937870974
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.464681273
Short name T650
Test name
Test status
Simulation time 22639562 ps
CPU time 0.55 seconds
Started Aug 19 05:04:25 PM PDT 24
Finished Aug 19 05:04:25 PM PDT 24
Peak memory 195296 kb
Host smart-e4259127-ff4b-4877-b247-f345ff8b1f72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464681273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.464681273
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.969170698
Short name T649
Test name
Test status
Simulation time 60265377 ps
CPU time 1.26 seconds
Started Aug 19 05:04:24 PM PDT 24
Finished Aug 19 05:04:26 PM PDT 24
Peak memory 200292 kb
Host smart-4f550876-5c93-416b-bc04-68e8f8b690d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969170698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.969170698
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.275498778
Short name T531
Test name
Test status
Simulation time 456970784 ps
CPU time 2.51 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:04:24 PM PDT 24
Peak memory 200328 kb
Host smart-347ff38d-64fa-4082-94b3-5c161de1f3b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275498778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.275498778
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1484529808
Short name T644
Test name
Test status
Simulation time 84947385 ps
CPU time 1.81 seconds
Started Aug 19 05:04:23 PM PDT 24
Finished Aug 19 05:04:25 PM PDT 24
Peak memory 200256 kb
Host smart-133cc863-7da7-42e7-83e0-4a84aedec238
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484529808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1484529808
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.259695333
Short name T74
Test name
Test status
Simulation time 340197801 ps
CPU time 1.77 seconds
Started Aug 19 05:04:21 PM PDT 24
Finished Aug 19 05:04:23 PM PDT 24
Peak memory 200332 kb
Host smart-a031aa43-945e-48a4-9b7c-ab005b3c1362
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259695333 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.259695333
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1400347169
Short name T597
Test name
Test status
Simulation time 95911764 ps
CPU time 0.81 seconds
Started Aug 19 05:04:23 PM PDT 24
Finished Aug 19 05:04:24 PM PDT 24
Peak memory 200056 kb
Host smart-da525508-2a18-461b-b4d9-2f099d9e0b30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400347169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1400347169
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.4067785807
Short name T616
Test name
Test status
Simulation time 21590994 ps
CPU time 0.59 seconds
Started Aug 19 05:04:24 PM PDT 24
Finished Aug 19 05:04:25 PM PDT 24
Peak memory 195368 kb
Host smart-0146f234-fa00-493c-99df-5bd110b91843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067785807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.4067785807
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3604909797
Short name T122
Test name
Test status
Simulation time 211398310 ps
CPU time 1.56 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:04:24 PM PDT 24
Peak memory 200148 kb
Host smart-7ae81934-7906-468c-a69a-bb53fee55005
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604909797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3604909797
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2579961932
Short name T599
Test name
Test status
Simulation time 715599155 ps
CPU time 3.22 seconds
Started Aug 19 05:04:22 PM PDT 24
Finished Aug 19 05:04:26 PM PDT 24
Peak memory 200300 kb
Host smart-f48a7523-d45a-4e75-858d-1c675a582b25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579961932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2579961932
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2933905098
Short name T640
Test name
Test status
Simulation time 88306141 ps
CPU time 2.82 seconds
Started Aug 19 05:04:20 PM PDT 24
Finished Aug 19 05:04:23 PM PDT 24
Peak memory 200332 kb
Host smart-88d800ae-06ea-4064-a686-a2bd1a1deb12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933905098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2933905098
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1722001268
Short name T310
Test name
Test status
Simulation time 34111717 ps
CPU time 0.59 seconds
Started Aug 19 05:11:02 PM PDT 24
Finished Aug 19 05:11:02 PM PDT 24
Peak memory 195728 kb
Host smart-9280a03f-a242-43af-a59d-2e57fff2e9e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722001268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1722001268
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.574250582
Short name T232
Test name
Test status
Simulation time 865995552 ps
CPU time 52.95 seconds
Started Aug 19 05:10:57 PM PDT 24
Finished Aug 19 05:11:50 PM PDT 24
Peak memory 200684 kb
Host smart-75b4c61c-c082-4fde-9585-97dd71d22956
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=574250582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.574250582
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3628500899
Short name T500
Test name
Test status
Simulation time 1179270147 ps
CPU time 63.72 seconds
Started Aug 19 05:10:58 PM PDT 24
Finished Aug 19 05:12:02 PM PDT 24
Peak memory 200480 kb
Host smart-34265fd3-ccd9-452a-b501-69c0e92a44fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628500899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3628500899
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1150738402
Short name T449
Test name
Test status
Simulation time 12429669560 ps
CPU time 715.59 seconds
Started Aug 19 05:10:58 PM PDT 24
Finished Aug 19 05:22:54 PM PDT 24
Peak memory 682192 kb
Host smart-f0a2e70e-9a4c-4b94-a477-d5594fe2521a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1150738402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1150738402
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2247416929
Short name T308
Test name
Test status
Simulation time 8267783950 ps
CPU time 23.74 seconds
Started Aug 19 05:10:49 PM PDT 24
Finished Aug 19 05:11:13 PM PDT 24
Peak memory 200636 kb
Host smart-bc5616d4-9376-43d3-994a-74e37c4d8938
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247416929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2247416929
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1514251470
Short name T330
Test name
Test status
Simulation time 3627885662 ps
CPU time 101.81 seconds
Started Aug 19 05:10:59 PM PDT 24
Finished Aug 19 05:12:41 PM PDT 24
Peak memory 200736 kb
Host smart-c4a22664-2ad5-4e20-a193-7386c22f66d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514251470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1514251470
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3490566629
Short name T67
Test name
Test status
Simulation time 104666150 ps
CPU time 0.84 seconds
Started Aug 19 05:10:56 PM PDT 24
Finished Aug 19 05:10:57 PM PDT 24
Peak memory 219032 kb
Host smart-6fadc849-f8da-4aa6-98fa-8afabad164bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490566629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3490566629
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3140349730
Short name T430
Test name
Test status
Simulation time 503137942 ps
CPU time 8.65 seconds
Started Aug 19 05:10:50 PM PDT 24
Finished Aug 19 05:10:59 PM PDT 24
Peak memory 200672 kb
Host smart-9d44d387-9063-4e82-995e-3e4f86a07588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140349730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3140349730
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1160020925
Short name T102
Test name
Test status
Simulation time 260167277101 ps
CPU time 1473.11 seconds
Started Aug 19 05:11:00 PM PDT 24
Finished Aug 19 05:35:33 PM PDT 24
Peak memory 755852 kb
Host smart-53b13d49-0aae-41a5-b627-296f9cd09555
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160020925 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1160020925
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3577284105
Short name T286
Test name
Test status
Simulation time 1747297564 ps
CPU time 78.5 seconds
Started Aug 19 05:10:54 PM PDT 24
Finished Aug 19 05:12:13 PM PDT 24
Peak memory 200708 kb
Host smart-bcfcc2dc-200c-45e5-a0aa-21496cda79df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3577284105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3577284105
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.1736330265
Short name T506
Test name
Test status
Simulation time 4790804737 ps
CPU time 94.3 seconds
Started Aug 19 05:10:49 PM PDT 24
Finished Aug 19 05:12:23 PM PDT 24
Peak memory 200720 kb
Host smart-a41c5ada-a420-4424-8e85-8f60b84351b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1736330265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.1736330265
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.46255888
Short name T475
Test name
Test status
Simulation time 8176917597 ps
CPU time 98.1 seconds
Started Aug 19 05:10:58 PM PDT 24
Finished Aug 19 05:12:36 PM PDT 24
Peak memory 200468 kb
Host smart-be54d708-a557-4e92-8870-059ca8651590
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=46255888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.46255888
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.219157666
Short name T52
Test name
Test status
Simulation time 129614402692 ps
CPU time 2417.97 seconds
Started Aug 19 05:10:56 PM PDT 24
Finished Aug 19 05:51:15 PM PDT 24
Peak memory 217116 kb
Host smart-5e05ff1f-af28-4ab5-a138-beeb897af68e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=219157666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.219157666
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.1564599813
Short name T97
Test name
Test status
Simulation time 207468567541 ps
CPU time 2664.38 seconds
Started Aug 19 05:10:50 PM PDT 24
Finished Aug 19 05:55:15 PM PDT 24
Peak memory 216268 kb
Host smart-9ad71e85-7487-47dd-bad2-0066f6b3b296
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1564599813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.1564599813
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1199586162
Short name T103
Test name
Test status
Simulation time 5878695451 ps
CPU time 79.04 seconds
Started Aug 19 05:10:59 PM PDT 24
Finished Aug 19 05:12:18 PM PDT 24
Peak memory 200720 kb
Host smart-7407094f-e4b3-4402-8368-224d34b342fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199586162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1199586162
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3930728488
Short name T428
Test name
Test status
Simulation time 25407213 ps
CPU time 0.63 seconds
Started Aug 19 05:11:04 PM PDT 24
Finished Aug 19 05:11:04 PM PDT 24
Peak memory 196404 kb
Host smart-833621d5-ebfd-4cb7-91f7-146a25609d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930728488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3930728488
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.422800327
Short name T370
Test name
Test status
Simulation time 5103238822 ps
CPU time 33.28 seconds
Started Aug 19 05:11:01 PM PDT 24
Finished Aug 19 05:11:35 PM PDT 24
Peak memory 200696 kb
Host smart-43bcbf92-67f9-4712-a0de-df960cd5468b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=422800327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.422800327
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.475420339
Short name T322
Test name
Test status
Simulation time 1706443592 ps
CPU time 17.08 seconds
Started Aug 19 05:10:59 PM PDT 24
Finished Aug 19 05:11:16 PM PDT 24
Peak memory 200628 kb
Host smart-298dcf18-edcf-4dc9-99e1-d1615c18d8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475420339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.475420339
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1046707722
Short name T288
Test name
Test status
Simulation time 2278797445 ps
CPU time 244.75 seconds
Started Aug 19 05:11:04 PM PDT 24
Finished Aug 19 05:15:08 PM PDT 24
Peak memory 655980 kb
Host smart-0d5d0983-8e4a-46fd-8d5e-770136a663bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1046707722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1046707722
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.59910184
Short name T225
Test name
Test status
Simulation time 8130278890 ps
CPU time 110.87 seconds
Started Aug 19 05:10:58 PM PDT 24
Finished Aug 19 05:12:49 PM PDT 24
Peak memory 200692 kb
Host smart-594991bf-7c44-42f0-93a3-3954fc8764f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59910184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.59910184
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3886753633
Short name T307
Test name
Test status
Simulation time 216216301 ps
CPU time 12.35 seconds
Started Aug 19 05:11:00 PM PDT 24
Finished Aug 19 05:11:12 PM PDT 24
Peak memory 200576 kb
Host smart-3c66466b-fa62-4886-90e6-8708b06c1219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886753633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3886753633
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2732608182
Short name T66
Test name
Test status
Simulation time 311583331 ps
CPU time 1.03 seconds
Started Aug 19 05:11:02 PM PDT 24
Finished Aug 19 05:11:03 PM PDT 24
Peak memory 219964 kb
Host smart-72765774-f23f-490c-81ce-8ff006dae675
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732608182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2732608182
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2315902645
Short name T458
Test name
Test status
Simulation time 345414851 ps
CPU time 5.8 seconds
Started Aug 19 05:11:02 PM PDT 24
Finished Aug 19 05:11:08 PM PDT 24
Peak memory 200732 kb
Host smart-123a1b5b-01ce-4305-bf36-2890c2152e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315902645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2315902645
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.262341423
Short name T153
Test name
Test status
Simulation time 58772712805 ps
CPU time 1290.15 seconds
Started Aug 19 05:10:58 PM PDT 24
Finished Aug 19 05:32:29 PM PDT 24
Peak memory 708400 kb
Host smart-ad272d9d-737c-43c7-abf4-f240b16205dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262341423 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.262341423
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3125516598
Short name T13
Test name
Test status
Simulation time 64840811731 ps
CPU time 568.47 seconds
Started Aug 19 05:11:03 PM PDT 24
Finished Aug 19 05:20:31 PM PDT 24
Peak memory 671612 kb
Host smart-ca12304c-e5cc-4c9d-86bb-32d5cc78b4a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3125516598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3125516598
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.1968665781
Short name T305
Test name
Test status
Simulation time 4492926253 ps
CPU time 54.15 seconds
Started Aug 19 05:11:00 PM PDT 24
Finished Aug 19 05:11:54 PM PDT 24
Peak memory 200712 kb
Host smart-ef4e8dc9-7e74-409d-875e-e63215078db8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1968665781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.1968665781
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.1690665317
Short name T480
Test name
Test status
Simulation time 27184148731 ps
CPU time 108.51 seconds
Started Aug 19 05:11:00 PM PDT 24
Finished Aug 19 05:12:49 PM PDT 24
Peak memory 200696 kb
Host smart-e94a18ea-c581-4caf-a679-43f2ae156823
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1690665317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.1690665317
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.666819940
Short name T72
Test name
Test status
Simulation time 86255211294 ps
CPU time 88.23 seconds
Started Aug 19 05:10:57 PM PDT 24
Finished Aug 19 05:12:26 PM PDT 24
Peak memory 200720 kb
Host smart-ad2f71cc-c64f-49f2-bdb3-e7d686e8b4e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=666819940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.666819940
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1657647689
Short name T483
Test name
Test status
Simulation time 75023429925 ps
CPU time 640.94 seconds
Started Aug 19 05:11:05 PM PDT 24
Finished Aug 19 05:21:46 PM PDT 24
Peak memory 200596 kb
Host smart-2e03389a-a446-49ae-a3bd-c7418d70f06e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1657647689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1657647689
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.4086241218
Short name T413
Test name
Test status
Simulation time 156762482054 ps
CPU time 2246.46 seconds
Started Aug 19 05:11:02 PM PDT 24
Finished Aug 19 05:48:29 PM PDT 24
Peak memory 216816 kb
Host smart-7838c9dc-57f0-4319-bf96-5c39ac2118ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4086241218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.4086241218
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.2647628949
Short name T144
Test name
Test status
Simulation time 187513059674 ps
CPU time 2472.42 seconds
Started Aug 19 05:10:58 PM PDT 24
Finished Aug 19 05:52:11 PM PDT 24
Peak memory 217024 kb
Host smart-58f6ca55-7ac1-4762-8568-5f1db484666b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2647628949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2647628949
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1092869421
Short name T130
Test name
Test status
Simulation time 36019815119 ps
CPU time 83.59 seconds
Started Aug 19 05:11:04 PM PDT 24
Finished Aug 19 05:12:28 PM PDT 24
Peak memory 200720 kb
Host smart-96ef0edc-075c-4fe8-b8fd-8d4223431e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092869421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1092869421
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2085046423
Short name T198
Test name
Test status
Simulation time 31854629 ps
CPU time 0.62 seconds
Started Aug 19 05:11:05 PM PDT 24
Finished Aug 19 05:11:06 PM PDT 24
Peak memory 196496 kb
Host smart-0ca5b17e-928d-445f-b5bd-a6385c6fb902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085046423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2085046423
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2478339893
Short name T516
Test name
Test status
Simulation time 1013057376 ps
CPU time 58.21 seconds
Started Aug 19 05:11:10 PM PDT 24
Finished Aug 19 05:12:08 PM PDT 24
Peak memory 200684 kb
Host smart-cb1e76f5-46c6-4870-b6bb-e0d27063c541
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2478339893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2478339893
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2513088860
Short name T432
Test name
Test status
Simulation time 8280153785 ps
CPU time 5.99 seconds
Started Aug 19 05:11:08 PM PDT 24
Finished Aug 19 05:11:14 PM PDT 24
Peak memory 200680 kb
Host smart-5bbcc7bf-48f5-4992-9198-a787d33c679a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513088860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2513088860
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1434214351
Short name T195
Test name
Test status
Simulation time 16107748543 ps
CPU time 685.97 seconds
Started Aug 19 05:11:05 PM PDT 24
Finished Aug 19 05:22:31 PM PDT 24
Peak memory 686720 kb
Host smart-65bbaa5a-c8e3-484e-b808-360e5974fcb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1434214351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1434214351
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3771291930
Short name T450
Test name
Test status
Simulation time 12676847102 ps
CPU time 170.14 seconds
Started Aug 19 05:11:11 PM PDT 24
Finished Aug 19 05:14:02 PM PDT 24
Peak memory 200716 kb
Host smart-4a525e19-4f47-4b79-ba0e-334f0c0089b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771291930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3771291930
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1351017774
Short name T96
Test name
Test status
Simulation time 2542614130 ps
CPU time 78.97 seconds
Started Aug 19 05:11:06 PM PDT 24
Finished Aug 19 05:12:25 PM PDT 24
Peak memory 200712 kb
Host smart-25dd3358-b130-474b-8811-444718111470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351017774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1351017774
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3443471341
Short name T349
Test name
Test status
Simulation time 620668809 ps
CPU time 1.96 seconds
Started Aug 19 05:11:05 PM PDT 24
Finished Aug 19 05:11:12 PM PDT 24
Peak memory 200616 kb
Host smart-37bc9139-20a4-4c3f-94e3-dcf29b5547f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443471341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3443471341
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.2675144837
Short name T289
Test name
Test status
Simulation time 2566337248 ps
CPU time 456.63 seconds
Started Aug 19 05:11:18 PM PDT 24
Finished Aug 19 05:18:55 PM PDT 24
Peak memory 637632 kb
Host smart-6a27c919-a49a-4ecb-a09f-99c3115cf9c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675144837 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2675144837
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1089134976
Short name T434
Test name
Test status
Simulation time 20048480582 ps
CPU time 140.82 seconds
Started Aug 19 05:11:17 PM PDT 24
Finished Aug 19 05:13:38 PM PDT 24
Peak memory 200800 kb
Host smart-daa4ed42-6f52-4c99-96e3-1c5fe5ee1891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089134976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1089134976
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2953886911
Short name T187
Test name
Test status
Simulation time 33956118 ps
CPU time 0.6 seconds
Started Aug 19 05:11:05 PM PDT 24
Finished Aug 19 05:11:06 PM PDT 24
Peak memory 197436 kb
Host smart-25286c71-70e2-4e74-86be-d0686a35b4b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953886911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2953886911
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.612046627
Short name T346
Test name
Test status
Simulation time 581949173 ps
CPU time 16.3 seconds
Started Aug 19 05:11:14 PM PDT 24
Finished Aug 19 05:11:30 PM PDT 24
Peak memory 200648 kb
Host smart-32fdca5e-bb5f-4d8b-a68d-fb638ffc4f7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612046627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.612046627
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3201985984
Short name T300
Test name
Test status
Simulation time 7245463075 ps
CPU time 59.7 seconds
Started Aug 19 05:11:03 PM PDT 24
Finished Aug 19 05:12:03 PM PDT 24
Peak memory 200804 kb
Host smart-431d6af2-1337-4aa9-bbd7-efec4e1c72a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201985984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3201985984
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1838940757
Short name T251
Test name
Test status
Simulation time 3051492921 ps
CPU time 730.88 seconds
Started Aug 19 05:11:26 PM PDT 24
Finished Aug 19 05:23:37 PM PDT 24
Peak memory 733972 kb
Host smart-e99ddcfb-2654-4cfa-96cf-ae79ec58a9aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1838940757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1838940757
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.298551221
Short name T59
Test name
Test status
Simulation time 5482924774 ps
CPU time 36.19 seconds
Started Aug 19 05:11:05 PM PDT 24
Finished Aug 19 05:11:41 PM PDT 24
Peak memory 200684 kb
Host smart-160bede5-2b95-4cd1-8cc5-f9e05346656e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298551221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.298551221
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1049375929
Short name T241
Test name
Test status
Simulation time 11809868434 ps
CPU time 173.89 seconds
Started Aug 19 05:11:07 PM PDT 24
Finished Aug 19 05:14:01 PM PDT 24
Peak memory 200880 kb
Host smart-834d3a5a-2921-4093-91f7-4226fa24dcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049375929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1049375929
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2618806980
Short name T331
Test name
Test status
Simulation time 136225427 ps
CPU time 1.58 seconds
Started Aug 19 05:11:28 PM PDT 24
Finished Aug 19 05:11:30 PM PDT 24
Peak memory 200456 kb
Host smart-550ac04d-9aae-42e9-997b-9ec4784812c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618806980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2618806980
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.375700542
Short name T417
Test name
Test status
Simulation time 103656778422 ps
CPU time 1430.69 seconds
Started Aug 19 05:11:05 PM PDT 24
Finished Aug 19 05:34:56 PM PDT 24
Peak memory 729724 kb
Host smart-2f1e27a2-0ffd-4de8-a171-132bc8e286ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375700542 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.375700542
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1385752494
Short name T316
Test name
Test status
Simulation time 29275953387 ps
CPU time 29.97 seconds
Started Aug 19 05:11:26 PM PDT 24
Finished Aug 19 05:11:56 PM PDT 24
Peak memory 200668 kb
Host smart-d55969ef-c52f-4619-9863-b686c6d9f0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385752494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1385752494
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3288879307
Short name T352
Test name
Test status
Simulation time 90273168 ps
CPU time 0.58 seconds
Started Aug 19 05:11:28 PM PDT 24
Finished Aug 19 05:11:29 PM PDT 24
Peak memory 196608 kb
Host smart-173eb907-d634-4315-9707-bb7f6233cad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288879307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3288879307
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.146580068
Short name T183
Test name
Test status
Simulation time 740416160 ps
CPU time 45.55 seconds
Started Aug 19 05:11:28 PM PDT 24
Finished Aug 19 05:12:14 PM PDT 24
Peak memory 200372 kb
Host smart-44bb17a8-e6e4-451a-baa0-f70ef3b8b02c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=146580068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.146580068
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.355626063
Short name T317
Test name
Test status
Simulation time 3799971883 ps
CPU time 74.18 seconds
Started Aug 19 05:11:18 PM PDT 24
Finished Aug 19 05:12:32 PM PDT 24
Peak memory 200676 kb
Host smart-081170f0-2b15-42e0-b581-79b50dcd9328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355626063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.355626063
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.699725778
Short name T314
Test name
Test status
Simulation time 11561935857 ps
CPU time 743.25 seconds
Started Aug 19 05:11:10 PM PDT 24
Finished Aug 19 05:23:33 PM PDT 24
Peak memory 701084 kb
Host smart-b4748c1a-3937-4cdb-ae24-7582211f8351
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=699725778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.699725778
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.356267305
Short name T446
Test name
Test status
Simulation time 6919260465 ps
CPU time 194.55 seconds
Started Aug 19 05:11:10 PM PDT 24
Finished Aug 19 05:14:25 PM PDT 24
Peak memory 200728 kb
Host smart-ee8cd231-75ac-4dac-90a1-7b80159d07ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356267305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.356267305
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3421692338
Short name T230
Test name
Test status
Simulation time 27314574645 ps
CPU time 126.85 seconds
Started Aug 19 05:11:13 PM PDT 24
Finished Aug 19 05:13:20 PM PDT 24
Peak memory 200684 kb
Host smart-cc269a02-8b42-46ea-800b-49aaa6c9674c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421692338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3421692338
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.235924081
Short name T415
Test name
Test status
Simulation time 545097197 ps
CPU time 9.73 seconds
Started Aug 19 05:11:22 PM PDT 24
Finished Aug 19 05:11:32 PM PDT 24
Peak memory 200708 kb
Host smart-377f94d2-8135-4c94-b8db-71f1913e0fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235924081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.235924081
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3930650496
Short name T387
Test name
Test status
Simulation time 10281989580 ps
CPU time 966.42 seconds
Started Aug 19 05:11:25 PM PDT 24
Finished Aug 19 05:27:32 PM PDT 24
Peak memory 734424 kb
Host smart-ca1e1a93-5aef-4c55-93f5-2d19f58f5e78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930650496 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3930650496
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1896471315
Short name T132
Test name
Test status
Simulation time 9382894143 ps
CPU time 99.5 seconds
Started Aug 19 05:11:26 PM PDT 24
Finished Aug 19 05:13:06 PM PDT 24
Peak memory 200592 kb
Host smart-85aa0c6a-b150-48c2-9490-3edc223cfb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896471315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1896471315
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.8226273
Short name T290
Test name
Test status
Simulation time 16468959 ps
CPU time 0.58 seconds
Started Aug 19 05:11:10 PM PDT 24
Finished Aug 19 05:11:11 PM PDT 24
Peak memory 196416 kb
Host smart-c72ed731-847d-4e9f-88e1-45f3828ba7f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8226273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.8226273
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.573218755
Short name T3
Test name
Test status
Simulation time 773471541 ps
CPU time 11.96 seconds
Started Aug 19 05:11:29 PM PDT 24
Finished Aug 19 05:11:41 PM PDT 24
Peak memory 200528 kb
Host smart-70c93fff-0f8c-4a3b-bfd6-5d79724d29bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=573218755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.573218755
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1437408843
Short name T41
Test name
Test status
Simulation time 8582227897 ps
CPU time 27.38 seconds
Started Aug 19 05:11:36 PM PDT 24
Finished Aug 19 05:12:04 PM PDT 24
Peak memory 200728 kb
Host smart-636ca5c8-d9fa-461f-9636-69ce7ac32362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437408843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1437408843
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1320641440
Short name T158
Test name
Test status
Simulation time 2391987812 ps
CPU time 568.73 seconds
Started Aug 19 05:11:09 PM PDT 24
Finished Aug 19 05:20:38 PM PDT 24
Peak memory 713348 kb
Host smart-5855936b-f549-4328-b470-afb71ca47d95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1320641440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1320641440
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2085827434
Short name T28
Test name
Test status
Simulation time 13379771253 ps
CPU time 162.15 seconds
Started Aug 19 05:11:05 PM PDT 24
Finished Aug 19 05:13:53 PM PDT 24
Peak memory 200720 kb
Host smart-2cd027e3-942a-438c-be37-24dba8ec49bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085827434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2085827434
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1384660965
Short name T205
Test name
Test status
Simulation time 1657160176 ps
CPU time 93.65 seconds
Started Aug 19 05:11:13 PM PDT 24
Finished Aug 19 05:12:47 PM PDT 24
Peak memory 200708 kb
Host smart-a8e0fd4e-b24d-4661-b108-7df90d7abb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384660965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1384660965
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2644920424
Short name T522
Test name
Test status
Simulation time 514783492 ps
CPU time 8.83 seconds
Started Aug 19 05:11:07 PM PDT 24
Finished Aug 19 05:11:15 PM PDT 24
Peak memory 200632 kb
Host smart-32d03e6a-029c-4176-b185-5dbe849ccfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644920424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2644920424
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.958905363
Short name T104
Test name
Test status
Simulation time 5920982693 ps
CPU time 77.3 seconds
Started Aug 19 05:11:10 PM PDT 24
Finished Aug 19 05:12:27 PM PDT 24
Peak memory 200780 kb
Host smart-af9fa994-3843-4f25-8f08-e7cbd6efee90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958905363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.958905363
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2738421083
Short name T180
Test name
Test status
Simulation time 21520415 ps
CPU time 0.6 seconds
Started Aug 19 05:11:27 PM PDT 24
Finished Aug 19 05:11:28 PM PDT 24
Peak memory 197440 kb
Host smart-5476b74a-9a15-47d1-9fbe-8e6bf357bfd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738421083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2738421083
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.537513520
Short name T93
Test name
Test status
Simulation time 652874492 ps
CPU time 33.6 seconds
Started Aug 19 05:11:18 PM PDT 24
Finished Aug 19 05:11:52 PM PDT 24
Peak memory 200576 kb
Host smart-edcd8a0e-882d-48d1-a4ec-e1b41941f210
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=537513520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.537513520
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.4147708074
Short name T355
Test name
Test status
Simulation time 268532047 ps
CPU time 4.12 seconds
Started Aug 19 05:11:13 PM PDT 24
Finished Aug 19 05:11:17 PM PDT 24
Peak memory 200528 kb
Host smart-b849f368-bf23-46ff-9c6e-093b0de99c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147708074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.4147708074
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2414592225
Short name T521
Test name
Test status
Simulation time 1044375858 ps
CPU time 167.49 seconds
Started Aug 19 05:11:25 PM PDT 24
Finished Aug 19 05:14:13 PM PDT 24
Peak memory 585104 kb
Host smart-ad6e9bb4-eeac-4f02-95bf-27ffdf0118c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2414592225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2414592225
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.110927977
Short name T204
Test name
Test status
Simulation time 3370275420 ps
CPU time 48.24 seconds
Started Aug 19 05:11:10 PM PDT 24
Finished Aug 19 05:11:59 PM PDT 24
Peak memory 200788 kb
Host smart-5eec2fc7-bb8a-42fe-944a-07946a47d691
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110927977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.110927977
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1448824973
Short name T339
Test name
Test status
Simulation time 21056136777 ps
CPU time 146.97 seconds
Started Aug 19 05:11:15 PM PDT 24
Finished Aug 19 05:13:42 PM PDT 24
Peak memory 200716 kb
Host smart-e50765e7-69dd-45f4-85b0-88101805ec8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448824973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1448824973
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3052987561
Short name T177
Test name
Test status
Simulation time 1132993703 ps
CPU time 3.98 seconds
Started Aug 19 05:11:20 PM PDT 24
Finished Aug 19 05:11:24 PM PDT 24
Peak memory 200660 kb
Host smart-c4ebd1cc-445d-4a71-a6b1-9ff526052ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052987561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3052987561
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2274800644
Short name T11
Test name
Test status
Simulation time 13915138128 ps
CPU time 1573.47 seconds
Started Aug 19 05:11:10 PM PDT 24
Finished Aug 19 05:37:24 PM PDT 24
Peak memory 674328 kb
Host smart-8ed9b3f1-3b72-4e97-beaa-0a4e70cc9829
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274800644 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2274800644
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2533472841
Short name T477
Test name
Test status
Simulation time 21816414787 ps
CPU time 50.53 seconds
Started Aug 19 05:11:14 PM PDT 24
Finished Aug 19 05:12:05 PM PDT 24
Peak memory 200716 kb
Host smart-68842b91-59c1-45d0-873f-951efcdc29e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533472841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2533472841
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.819285810
Short name T409
Test name
Test status
Simulation time 44425765 ps
CPU time 0.59 seconds
Started Aug 19 05:11:29 PM PDT 24
Finished Aug 19 05:11:30 PM PDT 24
Peak memory 196696 kb
Host smart-94273104-4a6f-4608-ba53-e19a31b1a01d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819285810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.819285810
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3910466946
Short name T491
Test name
Test status
Simulation time 432168546 ps
CPU time 24.06 seconds
Started Aug 19 05:11:17 PM PDT 24
Finished Aug 19 05:11:41 PM PDT 24
Peak memory 200640 kb
Host smart-0f6a3f96-d77d-407f-aa7e-6160df5335b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3910466946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3910466946
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2391790952
Short name T190
Test name
Test status
Simulation time 2439158537 ps
CPU time 46.12 seconds
Started Aug 19 05:11:18 PM PDT 24
Finished Aug 19 05:12:04 PM PDT 24
Peak memory 200728 kb
Host smart-80aff645-8c4e-4a7f-9633-7a4d768ba9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391790952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2391790952
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2034265874
Short name T399
Test name
Test status
Simulation time 684490151 ps
CPU time 74.27 seconds
Started Aug 19 05:11:25 PM PDT 24
Finished Aug 19 05:12:39 PM PDT 24
Peak memory 310600 kb
Host smart-9efc8070-fc44-4add-a7c0-1b4bcaf84324
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2034265874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2034265874
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3521673604
Short name T525
Test name
Test status
Simulation time 7688577619 ps
CPU time 21.8 seconds
Started Aug 19 05:11:29 PM PDT 24
Finished Aug 19 05:11:51 PM PDT 24
Peak memory 200680 kb
Host smart-60638ee8-d2d0-4a88-afcd-26d1192c039c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521673604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3521673604
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.4196547581
Short name T53
Test name
Test status
Simulation time 6665728791 ps
CPU time 31.56 seconds
Started Aug 19 05:11:29 PM PDT 24
Finished Aug 19 05:12:01 PM PDT 24
Peak memory 200844 kb
Host smart-48a5d5f8-fd68-4134-9e0f-4dd0ca1bec56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196547581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.4196547581
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2331247408
Short name T375
Test name
Test status
Simulation time 709660911 ps
CPU time 8 seconds
Started Aug 19 05:11:31 PM PDT 24
Finished Aug 19 05:11:39 PM PDT 24
Peak memory 200660 kb
Host smart-395356c6-f2e9-4a60-93e9-d3ef0710abef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331247408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2331247408
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2268529206
Short name T147
Test name
Test status
Simulation time 46014165638 ps
CPU time 804.33 seconds
Started Aug 19 05:11:21 PM PDT 24
Finished Aug 19 05:24:45 PM PDT 24
Peak memory 200736 kb
Host smart-0e8c538a-5ef1-4ace-a573-bc0e8f55d457
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268529206 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2268529206
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.4133240049
Short name T38
Test name
Test status
Simulation time 7069658032 ps
CPU time 77.99 seconds
Started Aug 19 05:11:30 PM PDT 24
Finished Aug 19 05:12:48 PM PDT 24
Peak memory 200804 kb
Host smart-231023ee-3bb6-430b-89d6-809b8d82ec7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133240049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.4133240049
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.1799826230
Short name T80
Test name
Test status
Simulation time 48086033 ps
CPU time 0.59 seconds
Started Aug 19 05:11:32 PM PDT 24
Finished Aug 19 05:11:32 PM PDT 24
Peak memory 195672 kb
Host smart-56f9750f-48b1-428e-a309-ce268f545738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799826230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1799826230
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2971729708
Short name T68
Test name
Test status
Simulation time 1382139350 ps
CPU time 20.52 seconds
Started Aug 19 05:11:22 PM PDT 24
Finished Aug 19 05:11:42 PM PDT 24
Peak memory 200628 kb
Host smart-89d3268b-ec4e-4570-b83e-d6e2ff11c242
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2971729708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2971729708
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1686154452
Short name T384
Test name
Test status
Simulation time 1397160496 ps
CPU time 18.54 seconds
Started Aug 19 05:11:28 PM PDT 24
Finished Aug 19 05:11:47 PM PDT 24
Peak memory 200624 kb
Host smart-f5247772-079a-40c7-bee5-60cf845fc992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686154452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1686154452
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.831187271
Short name T440
Test name
Test status
Simulation time 29528629047 ps
CPU time 1567.85 seconds
Started Aug 19 05:11:26 PM PDT 24
Finished Aug 19 05:37:34 PM PDT 24
Peak memory 715484 kb
Host smart-642674a9-e28b-456a-9cec-8cfce09248f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=831187271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.831187271
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.461126237
Short name T15
Test name
Test status
Simulation time 2854884624 ps
CPU time 51.77 seconds
Started Aug 19 05:11:27 PM PDT 24
Finished Aug 19 05:12:18 PM PDT 24
Peak memory 200812 kb
Host smart-53ad5e01-7496-4850-b4a1-4bb933f91993
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461126237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.461126237
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1092724314
Short name T35
Test name
Test status
Simulation time 4790054390 ps
CPU time 63.74 seconds
Started Aug 19 05:11:19 PM PDT 24
Finished Aug 19 05:12:23 PM PDT 24
Peak memory 200724 kb
Host smart-89f9a978-c19e-4de4-8a13-c073414e5bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092724314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1092724314
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.321790482
Short name T166
Test name
Test status
Simulation time 159708072 ps
CPU time 2.54 seconds
Started Aug 19 05:11:26 PM PDT 24
Finished Aug 19 05:11:29 PM PDT 24
Peak memory 200652 kb
Host smart-c2c53e6b-c8ea-4255-9574-8ec01fb4fb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321790482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.321790482
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2960639096
Short name T150
Test name
Test status
Simulation time 13096439129 ps
CPU time 1360.7 seconds
Started Aug 19 05:11:19 PM PDT 24
Finished Aug 19 05:33:59 PM PDT 24
Peak memory 719220 kb
Host smart-2db5b140-878b-411e-889b-6f9e0b5aeddf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960639096 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2960639096
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.202673240
Short name T34
Test name
Test status
Simulation time 5127694545 ps
CPU time 131.51 seconds
Started Aug 19 05:11:25 PM PDT 24
Finished Aug 19 05:13:37 PM PDT 24
Peak memory 200756 kb
Host smart-ba7c10ea-6020-4407-b926-0b1bbe86fc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202673240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.202673240
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1289157944
Short name T380
Test name
Test status
Simulation time 45648265 ps
CPU time 0.58 seconds
Started Aug 19 05:11:30 PM PDT 24
Finished Aug 19 05:11:31 PM PDT 24
Peak memory 195728 kb
Host smart-9ba048a2-ff9d-4e75-845b-4ee796170f3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289157944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1289157944
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2829277546
Short name T298
Test name
Test status
Simulation time 11141590351 ps
CPU time 50.01 seconds
Started Aug 19 05:11:18 PM PDT 24
Finished Aug 19 05:12:08 PM PDT 24
Peak memory 200688 kb
Host smart-3b26f57e-b558-43f8-8053-f6e9fea0c372
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2829277546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2829277546
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1322697065
Short name T152
Test name
Test status
Simulation time 1489073126 ps
CPU time 39.52 seconds
Started Aug 19 05:11:28 PM PDT 24
Finished Aug 19 05:12:07 PM PDT 24
Peak memory 200652 kb
Host smart-8922a52f-4ee8-4db3-8004-277ca82f3ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322697065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1322697065
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1647935590
Short name T304
Test name
Test status
Simulation time 14107998479 ps
CPU time 703.67 seconds
Started Aug 19 05:11:26 PM PDT 24
Finished Aug 19 05:23:10 PM PDT 24
Peak memory 693600 kb
Host smart-9878719f-fed7-4dc3-8a4d-77f7f1fd351d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647935590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1647935590
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1138623919
Short name T275
Test name
Test status
Simulation time 4535131806 ps
CPU time 61.51 seconds
Started Aug 19 05:11:25 PM PDT 24
Finished Aug 19 05:12:27 PM PDT 24
Peak memory 200728 kb
Host smart-8002288d-88c4-4bb1-a820-ce5d2e95eb87
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138623919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1138623919
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3124292314
Short name T40
Test name
Test status
Simulation time 11449756570 ps
CPU time 32.64 seconds
Started Aug 19 05:11:26 PM PDT 24
Finished Aug 19 05:11:58 PM PDT 24
Peak memory 200716 kb
Host smart-c892d9f4-7be8-4963-8a56-d7aac0653f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124292314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3124292314
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1670876566
Short name T270
Test name
Test status
Simulation time 1066644371 ps
CPU time 4.81 seconds
Started Aug 19 05:11:27 PM PDT 24
Finished Aug 19 05:11:32 PM PDT 24
Peak memory 200676 kb
Host smart-5faed451-b88a-4fa5-8717-5c04cc3b1e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670876566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1670876566
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2354746801
Short name T460
Test name
Test status
Simulation time 204794138104 ps
CPU time 2632.64 seconds
Started Aug 19 05:11:31 PM PDT 24
Finished Aug 19 05:55:24 PM PDT 24
Peak memory 798068 kb
Host smart-df7f2ff0-fbe3-4d44-8c11-fcc614cc9bb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354746801 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2354746801
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.2522814463
Short name T463
Test name
Test status
Simulation time 24152730788 ps
CPU time 115.44 seconds
Started Aug 19 05:11:22 PM PDT 24
Finished Aug 19 05:13:18 PM PDT 24
Peak memory 200720 kb
Host smart-6feded3f-09b3-4f68-a356-a9bebe1fa99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522814463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.2522814463
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.841141791
Short name T333
Test name
Test status
Simulation time 13051229 ps
CPU time 0.6 seconds
Started Aug 19 05:11:23 PM PDT 24
Finished Aug 19 05:11:24 PM PDT 24
Peak memory 196756 kb
Host smart-c2bef339-d3b3-4cc7-8f62-9de1c16aa755
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841141791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.841141791
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.728964188
Short name T367
Test name
Test status
Simulation time 2186463315 ps
CPU time 63.49 seconds
Started Aug 19 05:11:18 PM PDT 24
Finished Aug 19 05:12:22 PM PDT 24
Peak memory 200740 kb
Host smart-0f657056-de17-4d89-b12c-80cebf992be2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=728964188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.728964188
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.120816884
Short name T172
Test name
Test status
Simulation time 29468940 ps
CPU time 1.6 seconds
Started Aug 19 05:11:17 PM PDT 24
Finished Aug 19 05:11:19 PM PDT 24
Peak memory 200556 kb
Host smart-4e7a7090-170b-4da2-ba76-e72e4498fdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120816884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.120816884
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2274456920
Short name T76
Test name
Test status
Simulation time 696663757 ps
CPU time 101.23 seconds
Started Aug 19 05:11:16 PM PDT 24
Finished Aug 19 05:12:57 PM PDT 24
Peak memory 352668 kb
Host smart-21f6c5e3-f3f4-4ba3-9c47-8fbeb7727e99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2274456920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2274456920
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3257155905
Short name T200
Test name
Test status
Simulation time 2269959340 ps
CPU time 123.98 seconds
Started Aug 19 05:11:25 PM PDT 24
Finished Aug 19 05:13:29 PM PDT 24
Peak memory 200660 kb
Host smart-292051ab-016f-4308-bac8-d6126b65e3bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257155905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3257155905
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1299916196
Short name T451
Test name
Test status
Simulation time 4622914159 ps
CPU time 62.82 seconds
Started Aug 19 05:11:31 PM PDT 24
Finished Aug 19 05:12:34 PM PDT 24
Peak memory 200708 kb
Host smart-f8351b19-4675-4730-be36-58ddf68da5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299916196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1299916196
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.79684400
Short name T374
Test name
Test status
Simulation time 1792234061 ps
CPU time 4.95 seconds
Started Aug 19 05:11:22 PM PDT 24
Finished Aug 19 05:11:27 PM PDT 24
Peak memory 200632 kb
Host smart-d1e3135e-eeb6-4f3d-92c0-cd9e86e09a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79684400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.79684400
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.4112533981
Short name T154
Test name
Test status
Simulation time 23262736702 ps
CPU time 2782.72 seconds
Started Aug 19 05:11:17 PM PDT 24
Finished Aug 19 05:57:40 PM PDT 24
Peak memory 811512 kb
Host smart-5cd60f8e-3a73-4f73-b875-85de2e43dcdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112533981 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.4112533981
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2935001910
Short name T509
Test name
Test status
Simulation time 364015007 ps
CPU time 20.88 seconds
Started Aug 19 05:11:17 PM PDT 24
Finished Aug 19 05:11:38 PM PDT 24
Peak memory 200636 kb
Host smart-7a51f98f-78be-4c10-ade5-92a2f7010abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935001910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2935001910
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.271255097
Short name T276
Test name
Test status
Simulation time 34959463 ps
CPU time 0.58 seconds
Started Aug 19 05:11:29 PM PDT 24
Finished Aug 19 05:11:30 PM PDT 24
Peak memory 196404 kb
Host smart-dd6519f5-881d-45e1-9ce5-9a143c1c2f6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271255097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.271255097
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.513204571
Short name T264
Test name
Test status
Simulation time 6709134986 ps
CPU time 103.94 seconds
Started Aug 19 05:11:24 PM PDT 24
Finished Aug 19 05:13:09 PM PDT 24
Peak memory 200724 kb
Host smart-e0ca1aa3-bff8-43d9-8bd0-ace36edb5acd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=513204571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.513204571
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.777348392
Short name T418
Test name
Test status
Simulation time 7491967964 ps
CPU time 27.91 seconds
Started Aug 19 05:11:28 PM PDT 24
Finished Aug 19 05:11:56 PM PDT 24
Peak memory 200784 kb
Host smart-2ba445d4-06ac-4069-bac4-dcfd50bbabfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777348392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.777348392
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.4110992183
Short name T181
Test name
Test status
Simulation time 42640125610 ps
CPU time 649.47 seconds
Started Aug 19 05:11:26 PM PDT 24
Finished Aug 19 05:22:15 PM PDT 24
Peak memory 701072 kb
Host smart-bae41254-15a2-4590-9f7d-f36ce3223739
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4110992183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.4110992183
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.933065576
Short name T228
Test name
Test status
Simulation time 26754505857 ps
CPU time 109.82 seconds
Started Aug 19 05:11:28 PM PDT 24
Finished Aug 19 05:13:18 PM PDT 24
Peak memory 200656 kb
Host smart-7aa9f309-c0bc-4755-a99e-7bc51c6230b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933065576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.933065576
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1402410523
Short name T513
Test name
Test status
Simulation time 10221359633 ps
CPU time 137.79 seconds
Started Aug 19 05:11:30 PM PDT 24
Finished Aug 19 05:13:48 PM PDT 24
Peak memory 217132 kb
Host smart-9a539809-bc65-4992-a825-0c6e8979c863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402410523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1402410523
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.4015896155
Short name T501
Test name
Test status
Simulation time 837749888 ps
CPU time 5.3 seconds
Started Aug 19 05:11:28 PM PDT 24
Finished Aug 19 05:11:34 PM PDT 24
Peak memory 200548 kb
Host smart-1281d823-65b9-4cba-9b8f-34bb92dccfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015896155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.4015896155
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.754394040
Short name T303
Test name
Test status
Simulation time 13681436892 ps
CPU time 57.61 seconds
Started Aug 19 05:11:24 PM PDT 24
Finished Aug 19 05:12:22 PM PDT 24
Peak memory 200748 kb
Host smart-a54157e3-3a80-46db-85ef-abe975a0e9e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754394040 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.754394040
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3404163851
Short name T94
Test name
Test status
Simulation time 7567588879 ps
CPU time 9.26 seconds
Started Aug 19 05:11:27 PM PDT 24
Finished Aug 19 05:11:37 PM PDT 24
Peak memory 200664 kb
Host smart-8502174e-deb0-42b8-9b00-d5cabc56ed7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404163851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3404163851
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.275756032
Short name T297
Test name
Test status
Simulation time 25430294 ps
CPU time 0.63 seconds
Started Aug 19 05:11:03 PM PDT 24
Finished Aug 19 05:11:04 PM PDT 24
Peak memory 196740 kb
Host smart-62189f47-bff3-4327-b443-78cedb0c7670
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275756032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.275756032
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1703407428
Short name T420
Test name
Test status
Simulation time 1091384811 ps
CPU time 57.74 seconds
Started Aug 19 05:11:01 PM PDT 24
Finished Aug 19 05:11:59 PM PDT 24
Peak memory 200704 kb
Host smart-d8f1b56d-68b0-4d53-a0ec-578bf19d428a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1703407428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1703407428
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3039136083
Short name T92
Test name
Test status
Simulation time 12580894233 ps
CPU time 61.38 seconds
Started Aug 19 05:10:59 PM PDT 24
Finished Aug 19 05:12:00 PM PDT 24
Peak memory 208924 kb
Host smart-a2f082a2-34b4-4137-b58d-b2e0b2dcaa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039136083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3039136083
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2267101312
Short name T281
Test name
Test status
Simulation time 3158046271 ps
CPU time 605.35 seconds
Started Aug 19 05:11:02 PM PDT 24
Finished Aug 19 05:21:07 PM PDT 24
Peak memory 720804 kb
Host smart-b19ab4a6-dd18-4c51-8878-0ff366af9e27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2267101312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2267101312
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.649045825
Short name T340
Test name
Test status
Simulation time 4552855971 ps
CPU time 128.76 seconds
Started Aug 19 05:10:58 PM PDT 24
Finished Aug 19 05:13:07 PM PDT 24
Peak memory 200724 kb
Host smart-a9bb2868-4775-4f71-a827-981389c5044f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649045825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.649045825
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3419634789
Short name T392
Test name
Test status
Simulation time 67414524 ps
CPU time 3.58 seconds
Started Aug 19 05:11:00 PM PDT 24
Finished Aug 19 05:11:04 PM PDT 24
Peak memory 200676 kb
Host smart-513ca790-4e78-4c77-af7d-f8449ca7b9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419634789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3419634789
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2537420105
Short name T65
Test name
Test status
Simulation time 330695121 ps
CPU time 1.05 seconds
Started Aug 19 05:11:03 PM PDT 24
Finished Aug 19 05:11:04 PM PDT 24
Peak memory 220020 kb
Host smart-dd491b14-2279-49dd-ac45-7d15e47c4b37
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537420105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2537420105
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3396531830
Short name T261
Test name
Test status
Simulation time 961346285 ps
CPU time 11.53 seconds
Started Aug 19 05:10:57 PM PDT 24
Finished Aug 19 05:11:08 PM PDT 24
Peak memory 200708 kb
Host smart-15307282-eac5-450f-99a9-b11c36641c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396531830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3396531830
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3427738080
Short name T263
Test name
Test status
Simulation time 128215523 ps
CPU time 2.5 seconds
Started Aug 19 05:11:02 PM PDT 24
Finished Aug 19 05:11:05 PM PDT 24
Peak memory 200652 kb
Host smart-6e6c1d1e-5006-4963-afdf-edf77646b8a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427738080 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3427738080
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.1823486399
Short name T98
Test name
Test status
Simulation time 43127824203 ps
CPU time 82.81 seconds
Started Aug 19 05:11:00 PM PDT 24
Finished Aug 19 05:12:23 PM PDT 24
Peak memory 200712 kb
Host smart-ee9f7c82-dfa6-47d0-8f40-29b08757a04c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1823486399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.1823486399
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.2152380050
Short name T395
Test name
Test status
Simulation time 9170043800 ps
CPU time 89.54 seconds
Started Aug 19 05:11:03 PM PDT 24
Finished Aug 19 05:12:32 PM PDT 24
Peak memory 200764 kb
Host smart-4fa699a7-b6b4-4610-adc7-1ab003cc70d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2152380050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.2152380050
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.484532620
Short name T319
Test name
Test status
Simulation time 2069729822 ps
CPU time 66.79 seconds
Started Aug 19 05:11:05 PM PDT 24
Finished Aug 19 05:12:12 PM PDT 24
Peak memory 200644 kb
Host smart-a231c53f-e99c-40c7-9638-27736873dc1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=484532620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.484532620
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.2058022153
Short name T397
Test name
Test status
Simulation time 44772496535 ps
CPU time 651.28 seconds
Started Aug 19 05:10:58 PM PDT 24
Finished Aug 19 05:21:49 PM PDT 24
Peak memory 200648 kb
Host smart-070c62a6-b722-470d-9a72-934e13468f71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2058022153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.2058022153
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.2028688027
Short name T159
Test name
Test status
Simulation time 271973070673 ps
CPU time 2239.61 seconds
Started Aug 19 05:10:57 PM PDT 24
Finished Aug 19 05:48:17 PM PDT 24
Peak memory 216196 kb
Host smart-fdc8286d-3425-47d7-9ddb-cf5d33605343
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2028688027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.2028688027
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.1725450649
Short name T143
Test name
Test status
Simulation time 586568172879 ps
CPU time 2419.55 seconds
Started Aug 19 05:10:58 PM PDT 24
Finished Aug 19 05:51:17 PM PDT 24
Peak memory 216028 kb
Host smart-20517948-5259-46e3-8042-e3e1fc0a06c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1725450649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1725450649
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3649761410
Short name T128
Test name
Test status
Simulation time 1313430609 ps
CPU time 58.91 seconds
Started Aug 19 05:11:05 PM PDT 24
Finished Aug 19 05:12:04 PM PDT 24
Peak memory 200704 kb
Host smart-496f7af8-5f3e-431f-8fff-d2cb4d90c9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649761410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3649761410
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2766516376
Short name T347
Test name
Test status
Simulation time 29197926 ps
CPU time 0.59 seconds
Started Aug 19 05:11:29 PM PDT 24
Finished Aug 19 05:11:30 PM PDT 24
Peak memory 196404 kb
Host smart-92cb2a84-ae0c-4763-87d4-cb9c195e34b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766516376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2766516376
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.775221740
Short name T439
Test name
Test status
Simulation time 5922038835 ps
CPU time 94.57 seconds
Started Aug 19 05:11:32 PM PDT 24
Finished Aug 19 05:13:06 PM PDT 24
Peak memory 200768 kb
Host smart-cf9b4d5e-7921-4cf1-b047-ea2dc10cb0b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=775221740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.775221740
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2205207639
Short name T212
Test name
Test status
Simulation time 15625761983 ps
CPU time 56.42 seconds
Started Aug 19 05:11:25 PM PDT 24
Finished Aug 19 05:12:22 PM PDT 24
Peak memory 200708 kb
Host smart-b508bf37-f903-4ce9-980a-4ba69e8cdf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205207639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2205207639
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.4268450639
Short name T199
Test name
Test status
Simulation time 5163569025 ps
CPU time 494.91 seconds
Started Aug 19 05:11:29 PM PDT 24
Finished Aug 19 05:19:44 PM PDT 24
Peak memory 641816 kb
Host smart-729d6ea7-88a3-46c3-bc59-bb8167119f00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4268450639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.4268450639
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3701045134
Short name T254
Test name
Test status
Simulation time 252579463403 ps
CPU time 249.34 seconds
Started Aug 19 05:11:26 PM PDT 24
Finished Aug 19 05:15:35 PM PDT 24
Peak memory 200704 kb
Host smart-f6d49473-6c3d-439d-b12f-7e3add0ddea0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701045134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3701045134
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3316873306
Short name T508
Test name
Test status
Simulation time 6087902126 ps
CPU time 78.64 seconds
Started Aug 19 05:11:28 PM PDT 24
Finished Aug 19 05:12:47 PM PDT 24
Peak memory 217000 kb
Host smart-2ddbc781-d129-4f1b-93f2-eeea1d07afe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316873306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3316873306
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1654081679
Short name T274
Test name
Test status
Simulation time 755106295 ps
CPU time 8.53 seconds
Started Aug 19 05:11:29 PM PDT 24
Finished Aug 19 05:11:38 PM PDT 24
Peak memory 200672 kb
Host smart-24c000bf-7918-4f28-9cde-18de3ca1d5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654081679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1654081679
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2609683804
Short name T373
Test name
Test status
Simulation time 1544431559 ps
CPU time 73.25 seconds
Started Aug 19 05:11:28 PM PDT 24
Finished Aug 19 05:12:41 PM PDT 24
Peak memory 200664 kb
Host smart-77a69749-0fdf-4b35-9d81-9daffc4343e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609683804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2609683804
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1022018449
Short name T410
Test name
Test status
Simulation time 59278202 ps
CPU time 0.6 seconds
Started Aug 19 05:11:33 PM PDT 24
Finished Aug 19 05:11:34 PM PDT 24
Peak memory 196720 kb
Host smart-f8d6822a-b0a8-4fcf-8dff-aa9401b3be0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022018449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1022018449
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.687879876
Short name T196
Test name
Test status
Simulation time 2047758258 ps
CPU time 56.81 seconds
Started Aug 19 05:11:27 PM PDT 24
Finished Aug 19 05:12:24 PM PDT 24
Peak memory 200644 kb
Host smart-3a756e5c-59d6-4e40-aeab-a0335f1c30c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=687879876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.687879876
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2389562890
Short name T469
Test name
Test status
Simulation time 3085960033 ps
CPU time 22.09 seconds
Started Aug 19 05:11:29 PM PDT 24
Finished Aug 19 05:11:52 PM PDT 24
Peak memory 200708 kb
Host smart-29e426e6-ebe2-4a7c-b8ae-49e5f344b8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389562890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2389562890
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1662973964
Short name T467
Test name
Test status
Simulation time 11898878223 ps
CPU time 1201.51 seconds
Started Aug 19 05:11:32 PM PDT 24
Finished Aug 19 05:31:33 PM PDT 24
Peak memory 759216 kb
Host smart-f97036bb-bd2c-45b0-8f5c-827ce7c6e9b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1662973964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1662973964
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3163920724
Short name T235
Test name
Test status
Simulation time 56621712112 ps
CPU time 193.53 seconds
Started Aug 19 05:11:34 PM PDT 24
Finished Aug 19 05:14:47 PM PDT 24
Peak memory 200812 kb
Host smart-31603f2a-3282-4bba-88bb-825d6e0ee743
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163920724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3163920724
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.51518533
Short name T284
Test name
Test status
Simulation time 1395024939 ps
CPU time 38.9 seconds
Started Aug 19 05:11:26 PM PDT 24
Finished Aug 19 05:12:05 PM PDT 24
Peak memory 200660 kb
Host smart-0cb9df0c-1987-4dd4-8465-fe7777148019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51518533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.51518533
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2130782793
Short name T213
Test name
Test status
Simulation time 1349325964 ps
CPU time 16.99 seconds
Started Aug 19 05:11:17 PM PDT 24
Finished Aug 19 05:11:34 PM PDT 24
Peak memory 200680 kb
Host smart-85a2da03-7de2-4341-b071-af303c8b6c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130782793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2130782793
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3178604928
Short name T478
Test name
Test status
Simulation time 178086149201 ps
CPU time 5673.46 seconds
Started Aug 19 05:11:34 PM PDT 24
Finished Aug 19 06:46:08 PM PDT 24
Peak memory 876440 kb
Host smart-7bce655a-3db7-463e-adad-2730b459fac1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178604928 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3178604928
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1310252954
Short name T411
Test name
Test status
Simulation time 18600022262 ps
CPU time 76.8 seconds
Started Aug 19 05:11:32 PM PDT 24
Finished Aug 19 05:12:49 PM PDT 24
Peak memory 200728 kb
Host smart-fb8e3193-80b8-4753-b552-e9aecd38d962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310252954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1310252954
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3980635631
Short name T383
Test name
Test status
Simulation time 39571833 ps
CPU time 0.59 seconds
Started Aug 19 05:11:29 PM PDT 24
Finished Aug 19 05:11:30 PM PDT 24
Peak memory 195728 kb
Host smart-48cc6822-d010-40f8-ab1e-eebc27db5804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980635631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3980635631
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1958302399
Short name T369
Test name
Test status
Simulation time 1864911919 ps
CPU time 20.54 seconds
Started Aug 19 05:11:29 PM PDT 24
Finished Aug 19 05:11:50 PM PDT 24
Peak memory 200676 kb
Host smart-d40baa89-f3f0-43e8-8d3e-8133fbd8d285
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1958302399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1958302399
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2750048193
Short name T398
Test name
Test status
Simulation time 20212328378 ps
CPU time 26.68 seconds
Started Aug 19 05:11:45 PM PDT 24
Finished Aug 19 05:12:11 PM PDT 24
Peak memory 200716 kb
Host smart-cd26435d-8705-44ac-9130-cf9c358e9be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750048193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2750048193
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.573624851
Short name T242
Test name
Test status
Simulation time 1336627575 ps
CPU time 61.37 seconds
Started Aug 19 05:11:30 PM PDT 24
Finished Aug 19 05:12:31 PM PDT 24
Peak memory 325140 kb
Host smart-40174f66-ccc1-4bc9-9660-35afb325080f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=573624851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.573624851
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2559482745
Short name T202
Test name
Test status
Simulation time 2881769821 ps
CPU time 50.09 seconds
Started Aug 19 05:11:30 PM PDT 24
Finished Aug 19 05:12:20 PM PDT 24
Peak memory 200588 kb
Host smart-d94452ca-8689-4289-9313-6a4ea60f2e81
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559482745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2559482745
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1651537824
Short name T354
Test name
Test status
Simulation time 16845615744 ps
CPU time 75.59 seconds
Started Aug 19 05:11:28 PM PDT 24
Finished Aug 19 05:12:49 PM PDT 24
Peak memory 200732 kb
Host smart-6da9a1dc-8cb6-4321-a025-0f50b46170cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651537824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1651537824
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2332851009
Short name T18
Test name
Test status
Simulation time 3509519946 ps
CPU time 10.58 seconds
Started Aug 19 05:11:40 PM PDT 24
Finished Aug 19 05:11:50 PM PDT 24
Peak memory 200740 kb
Host smart-42216f0c-a45f-41f6-90d7-f713e4ac4211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332851009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2332851009
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.4244389047
Short name T299
Test name
Test status
Simulation time 83977898465 ps
CPU time 2382.02 seconds
Started Aug 19 05:11:30 PM PDT 24
Finished Aug 19 05:51:13 PM PDT 24
Peak memory 673452 kb
Host smart-fb6a402e-664d-48e4-a8a9-9c60dd9c4ff0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244389047 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.4244389047
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2226684322
Short name T481
Test name
Test status
Simulation time 5878179919 ps
CPU time 19.95 seconds
Started Aug 19 05:11:32 PM PDT 24
Finished Aug 19 05:11:52 PM PDT 24
Peak memory 200716 kb
Host smart-da62eff8-c652-471a-a77e-28c143576eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226684322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2226684322
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2491171132
Short name T178
Test name
Test status
Simulation time 12944626 ps
CPU time 0.57 seconds
Started Aug 19 05:11:40 PM PDT 24
Finished Aug 19 05:11:41 PM PDT 24
Peak memory 195728 kb
Host smart-1d84c870-4a53-430f-9562-2e838e3fe79b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491171132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2491171132
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1275873908
Short name T25
Test name
Test status
Simulation time 7860457409 ps
CPU time 114.53 seconds
Started Aug 19 05:11:27 PM PDT 24
Finished Aug 19 05:13:22 PM PDT 24
Peak memory 200744 kb
Host smart-ce4cf75d-1441-45fc-842b-5681f862486a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1275873908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1275873908
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1558002906
Short name T161
Test name
Test status
Simulation time 4363513637 ps
CPU time 15.19 seconds
Started Aug 19 05:11:30 PM PDT 24
Finished Aug 19 05:11:45 PM PDT 24
Peak memory 200832 kb
Host smart-b42fe3e9-a386-4dc7-ab79-bcfc6c4c629d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558002906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1558002906
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2913527337
Short name T394
Test name
Test status
Simulation time 32725362155 ps
CPU time 1021.5 seconds
Started Aug 19 05:11:31 PM PDT 24
Finished Aug 19 05:28:32 PM PDT 24
Peak memory 537056 kb
Host smart-88b94f7b-ed22-4eca-9459-d735506d1b2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2913527337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2913527337
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2846602921
Short name T214
Test name
Test status
Simulation time 6178510710 ps
CPU time 53.39 seconds
Started Aug 19 05:11:30 PM PDT 24
Finished Aug 19 05:12:23 PM PDT 24
Peak memory 200732 kb
Host smart-ea6f90a4-f2a7-40c9-bad1-75344b945286
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846602921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2846602921
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3601920261
Short name T334
Test name
Test status
Simulation time 9674096260 ps
CPU time 171.39 seconds
Started Aug 19 05:11:29 PM PDT 24
Finished Aug 19 05:14:20 PM PDT 24
Peak memory 200752 kb
Host smart-f46295d6-aa39-49c2-9358-f905b8627e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601920261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3601920261
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3761732484
Short name T456
Test name
Test status
Simulation time 766002347 ps
CPU time 9.16 seconds
Started Aug 19 05:11:29 PM PDT 24
Finished Aug 19 05:11:39 PM PDT 24
Peak memory 200688 kb
Host smart-6e3fce69-8e72-4d9e-8673-93bb38f8019c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761732484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3761732484
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3562738217
Short name T441
Test name
Test status
Simulation time 6699159969 ps
CPU time 545.81 seconds
Started Aug 19 05:11:39 PM PDT 24
Finished Aug 19 05:20:45 PM PDT 24
Peak memory 506084 kb
Host smart-100cb52f-6df1-4779-b827-fa49dee78a7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562738217 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3562738217
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2500889455
Short name T393
Test name
Test status
Simulation time 81248271873 ps
CPU time 114.98 seconds
Started Aug 19 05:11:30 PM PDT 24
Finished Aug 19 05:13:25 PM PDT 24
Peak memory 200676 kb
Host smart-22c40d2c-ff11-4647-ae0c-e3f461331370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500889455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2500889455
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3721738314
Short name T510
Test name
Test status
Simulation time 8551327081 ps
CPU time 52.74 seconds
Started Aug 19 05:11:48 PM PDT 24
Finished Aug 19 05:12:41 PM PDT 24
Peak memory 216892 kb
Host smart-4918b141-a3b4-4a74-8274-79e03f26e018
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3721738314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3721738314
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1255189776
Short name T197
Test name
Test status
Simulation time 2921419926 ps
CPU time 53.56 seconds
Started Aug 19 05:11:39 PM PDT 24
Finished Aug 19 05:12:33 PM PDT 24
Peak memory 200744 kb
Host smart-e93db820-3018-41c1-bd47-f6e047edacf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255189776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1255189776
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1440806074
Short name T461
Test name
Test status
Simulation time 1166330756 ps
CPU time 207.74 seconds
Started Aug 19 05:11:38 PM PDT 24
Finished Aug 19 05:15:06 PM PDT 24
Peak memory 415920 kb
Host smart-5fc13f4a-44b7-4703-956e-2ef9f6d0e808
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1440806074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1440806074
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2705363803
Short name T360
Test name
Test status
Simulation time 28680424522 ps
CPU time 238.75 seconds
Started Aug 19 05:11:39 PM PDT 24
Finished Aug 19 05:15:38 PM PDT 24
Peak memory 200724 kb
Host smart-51042820-9e95-4062-a428-693e31623301
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705363803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2705363803
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1981470899
Short name T507
Test name
Test status
Simulation time 1357395278 ps
CPU time 72.22 seconds
Started Aug 19 05:11:39 PM PDT 24
Finished Aug 19 05:12:51 PM PDT 24
Peak memory 200632 kb
Host smart-61e9dbed-e989-4285-92bb-6da476355889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981470899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1981470899
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.4143487212
Short name T403
Test name
Test status
Simulation time 592875407 ps
CPU time 6.53 seconds
Started Aug 19 05:11:34 PM PDT 24
Finished Aug 19 05:11:40 PM PDT 24
Peak memory 200676 kb
Host smart-34ca0043-dc32-4db0-a187-3bd9fa9a464a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143487212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.4143487212
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.570234262
Short name T492
Test name
Test status
Simulation time 1245298806819 ps
CPU time 1130.59 seconds
Started Aug 19 05:11:37 PM PDT 24
Finished Aug 19 05:30:28 PM PDT 24
Peak memory 477112 kb
Host smart-9917a855-0165-48d9-8bbb-069e7f2c7db3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570234262 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.570234262
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2882573263
Short name T378
Test name
Test status
Simulation time 1338956684 ps
CPU time 30.36 seconds
Started Aug 19 05:11:33 PM PDT 24
Finished Aug 19 05:12:04 PM PDT 24
Peak memory 200660 kb
Host smart-102b6f9b-47f7-4994-b31b-1a294bd5bbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882573263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2882573263
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.898338531
Short name T185
Test name
Test status
Simulation time 12259176 ps
CPU time 0.6 seconds
Started Aug 19 05:11:37 PM PDT 24
Finished Aug 19 05:11:38 PM PDT 24
Peak memory 196424 kb
Host smart-dfa43d7e-785b-48f7-8681-883a7003f549
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898338531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.898338531
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1427361740
Short name T255
Test name
Test status
Simulation time 1439538881 ps
CPU time 88.35 seconds
Started Aug 19 05:11:29 PM PDT 24
Finished Aug 19 05:12:58 PM PDT 24
Peak memory 200688 kb
Host smart-f50638fd-c0c4-4bff-bf92-0530c26a5eee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1427361740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1427361740
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3625788155
Short name T222
Test name
Test status
Simulation time 5936848411 ps
CPU time 54.62 seconds
Started Aug 19 05:11:36 PM PDT 24
Finished Aug 19 05:12:31 PM PDT 24
Peak memory 200752 kb
Host smart-73854763-a5c0-458c-bb57-a4b0e6e73580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625788155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3625788155
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2928045302
Short name T348
Test name
Test status
Simulation time 6274383842 ps
CPU time 1386.32 seconds
Started Aug 19 05:11:33 PM PDT 24
Finished Aug 19 05:34:39 PM PDT 24
Peak memory 729196 kb
Host smart-6554f529-3a38-44d4-b9a2-82df5342b137
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2928045302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2928045302
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2216726843
Short name T359
Test name
Test status
Simulation time 6218201444 ps
CPU time 37.27 seconds
Started Aug 19 05:11:37 PM PDT 24
Finished Aug 19 05:12:14 PM PDT 24
Peak memory 200744 kb
Host smart-7bf99d47-2dc3-4b21-9282-e34f39df29a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216726843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2216726843
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1003677687
Short name T206
Test name
Test status
Simulation time 11095702368 ps
CPU time 160.55 seconds
Started Aug 19 05:11:44 PM PDT 24
Finished Aug 19 05:14:24 PM PDT 24
Peak memory 208984 kb
Host smart-f430eb1e-e558-4df9-94b6-7c5ff1c171ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003677687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1003677687
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3875492028
Short name T388
Test name
Test status
Simulation time 94280931 ps
CPU time 4.89 seconds
Started Aug 19 05:11:36 PM PDT 24
Finished Aug 19 05:11:41 PM PDT 24
Peak memory 200680 kb
Host smart-6f6fe766-5ef9-4db5-b551-84cfd4152df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875492028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3875492028
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1292302698
Short name T209
Test name
Test status
Simulation time 92817931522 ps
CPU time 3334.09 seconds
Started Aug 19 05:11:33 PM PDT 24
Finished Aug 19 06:07:08 PM PDT 24
Peak memory 817388 kb
Host smart-93988339-6385-416b-bdfc-31b394a0938b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292302698 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1292302698
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.958100316
Short name T50
Test name
Test status
Simulation time 36869570324 ps
CPU time 127.63 seconds
Started Aug 19 05:11:29 PM PDT 24
Finished Aug 19 05:13:37 PM PDT 24
Peak memory 200724 kb
Host smart-76e53c1a-c1d3-4594-ba3a-8530b69b719e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958100316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.958100316
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2664220877
Short name T436
Test name
Test status
Simulation time 13968036 ps
CPU time 0.61 seconds
Started Aug 19 05:11:43 PM PDT 24
Finished Aug 19 05:11:44 PM PDT 24
Peak memory 197436 kb
Host smart-b30b0e55-adf9-48d2-ae8e-c18c74add4c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664220877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2664220877
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1868750807
Short name T223
Test name
Test status
Simulation time 989800886 ps
CPU time 27.56 seconds
Started Aug 19 05:11:33 PM PDT 24
Finished Aug 19 05:12:01 PM PDT 24
Peak memory 200640 kb
Host smart-f1fd1fc9-eafa-4e54-ac35-b125428f9940
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1868750807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1868750807
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2599718840
Short name T186
Test name
Test status
Simulation time 456825374 ps
CPU time 6.34 seconds
Started Aug 19 05:11:42 PM PDT 24
Finished Aug 19 05:11:48 PM PDT 24
Peak memory 200648 kb
Host smart-8da23f3c-9939-4712-b0f9-0dbc203e4114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599718840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2599718840
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.227579855
Short name T278
Test name
Test status
Simulation time 22765756791 ps
CPU time 1271.81 seconds
Started Aug 19 05:11:30 PM PDT 24
Finished Aug 19 05:32:42 PM PDT 24
Peak memory 761008 kb
Host smart-5644fe8d-61ac-4b64-9f8b-e0fc9e068d21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=227579855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.227579855
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3975451493
Short name T256
Test name
Test status
Simulation time 11957581447 ps
CPU time 57.61 seconds
Started Aug 19 05:11:29 PM PDT 24
Finished Aug 19 05:12:27 PM PDT 24
Peak memory 200672 kb
Host smart-70d0d46b-5771-4212-867b-551b4570e459
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975451493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3975451493
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1683821863
Short name T48
Test name
Test status
Simulation time 1567985319 ps
CPU time 45.29 seconds
Started Aug 19 05:11:31 PM PDT 24
Finished Aug 19 05:12:16 PM PDT 24
Peak memory 200668 kb
Host smart-f305c2ed-150c-4a01-99f1-2c4f93ce7444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683821863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1683821863
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2653394575
Short name T406
Test name
Test status
Simulation time 625581728 ps
CPU time 6.9 seconds
Started Aug 19 05:11:45 PM PDT 24
Finished Aug 19 05:11:52 PM PDT 24
Peak memory 200600 kb
Host smart-1bbe8950-d833-4744-a143-ea37fa41bb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653394575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2653394575
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1018173647
Short name T207
Test name
Test status
Simulation time 23201867975 ps
CPU time 105.33 seconds
Started Aug 19 05:11:40 PM PDT 24
Finished Aug 19 05:13:26 PM PDT 24
Peak memory 200748 kb
Host smart-87230c37-eafc-4052-b171-a588281a7d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018173647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1018173647
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.294774547
Short name T457
Test name
Test status
Simulation time 21330144 ps
CPU time 0.62 seconds
Started Aug 19 05:11:28 PM PDT 24
Finished Aug 19 05:11:29 PM PDT 24
Peak memory 196728 kb
Host smart-3b8813fe-b7b1-45b1-a753-a225debb4c5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294774547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.294774547
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.4168061989
Short name T43
Test name
Test status
Simulation time 41208171 ps
CPU time 2.2 seconds
Started Aug 19 05:11:33 PM PDT 24
Finished Aug 19 05:11:35 PM PDT 24
Peak memory 200528 kb
Host smart-56466cca-51d7-4a54-9101-6f5bd88e34d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4168061989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.4168061989
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3057071146
Short name T260
Test name
Test status
Simulation time 16998754617 ps
CPU time 77.45 seconds
Started Aug 19 05:11:38 PM PDT 24
Finished Aug 19 05:12:56 PM PDT 24
Peak memory 208896 kb
Host smart-da7a7b0a-f340-47a1-88eb-c4bda0733814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057071146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3057071146
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1499749041
Short name T455
Test name
Test status
Simulation time 4344780722 ps
CPU time 802.02 seconds
Started Aug 19 05:11:35 PM PDT 24
Finished Aug 19 05:24:58 PM PDT 24
Peak memory 535392 kb
Host smart-6013709f-d332-4dce-b2e9-211db713d760
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1499749041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1499749041
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3773843980
Short name T234
Test name
Test status
Simulation time 15205454236 ps
CPU time 202.69 seconds
Started Aug 19 05:11:44 PM PDT 24
Finished Aug 19 05:15:06 PM PDT 24
Peak memory 200744 kb
Host smart-7703a225-e511-4205-a8d6-74cbff3f53a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773843980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3773843980
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3739249498
Short name T365
Test name
Test status
Simulation time 9185273637 ps
CPU time 81.23 seconds
Started Aug 19 05:11:31 PM PDT 24
Finished Aug 19 05:12:53 PM PDT 24
Peak memory 200812 kb
Host smart-5b08c694-08a2-49d9-b960-91fdbb9bbfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739249498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3739249498
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1356740051
Short name T315
Test name
Test status
Simulation time 5526841969 ps
CPU time 16.33 seconds
Started Aug 19 05:11:30 PM PDT 24
Finished Aug 19 05:11:47 PM PDT 24
Peak memory 200712 kb
Host smart-e7164a9b-69a8-42b2-8998-16cdcdff06be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356740051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1356740051
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3425730390
Short name T423
Test name
Test status
Simulation time 21857152992 ps
CPU time 1684.54 seconds
Started Aug 19 05:11:34 PM PDT 24
Finished Aug 19 05:39:39 PM PDT 24
Peak memory 757024 kb
Host smart-858d4d23-0faf-4bf2-b747-9b17e7752c3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425730390 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3425730390
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1422735095
Short name T100
Test name
Test status
Simulation time 37248399336 ps
CPU time 130.09 seconds
Started Aug 19 05:11:31 PM PDT 24
Finished Aug 19 05:13:41 PM PDT 24
Peak memory 200712 kb
Host smart-eedf8728-9b77-4418-a537-18dc24901233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422735095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1422735095
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3281327330
Short name T233
Test name
Test status
Simulation time 49958359 ps
CPU time 0.59 seconds
Started Aug 19 05:11:43 PM PDT 24
Finished Aug 19 05:11:43 PM PDT 24
Peak memory 195736 kb
Host smart-6f30b5ce-3038-41b5-8d99-7fc0ac44b1aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281327330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3281327330
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3697305195
Short name T216
Test name
Test status
Simulation time 1011158105 ps
CPU time 62.71 seconds
Started Aug 19 05:11:40 PM PDT 24
Finished Aug 19 05:12:43 PM PDT 24
Peak memory 200632 kb
Host smart-aad9cd7b-4cb7-4dfd-b664-51dd7b6c337b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3697305195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3697305195
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2377348941
Short name T54
Test name
Test status
Simulation time 1825526435 ps
CPU time 59.86 seconds
Started Aug 19 05:11:31 PM PDT 24
Finished Aug 19 05:12:31 PM PDT 24
Peak memory 200680 kb
Host smart-50a22ea9-17e5-4d8d-a2c4-db4b573729a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377348941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2377348941
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.134199880
Short name T160
Test name
Test status
Simulation time 44492177 ps
CPU time 0.72 seconds
Started Aug 19 05:11:33 PM PDT 24
Finished Aug 19 05:11:34 PM PDT 24
Peak memory 198844 kb
Host smart-c142fee4-2cf7-4c71-a186-8f80887391d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=134199880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.134199880
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1938026635
Short name T179
Test name
Test status
Simulation time 1317923243 ps
CPU time 71.98 seconds
Started Aug 19 05:11:30 PM PDT 24
Finished Aug 19 05:12:43 PM PDT 24
Peak memory 200632 kb
Host smart-fd307e89-5734-479c-be23-9e5be1e78960
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938026635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1938026635
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.4174094228
Short name T265
Test name
Test status
Simulation time 8027804450 ps
CPU time 114.03 seconds
Started Aug 19 05:11:34 PM PDT 24
Finished Aug 19 05:13:28 PM PDT 24
Peak memory 217108 kb
Host smart-90fb9fa6-5efe-4845-8349-1227e0b1ce38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174094228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.4174094228
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3434682424
Short name T146
Test name
Test status
Simulation time 569024954 ps
CPU time 6.76 seconds
Started Aug 19 05:11:32 PM PDT 24
Finished Aug 19 05:11:38 PM PDT 24
Peak memory 200624 kb
Host smart-a7cbda8a-8a9d-4999-864f-0f778e7c2b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434682424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3434682424
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.1549118602
Short name T498
Test name
Test status
Simulation time 7565978175 ps
CPU time 29.35 seconds
Started Aug 19 05:11:30 PM PDT 24
Finished Aug 19 05:12:00 PM PDT 24
Peak memory 200728 kb
Host smart-e364e74d-3b9c-49f7-8910-b2314d28ed49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549118602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1549118602
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2792229718
Short name T445
Test name
Test status
Simulation time 15492923 ps
CPU time 0.65 seconds
Started Aug 19 05:11:39 PM PDT 24
Finished Aug 19 05:11:40 PM PDT 24
Peak memory 196756 kb
Host smart-5417921c-a271-45f5-8ee4-cf0e7b8a279b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792229718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2792229718
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.4040416417
Short name T45
Test name
Test status
Simulation time 4584856064 ps
CPU time 48.03 seconds
Started Aug 19 05:11:41 PM PDT 24
Finished Aug 19 05:12:29 PM PDT 24
Peak memory 200876 kb
Host smart-79a51375-050e-4e4e-99c8-1d778ec6e902
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4040416417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.4040416417
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1913876483
Short name T271
Test name
Test status
Simulation time 2971667561 ps
CPU time 481.61 seconds
Started Aug 19 05:11:37 PM PDT 24
Finished Aug 19 05:19:39 PM PDT 24
Peak memory 649804 kb
Host smart-90e49d9b-b12d-4c12-9336-aed451ca6891
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1913876483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1913876483
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2967579968
Short name T312
Test name
Test status
Simulation time 4069238564 ps
CPU time 59.66 seconds
Started Aug 19 05:11:34 PM PDT 24
Finished Aug 19 05:12:34 PM PDT 24
Peak memory 200780 kb
Host smart-0ef90549-b45d-4f55-9e57-4e69a47b1f42
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967579968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2967579968
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1083684576
Short name T29
Test name
Test status
Simulation time 2612149986 ps
CPU time 149.99 seconds
Started Aug 19 05:11:44 PM PDT 24
Finished Aug 19 05:14:14 PM PDT 24
Peak memory 200796 kb
Host smart-93ac8f65-8380-4ca1-b3ee-20565aa58eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083684576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1083684576
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.713218796
Short name T453
Test name
Test status
Simulation time 1200838967 ps
CPU time 17.44 seconds
Started Aug 19 05:11:32 PM PDT 24
Finished Aug 19 05:11:50 PM PDT 24
Peak memory 200652 kb
Host smart-7aaa94d1-3157-4700-b5fb-5bbe36a61cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713218796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.713218796
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3331877060
Short name T91
Test name
Test status
Simulation time 198734215848 ps
CPU time 2596.1 seconds
Started Aug 19 05:11:32 PM PDT 24
Finished Aug 19 05:54:49 PM PDT 24
Peak memory 720088 kb
Host smart-4fbfac1c-8cbd-4c48-8939-c0ea17f1692c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331877060 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3331877060
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.479397529
Short name T412
Test name
Test status
Simulation time 9210378193 ps
CPU time 128.09 seconds
Started Aug 19 05:11:41 PM PDT 24
Finished Aug 19 05:13:49 PM PDT 24
Peak memory 200684 kb
Host smart-9e3becca-6de8-4b0e-97d9-d4c139b4c6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479397529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.479397529
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2234851212
Short name T448
Test name
Test status
Simulation time 38823210 ps
CPU time 0.61 seconds
Started Aug 19 05:11:00 PM PDT 24
Finished Aug 19 05:11:00 PM PDT 24
Peak memory 197400 kb
Host smart-89cf01a9-eca8-4eeb-bef7-2c1e7c5fe900
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234851212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2234851212
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1278149477
Short name T217
Test name
Test status
Simulation time 17909245318 ps
CPU time 27.61 seconds
Started Aug 19 05:11:01 PM PDT 24
Finished Aug 19 05:11:29 PM PDT 24
Peak memory 200732 kb
Host smart-11ea7030-9942-4c2e-99db-ddadf343a055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278149477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1278149477
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.827320569
Short name T517
Test name
Test status
Simulation time 1654231330 ps
CPU time 135.56 seconds
Started Aug 19 05:10:58 PM PDT 24
Finished Aug 19 05:13:14 PM PDT 24
Peak memory 568992 kb
Host smart-ce37b773-8f2b-483e-9584-29251d914b42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=827320569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.827320569
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.4077226695
Short name T2
Test name
Test status
Simulation time 1478060744 ps
CPU time 24.29 seconds
Started Aug 19 05:10:59 PM PDT 24
Finished Aug 19 05:11:24 PM PDT 24
Peak memory 200584 kb
Host smart-5c35c692-3c2a-4c25-9fb1-5aeb0797b3b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077226695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.4077226695
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.545240476
Short name T452
Test name
Test status
Simulation time 2928519276 ps
CPU time 52.07 seconds
Started Aug 19 05:11:01 PM PDT 24
Finished Aug 19 05:11:53 PM PDT 24
Peak memory 200704 kb
Host smart-ab4e3f69-e4e6-4d9a-a34c-c2f88d90cbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545240476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.545240476
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.4176575862
Short name T64
Test name
Test status
Simulation time 68624423 ps
CPU time 0.99 seconds
Started Aug 19 05:10:59 PM PDT 24
Finished Aug 19 05:11:01 PM PDT 24
Peak memory 219016 kb
Host smart-7d3710ad-6c7d-4d95-9235-7bab659d187e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176575862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.4176575862
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3205824002
Short name T192
Test name
Test status
Simulation time 307301294 ps
CPU time 4.36 seconds
Started Aug 19 05:10:59 PM PDT 24
Finished Aug 19 05:11:04 PM PDT 24
Peak memory 200644 kb
Host smart-3398f6e5-3129-4637-86f8-8e1bb49fa66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205824002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3205824002
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3822042011
Short name T10
Test name
Test status
Simulation time 30860065035 ps
CPU time 4141.88 seconds
Started Aug 19 05:11:00 PM PDT 24
Finished Aug 19 06:20:02 PM PDT 24
Peak memory 791000 kb
Host smart-7da1904c-2a3e-46da-8257-9ec2a3bddddf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822042011 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3822042011
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.480237942
Short name T22
Test name
Test status
Simulation time 36311365934 ps
CPU time 358.97 seconds
Started Aug 19 05:10:58 PM PDT 24
Finished Aug 19 05:16:57 PM PDT 24
Peak memory 479992 kb
Host smart-680c4e99-8ea2-4d62-bf92-51b5f1560282
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=480237942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.480237942
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.466318446
Short name T324
Test name
Test status
Simulation time 19857132957 ps
CPU time 76.99 seconds
Started Aug 19 05:10:58 PM PDT 24
Finished Aug 19 05:12:15 PM PDT 24
Peak memory 200692 kb
Host smart-9aaefab8-4e89-488f-a31d-62de732aa39d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=466318446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.466318446
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.2579755572
Short name T518
Test name
Test status
Simulation time 3202713361 ps
CPU time 54.5 seconds
Started Aug 19 05:11:16 PM PDT 24
Finished Aug 19 05:12:11 PM PDT 24
Peak memory 200776 kb
Host smart-42605c90-7dca-4ce0-a131-3dbd47189ccb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2579755572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.2579755572
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.3162316408
Short name T36
Test name
Test status
Simulation time 32106232842 ps
CPU time 131.57 seconds
Started Aug 19 05:10:59 PM PDT 24
Finished Aug 19 05:13:11 PM PDT 24
Peak memory 200700 kb
Host smart-427e88ae-10d8-4fed-aaf9-db4096179a04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3162316408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.3162316408
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.2336616657
Short name T368
Test name
Test status
Simulation time 9788041986 ps
CPU time 561.79 seconds
Started Aug 19 05:11:02 PM PDT 24
Finished Aug 19 05:20:24 PM PDT 24
Peak memory 200724 kb
Host smart-8479a2e2-5c52-4025-b194-31239a71d236
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2336616657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2336616657
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.3444750995
Short name T142
Test name
Test status
Simulation time 37874908601 ps
CPU time 1984.45 seconds
Started Aug 19 05:10:57 PM PDT 24
Finished Aug 19 05:44:01 PM PDT 24
Peak memory 216364 kb
Host smart-3ef8b24e-b2fe-429a-ab2e-10e45e044cb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3444750995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.3444750995
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.4163916096
Short name T356
Test name
Test status
Simulation time 50412057303 ps
CPU time 2238.24 seconds
Started Aug 19 05:10:59 PM PDT 24
Finished Aug 19 05:48:18 PM PDT 24
Peak memory 216176 kb
Host smart-2a053c77-a7bb-418e-87a3-331fc509ec6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4163916096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.4163916096
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.766139597
Short name T58
Test name
Test status
Simulation time 6280809613 ps
CPU time 87.42 seconds
Started Aug 19 05:11:03 PM PDT 24
Finished Aug 19 05:12:31 PM PDT 24
Peak memory 200732 kb
Host smart-d2edfa09-b308-47b8-8b74-6d45744c0d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766139597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.766139597
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2821416173
Short name T239
Test name
Test status
Simulation time 41916462 ps
CPU time 0.61 seconds
Started Aug 19 05:11:35 PM PDT 24
Finished Aug 19 05:11:36 PM PDT 24
Peak memory 197392 kb
Host smart-b7404561-ed54-4d0d-a9de-cafc351c9a5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821416173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2821416173
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.147283407
Short name T371
Test name
Test status
Simulation time 241727450 ps
CPU time 3.74 seconds
Started Aug 19 05:11:33 PM PDT 24
Finished Aug 19 05:11:37 PM PDT 24
Peak memory 200572 kb
Host smart-166630d2-5df7-424e-ac02-9a010c868091
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=147283407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.147283407
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1112030545
Short name T421
Test name
Test status
Simulation time 17047969514 ps
CPU time 61.14 seconds
Started Aug 19 05:11:33 PM PDT 24
Finished Aug 19 05:12:35 PM PDT 24
Peak memory 200756 kb
Host smart-9a186026-1711-4926-80a1-646b5ebf395f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112030545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1112030545
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2492117970
Short name T344
Test name
Test status
Simulation time 6134900295 ps
CPU time 230.96 seconds
Started Aug 19 05:11:30 PM PDT 24
Finished Aug 19 05:15:21 PM PDT 24
Peak memory 595656 kb
Host smart-a5a623a5-f5b4-4859-8c00-9ac5d0c195f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2492117970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2492117970
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3403537493
Short name T482
Test name
Test status
Simulation time 65074248984 ps
CPU time 273.84 seconds
Started Aug 19 05:11:33 PM PDT 24
Finished Aug 19 05:16:07 PM PDT 24
Peak memory 200720 kb
Host smart-dabd6002-9262-475e-af38-b85b0e167b61
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403537493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3403537493
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3049918898
Short name T419
Test name
Test status
Simulation time 1755378646 ps
CPU time 107.75 seconds
Started Aug 19 05:11:37 PM PDT 24
Finished Aug 19 05:13:25 PM PDT 24
Peak memory 200724 kb
Host smart-c4b270cc-024a-4f7f-964f-f571dd95c3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049918898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3049918898
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3819536158
Short name T311
Test name
Test status
Simulation time 211764647 ps
CPU time 9.12 seconds
Started Aug 19 05:11:36 PM PDT 24
Finished Aug 19 05:11:46 PM PDT 24
Peak memory 200640 kb
Host smart-6b6c28d2-771e-494f-a203-6e70f1053e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819536158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3819536158
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.238935144
Short name T89
Test name
Test status
Simulation time 110356591337 ps
CPU time 468.59 seconds
Started Aug 19 05:11:43 PM PDT 24
Finished Aug 19 05:19:32 PM PDT 24
Peak memory 574040 kb
Host smart-058a795d-506c-4e9e-bde2-3054eab27227
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238935144 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.238935144
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3221765333
Short name T487
Test name
Test status
Simulation time 10687981128 ps
CPU time 89.51 seconds
Started Aug 19 05:11:37 PM PDT 24
Finished Aug 19 05:13:07 PM PDT 24
Peak memory 200624 kb
Host smart-73ec01c3-9e5a-4806-9b91-31592f7b57da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221765333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3221765333
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2564745900
Short name T78
Test name
Test status
Simulation time 29306774 ps
CPU time 0.57 seconds
Started Aug 19 05:11:47 PM PDT 24
Finished Aug 19 05:11:47 PM PDT 24
Peak memory 196364 kb
Host smart-99096a1c-cce1-4c8e-b792-400b8d2654af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564745900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2564745900
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3701827590
Short name T55
Test name
Test status
Simulation time 2158513426 ps
CPU time 30.53 seconds
Started Aug 19 05:11:33 PM PDT 24
Finished Aug 19 05:12:04 PM PDT 24
Peak memory 200776 kb
Host smart-b31121a3-1926-40ad-bb40-6b712c3393cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3701827590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3701827590
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3061689663
Short name T328
Test name
Test status
Simulation time 10504700993 ps
CPU time 46.85 seconds
Started Aug 19 05:11:36 PM PDT 24
Finished Aug 19 05:12:23 PM PDT 24
Peak memory 200732 kb
Host smart-6832db5a-9649-4db6-99fa-4bb9bbde8ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061689663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3061689663
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3593992142
Short name T386
Test name
Test status
Simulation time 1632722694 ps
CPU time 99.86 seconds
Started Aug 19 05:11:41 PM PDT 24
Finished Aug 19 05:13:21 PM PDT 24
Peak memory 462000 kb
Host smart-a91ccccd-2a49-4ea8-a549-5d0667a63781
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3593992142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3593992142
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.4201609464
Short name T168
Test name
Test status
Simulation time 8845001714 ps
CPU time 114.37 seconds
Started Aug 19 05:11:42 PM PDT 24
Finished Aug 19 05:13:37 PM PDT 24
Peak memory 200804 kb
Host smart-37b5b9c1-0172-42c6-82b8-40eae43ebc88
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201609464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.4201609464
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3460213793
Short name T447
Test name
Test status
Simulation time 3095036275 ps
CPU time 169.61 seconds
Started Aug 19 05:11:41 PM PDT 24
Finished Aug 19 05:14:31 PM PDT 24
Peak memory 200760 kb
Host smart-0ba07a65-2a94-42e9-b4fc-093cf3d58242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460213793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3460213793
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2722262908
Short name T283
Test name
Test status
Simulation time 697469174 ps
CPU time 7.96 seconds
Started Aug 19 05:11:40 PM PDT 24
Finished Aug 19 05:11:48 PM PDT 24
Peak memory 200708 kb
Host smart-2e514b3c-b94e-4ec2-b348-b2bd838607cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722262908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2722262908
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.3663903285
Short name T425
Test name
Test status
Simulation time 4916806976 ps
CPU time 279.84 seconds
Started Aug 19 05:11:39 PM PDT 24
Finished Aug 19 05:16:19 PM PDT 24
Peak memory 200696 kb
Host smart-562b66a6-9ac3-4df4-b490-83414388146c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663903285 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3663903285
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1883662616
Short name T1
Test name
Test status
Simulation time 19257504443 ps
CPU time 80.74 seconds
Started Aug 19 05:11:40 PM PDT 24
Finished Aug 19 05:13:00 PM PDT 24
Peak memory 200724 kb
Host smart-2cdcae15-fa3b-4130-8a92-c10f609f6f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883662616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1883662616
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.439438401
Short name T42
Test name
Test status
Simulation time 18609016 ps
CPU time 0.58 seconds
Started Aug 19 05:11:49 PM PDT 24
Finished Aug 19 05:11:49 PM PDT 24
Peak memory 196696 kb
Host smart-f5a9b756-d5d9-4ff1-8b4b-c3b328d4d850
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439438401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.439438401
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1848531962
Short name T20
Test name
Test status
Simulation time 1082355033 ps
CPU time 67.06 seconds
Started Aug 19 05:11:48 PM PDT 24
Finished Aug 19 05:12:55 PM PDT 24
Peak memory 200644 kb
Host smart-91dd19e9-6b14-4704-9d05-b61bf8c9d746
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1848531962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1848531962
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.4146977359
Short name T83
Test name
Test status
Simulation time 79177432 ps
CPU time 4.12 seconds
Started Aug 19 05:11:45 PM PDT 24
Finished Aug 19 05:11:49 PM PDT 24
Peak memory 200640 kb
Host smart-b01100e2-dab5-4328-9f5f-0814dd1bf9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146977359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.4146977359
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3186961919
Short name T495
Test name
Test status
Simulation time 101964822289 ps
CPU time 1343.22 seconds
Started Aug 19 05:11:56 PM PDT 24
Finished Aug 19 05:34:20 PM PDT 24
Peak memory 740676 kb
Host smart-814cd43c-0e05-404f-999a-a7013e1927bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3186961919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3186961919
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3993327220
Short name T433
Test name
Test status
Simulation time 1699188872 ps
CPU time 22.31 seconds
Started Aug 19 05:11:45 PM PDT 24
Finished Aug 19 05:12:07 PM PDT 24
Peak memory 200612 kb
Host smart-fcda0d7d-1e8b-43fc-9847-530a63d03946
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993327220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3993327220
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2803905113
Short name T39
Test name
Test status
Simulation time 9227788663 ps
CPU time 141.44 seconds
Started Aug 19 05:11:45 PM PDT 24
Finished Aug 19 05:14:07 PM PDT 24
Peak memory 200912 kb
Host smart-972a98fa-011c-4d57-b6bd-3ce6ac9c2565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803905113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2803905113
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2163150135
Short name T401
Test name
Test status
Simulation time 219985132 ps
CPU time 2.42 seconds
Started Aug 19 05:11:41 PM PDT 24
Finished Aug 19 05:11:44 PM PDT 24
Peak memory 200496 kb
Host smart-f105e3d1-cd28-4189-bbc3-992d5151ca98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163150135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2163150135
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.405220884
Short name T229
Test name
Test status
Simulation time 102836244599 ps
CPU time 4841.06 seconds
Started Aug 19 05:11:43 PM PDT 24
Finished Aug 19 06:32:25 PM PDT 24
Peak memory 832940 kb
Host smart-a058b83c-fb9a-425b-9360-2aa22beed05d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405220884 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.405220884
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2833541785
Short name T505
Test name
Test status
Simulation time 16199495321 ps
CPU time 100.87 seconds
Started Aug 19 05:11:46 PM PDT 24
Finished Aug 19 05:13:27 PM PDT 24
Peak memory 200772 kb
Host smart-51a385a7-9ad6-44d9-a13b-7022806450a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833541785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2833541785
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2805338203
Short name T326
Test name
Test status
Simulation time 18315697 ps
CPU time 0.62 seconds
Started Aug 19 05:11:47 PM PDT 24
Finished Aug 19 05:11:48 PM PDT 24
Peak memory 196748 kb
Host smart-ae691083-4563-483d-8a02-2d0e45509034
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805338203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2805338203
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3584862665
Short name T407
Test name
Test status
Simulation time 5306055294 ps
CPU time 68.1 seconds
Started Aug 19 05:11:48 PM PDT 24
Finished Aug 19 05:12:56 PM PDT 24
Peak memory 200736 kb
Host smart-5618761f-8c03-458b-80e0-bf3f49588c84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3584862665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3584862665
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3250997906
Short name T494
Test name
Test status
Simulation time 15219969282 ps
CPU time 71.4 seconds
Started Aug 19 05:11:48 PM PDT 24
Finished Aug 19 05:13:00 PM PDT 24
Peak memory 208980 kb
Host smart-89140155-a6f5-4d9b-a643-ad8c55b8267b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250997906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3250997906
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.4147157009
Short name T252
Test name
Test status
Simulation time 26763731494 ps
CPU time 905.33 seconds
Started Aug 19 05:11:47 PM PDT 24
Finished Aug 19 05:26:53 PM PDT 24
Peak memory 725360 kb
Host smart-662c5db4-cd04-44f3-8581-400f9ba02f38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4147157009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.4147157009
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1905523954
Short name T243
Test name
Test status
Simulation time 2826785223 ps
CPU time 155.79 seconds
Started Aug 19 05:11:42 PM PDT 24
Finished Aug 19 05:14:18 PM PDT 24
Peak memory 200680 kb
Host smart-70ee63a9-33c2-4873-9f87-28bccad9b692
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905523954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1905523954
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.4162829374
Short name T309
Test name
Test status
Simulation time 14464800370 ps
CPU time 128.24 seconds
Started Aug 19 05:11:48 PM PDT 24
Finished Aug 19 05:13:57 PM PDT 24
Peak memory 200728 kb
Host smart-a21129f2-e357-4de2-822e-6f84a9cefd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162829374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.4162829374
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.20811734
Short name T464
Test name
Test status
Simulation time 98350727 ps
CPU time 1.27 seconds
Started Aug 19 05:11:44 PM PDT 24
Finished Aug 19 05:11:46 PM PDT 24
Peak memory 200664 kb
Host smart-2291b55d-4c76-4d47-8ce6-cb53fc49dfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20811734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.20811734
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2286964503
Short name T503
Test name
Test status
Simulation time 98181078554 ps
CPU time 3288.99 seconds
Started Aug 19 05:11:44 PM PDT 24
Finished Aug 19 06:06:34 PM PDT 24
Peak memory 741732 kb
Host smart-7d001bba-f892-48b1-9c6f-544ab4e2b438
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286964503 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2286964503
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2837589261
Short name T248
Test name
Test status
Simulation time 43642756778 ps
CPU time 149.54 seconds
Started Aug 19 05:11:50 PM PDT 24
Finished Aug 19 05:14:19 PM PDT 24
Peak memory 200728 kb
Host smart-98c3ce59-a0e3-4f48-8d45-6f947f4f5b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837589261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2837589261
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2432616233
Short name T61
Test name
Test status
Simulation time 19425707 ps
CPU time 0.64 seconds
Started Aug 19 05:11:47 PM PDT 24
Finished Aug 19 05:11:48 PM PDT 24
Peak memory 196772 kb
Host smart-c2169cbf-8007-401a-9130-fc6333979b96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432616233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2432616233
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.3284181656
Short name T302
Test name
Test status
Simulation time 18384688848 ps
CPU time 53.81 seconds
Started Aug 19 05:11:48 PM PDT 24
Finished Aug 19 05:12:42 PM PDT 24
Peak memory 200724 kb
Host smart-b47ddc0e-4f57-4d30-b159-81645c84f645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284181656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3284181656
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2004871798
Short name T238
Test name
Test status
Simulation time 14495171338 ps
CPU time 230.87 seconds
Started Aug 19 05:11:53 PM PDT 24
Finished Aug 19 05:15:44 PM PDT 24
Peak memory 601268 kb
Host smart-b960a910-5206-41e4-99b3-457555c6187b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2004871798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2004871798
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1903535638
Short name T320
Test name
Test status
Simulation time 9560527214 ps
CPU time 96.21 seconds
Started Aug 19 05:11:50 PM PDT 24
Finished Aug 19 05:13:26 PM PDT 24
Peak memory 200700 kb
Host smart-b920fb2f-e19c-4f6b-8f8f-12bf83e55ca0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903535638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1903535638
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1226053763
Short name T169
Test name
Test status
Simulation time 5088521665 ps
CPU time 92.26 seconds
Started Aug 19 05:11:50 PM PDT 24
Finished Aug 19 05:13:22 PM PDT 24
Peak memory 200716 kb
Host smart-0866ada7-22f1-4c33-b661-57e7fe39804c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226053763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1226053763
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.309914564
Short name T127
Test name
Test status
Simulation time 11603497428 ps
CPU time 11.51 seconds
Started Aug 19 05:11:52 PM PDT 24
Finished Aug 19 05:12:04 PM PDT 24
Peak memory 200740 kb
Host smart-2e5712d8-4eb2-4eeb-9e04-559b69b60658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309914564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.309914564
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.6454555
Short name T465
Test name
Test status
Simulation time 61395706823 ps
CPU time 78.88 seconds
Started Aug 19 05:11:48 PM PDT 24
Finished Aug 19 05:13:07 PM PDT 24
Peak memory 200588 kb
Host smart-33c62036-a237-484b-8ffc-3256e3b2db21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6454555 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.6454555
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2577034684
Short name T30
Test name
Test status
Simulation time 1107504227 ps
CPU time 31.33 seconds
Started Aug 19 05:11:57 PM PDT 24
Finished Aug 19 05:12:29 PM PDT 24
Peak memory 200660 kb
Host smart-0ca2833b-4b21-4474-a1f1-3b86fdb97dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577034684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2577034684
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.4181774527
Short name T63
Test name
Test status
Simulation time 185149204 ps
CPU time 0.61 seconds
Started Aug 19 05:11:44 PM PDT 24
Finished Aug 19 05:11:44 PM PDT 24
Peak memory 197288 kb
Host smart-b3377142-3c09-4e93-acde-d244d4b859af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181774527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.4181774527
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.792579751
Short name T358
Test name
Test status
Simulation time 562880634 ps
CPU time 34.89 seconds
Started Aug 19 05:11:48 PM PDT 24
Finished Aug 19 05:12:23 PM PDT 24
Peak memory 200628 kb
Host smart-460caf43-1704-45c4-9345-400b289ea849
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=792579751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.792579751
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3136860229
Short name T155
Test name
Test status
Simulation time 524253214 ps
CPU time 8.01 seconds
Started Aug 19 05:11:57 PM PDT 24
Finished Aug 19 05:12:05 PM PDT 24
Peak memory 200712 kb
Host smart-5e10ad50-b12e-45e0-a091-fd098ee3a4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136860229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3136860229
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2007485645
Short name T157
Test name
Test status
Simulation time 2570096572 ps
CPU time 493.71 seconds
Started Aug 19 05:11:45 PM PDT 24
Finished Aug 19 05:19:59 PM PDT 24
Peak memory 663272 kb
Host smart-b63c3857-f230-41b6-9cfa-c2a318376602
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2007485645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2007485645
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3330243899
Short name T390
Test name
Test status
Simulation time 24538837804 ps
CPU time 134.04 seconds
Started Aug 19 05:11:48 PM PDT 24
Finished Aug 19 05:14:02 PM PDT 24
Peak memory 200812 kb
Host smart-6d01565c-7b4f-424b-bd0b-4fd886400619
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330243899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3330243899
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.936758021
Short name T267
Test name
Test status
Simulation time 9764824964 ps
CPU time 142.71 seconds
Started Aug 19 05:11:47 PM PDT 24
Finished Aug 19 05:14:10 PM PDT 24
Peak memory 200712 kb
Host smart-aabae2d5-ea3e-4f70-8b9c-4437b71d5043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936758021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.936758021
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3403099594
Short name T396
Test name
Test status
Simulation time 941792417 ps
CPU time 4.7 seconds
Started Aug 19 05:11:45 PM PDT 24
Finished Aug 19 05:11:50 PM PDT 24
Peak memory 200708 kb
Host smart-7c08ad52-a40b-4913-9fe2-86629c445656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403099594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3403099594
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1551465633
Short name T131
Test name
Test status
Simulation time 305095991666 ps
CPU time 2330.49 seconds
Started Aug 19 05:11:45 PM PDT 24
Finished Aug 19 05:50:36 PM PDT 24
Peak memory 738500 kb
Host smart-39479ef1-4c78-4992-a282-3434f93efb69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551465633 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1551465633
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.505577004
Short name T101
Test name
Test status
Simulation time 418013731 ps
CPU time 24.54 seconds
Started Aug 19 05:11:52 PM PDT 24
Finished Aug 19 05:12:16 PM PDT 24
Peak memory 200640 kb
Host smart-d2f4ca14-269f-4c72-be05-4c1927204506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505577004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.505577004
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2441812099
Short name T33
Test name
Test status
Simulation time 41450122 ps
CPU time 0.63 seconds
Started Aug 19 05:11:48 PM PDT 24
Finished Aug 19 05:11:49 PM PDT 24
Peak memory 196756 kb
Host smart-8d9fba71-1699-44f2-a708-4c68688499ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441812099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2441812099
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3456333977
Short name T366
Test name
Test status
Simulation time 1800810813 ps
CPU time 114.31 seconds
Started Aug 19 05:11:50 PM PDT 24
Finished Aug 19 05:13:44 PM PDT 24
Peak memory 200636 kb
Host smart-3223cca0-5bd9-49dc-b9dd-45d66c6712dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3456333977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3456333977
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1442786713
Short name T497
Test name
Test status
Simulation time 1602959846 ps
CPU time 28.47 seconds
Started Aug 19 05:11:48 PM PDT 24
Finished Aug 19 05:12:16 PM PDT 24
Peak memory 200636 kb
Host smart-9fde63c1-44b3-4f7e-a644-904ca936ddc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442786713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1442786713
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1889680772
Short name T427
Test name
Test status
Simulation time 13969886048 ps
CPU time 650.48 seconds
Started Aug 19 05:11:53 PM PDT 24
Finished Aug 19 05:22:44 PM PDT 24
Peak memory 725048 kb
Host smart-a639d744-df4b-4f18-85bc-5fa38ca71d36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1889680772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1889680772
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.956593292
Short name T191
Test name
Test status
Simulation time 9055548864 ps
CPU time 165.21 seconds
Started Aug 19 05:11:47 PM PDT 24
Finished Aug 19 05:14:32 PM PDT 24
Peak memory 200784 kb
Host smart-c11a313f-3024-4ef4-ad5d-6cd3e1e25e9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956593292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.956593292
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1669280488
Short name T292
Test name
Test status
Simulation time 4308076102 ps
CPU time 120.68 seconds
Started Aug 19 05:11:49 PM PDT 24
Finished Aug 19 05:13:49 PM PDT 24
Peak memory 200716 kb
Host smart-dd4bae16-455e-4ce7-beaf-bd2add656409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669280488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1669280488
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3988394276
Short name T170
Test name
Test status
Simulation time 830050673 ps
CPU time 1.74 seconds
Started Aug 19 05:11:51 PM PDT 24
Finished Aug 19 05:11:53 PM PDT 24
Peak memory 200652 kb
Host smart-83148453-e539-441d-b6d2-94dbf23cf9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988394276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3988394276
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.635150079
Short name T90
Test name
Test status
Simulation time 94068660338 ps
CPU time 1957.74 seconds
Started Aug 19 05:11:46 PM PDT 24
Finished Aug 19 05:44:24 PM PDT 24
Peak memory 780456 kb
Host smart-69466fbf-a9dc-4ce5-b550-fa406121589b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635150079 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.635150079
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.4077373357
Short name T474
Test name
Test status
Simulation time 18608108887 ps
CPU time 78.09 seconds
Started Aug 19 05:11:50 PM PDT 24
Finished Aug 19 05:13:08 PM PDT 24
Peak memory 200768 kb
Host smart-1e5823c3-3577-49f7-8cb4-d83666a3df9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077373357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.4077373357
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3069343533
Short name T345
Test name
Test status
Simulation time 11667692 ps
CPU time 0.54 seconds
Started Aug 19 05:11:52 PM PDT 24
Finished Aug 19 05:11:52 PM PDT 24
Peak memory 195548 kb
Host smart-dae801d5-6020-4120-8f13-92ce75be627c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069343533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3069343533
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1174891841
Short name T472
Test name
Test status
Simulation time 1192900591 ps
CPU time 17.26 seconds
Started Aug 19 05:11:53 PM PDT 24
Finished Aug 19 05:12:11 PM PDT 24
Peak memory 200608 kb
Host smart-4b9e352c-1d46-4e75-88c6-530b5b4139e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1174891841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1174891841
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1875136390
Short name T149
Test name
Test status
Simulation time 754875893 ps
CPU time 39.11 seconds
Started Aug 19 05:11:48 PM PDT 24
Finished Aug 19 05:12:28 PM PDT 24
Peak memory 200552 kb
Host smart-a3c6a0d4-278f-49c3-89e7-174ef4512e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875136390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1875136390
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.828926604
Short name T273
Test name
Test status
Simulation time 2878321046 ps
CPU time 430.47 seconds
Started Aug 19 05:11:50 PM PDT 24
Finished Aug 19 05:19:01 PM PDT 24
Peak memory 475128 kb
Host smart-fe61a384-42b0-4cb2-a4f2-f8f2dcc3af45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=828926604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.828926604
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3059273094
Short name T405
Test name
Test status
Simulation time 10403870453 ps
CPU time 150.9 seconds
Started Aug 19 05:11:57 PM PDT 24
Finished Aug 19 05:14:28 PM PDT 24
Peak memory 200732 kb
Host smart-0345c574-fb4f-46e9-b104-31b1c8c22b75
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059273094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3059273094
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3378672815
Short name T335
Test name
Test status
Simulation time 3370573836 ps
CPU time 21.97 seconds
Started Aug 19 05:11:50 PM PDT 24
Finished Aug 19 05:12:12 PM PDT 24
Peak memory 200608 kb
Host smart-47c6dcb7-c7c6-4468-b56e-3a3639c63429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378672815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3378672815
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2201115388
Short name T250
Test name
Test status
Simulation time 234994662 ps
CPU time 10.86 seconds
Started Aug 19 05:11:56 PM PDT 24
Finished Aug 19 05:12:07 PM PDT 24
Peak memory 200668 kb
Host smart-a42d093e-c79a-4477-8138-49c5ea341d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201115388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2201115388
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.1477305768
Short name T221
Test name
Test status
Simulation time 17978653021 ps
CPU time 161.68 seconds
Started Aug 19 05:11:54 PM PDT 24
Finished Aug 19 05:14:36 PM PDT 24
Peak memory 217164 kb
Host smart-1860a221-0b76-41c8-8963-d0eb0ad5cc77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477305768 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.1477305768
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1603082860
Short name T459
Test name
Test status
Simulation time 2192804434 ps
CPU time 42.26 seconds
Started Aug 19 05:11:46 PM PDT 24
Finished Aug 19 05:12:29 PM PDT 24
Peak memory 200744 kb
Host smart-688f640f-6b2f-4297-b2a8-6e94d90320e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603082860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1603082860
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.10971229
Short name T259
Test name
Test status
Simulation time 31733636 ps
CPU time 0.59 seconds
Started Aug 19 05:11:46 PM PDT 24
Finished Aug 19 05:11:46 PM PDT 24
Peak memory 195720 kb
Host smart-c4d2257f-f9ab-4397-89a7-1e4dd8993fe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10971229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.10971229
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2490473016
Short name T431
Test name
Test status
Simulation time 1232447447 ps
CPU time 67.23 seconds
Started Aug 19 05:11:56 PM PDT 24
Finished Aug 19 05:13:04 PM PDT 24
Peak memory 200680 kb
Host smart-df29163c-46db-400c-be2b-811cc436689d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2490473016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2490473016
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.4103389090
Short name T262
Test name
Test status
Simulation time 2593421269 ps
CPU time 12.57 seconds
Started Aug 19 05:11:53 PM PDT 24
Finished Aug 19 05:12:05 PM PDT 24
Peak memory 200708 kb
Host smart-ccb10828-b8cc-4d94-8eff-96fed0c98a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103389090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.4103389090
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.4087669085
Short name T215
Test name
Test status
Simulation time 12670224441 ps
CPU time 575.37 seconds
Started Aug 19 05:11:52 PM PDT 24
Finished Aug 19 05:21:28 PM PDT 24
Peak memory 682164 kb
Host smart-e2ee5797-2441-4b2a-bd63-df985489bb92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4087669085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.4087669085
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.1008316346
Short name T512
Test name
Test status
Simulation time 1169486731 ps
CPU time 60.39 seconds
Started Aug 19 05:11:57 PM PDT 24
Finished Aug 19 05:12:57 PM PDT 24
Peak memory 200656 kb
Host smart-f0691510-0d8a-4e2e-bdc6-e7eb4811cc20
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008316346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.1008316346
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3868266488
Short name T95
Test name
Test status
Simulation time 9945178986 ps
CPU time 188.73 seconds
Started Aug 19 05:11:43 PM PDT 24
Finished Aug 19 05:14:52 PM PDT 24
Peak memory 200696 kb
Host smart-11f67d68-1971-4148-924b-4d8461f09a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868266488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3868266488
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.954702799
Short name T468
Test name
Test status
Simulation time 291619755 ps
CPU time 5.75 seconds
Started Aug 19 05:11:49 PM PDT 24
Finished Aug 19 05:11:55 PM PDT 24
Peak memory 200668 kb
Host smart-19f8c5e8-3a14-4369-8b40-18d62747cc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954702799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.954702799
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1920906801
Short name T203
Test name
Test status
Simulation time 50251012793 ps
CPU time 1583.61 seconds
Started Aug 19 05:11:51 PM PDT 24
Finished Aug 19 05:38:14 PM PDT 24
Peak memory 740932 kb
Host smart-d12ac7cf-8e1f-40d1-b132-1f607bf4e201
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920906801 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1920906801
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.420727504
Short name T282
Test name
Test status
Simulation time 319097142 ps
CPU time 17.46 seconds
Started Aug 19 05:11:50 PM PDT 24
Finished Aug 19 05:12:08 PM PDT 24
Peak memory 200704 kb
Host smart-1fc41fec-259d-4e39-b343-cc6f79fcdac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420727504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.420727504
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3200575453
Short name T379
Test name
Test status
Simulation time 65063027 ps
CPU time 0.61 seconds
Started Aug 19 05:12:07 PM PDT 24
Finished Aug 19 05:12:07 PM PDT 24
Peak memory 195684 kb
Host smart-b6944619-1b1a-44e4-a0f4-6d7564de3f8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200575453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3200575453
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2207057519
Short name T486
Test name
Test status
Simulation time 3241645492 ps
CPU time 100.6 seconds
Started Aug 19 05:12:42 PM PDT 24
Finished Aug 19 05:14:23 PM PDT 24
Peak memory 200704 kb
Host smart-1b715ec0-8053-4532-bf68-65733c698fe7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2207057519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2207057519
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.4082858294
Short name T454
Test name
Test status
Simulation time 2833213289 ps
CPU time 10.75 seconds
Started Aug 19 05:12:00 PM PDT 24
Finished Aug 19 05:12:11 PM PDT 24
Peak memory 200712 kb
Host smart-b714aaf1-c93d-4cbe-8a2e-53f170189f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082858294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.4082858294
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1987829405
Short name T515
Test name
Test status
Simulation time 15054503014 ps
CPU time 311.02 seconds
Started Aug 19 05:12:02 PM PDT 24
Finished Aug 19 05:17:13 PM PDT 24
Peak memory 484872 kb
Host smart-5a53d3db-5637-4266-b947-0e4c6f63e05d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1987829405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1987829405
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.355312855
Short name T514
Test name
Test status
Simulation time 371824195 ps
CPU time 19.26 seconds
Started Aug 19 05:12:06 PM PDT 24
Finished Aug 19 05:12:26 PM PDT 24
Peak memory 200580 kb
Host smart-b28910cc-9593-4d83-b4d0-b3942c03644f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355312855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.355312855
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3445609993
Short name T443
Test name
Test status
Simulation time 2903133028 ps
CPU time 42.57 seconds
Started Aug 19 05:12:01 PM PDT 24
Finished Aug 19 05:12:44 PM PDT 24
Peak memory 200788 kb
Host smart-e7ce1c9d-c07a-412d-8c01-e5c9d21061bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445609993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3445609993
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1487737675
Short name T504
Test name
Test status
Simulation time 420750890 ps
CPU time 9.36 seconds
Started Aug 19 05:11:58 PM PDT 24
Finished Aug 19 05:12:08 PM PDT 24
Peak memory 200660 kb
Host smart-dee444be-5242-45dc-a81c-642cfbf76f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487737675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1487737675
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3515727753
Short name T285
Test name
Test status
Simulation time 81964415670 ps
CPU time 1507.78 seconds
Started Aug 19 05:11:59 PM PDT 24
Finished Aug 19 05:37:07 PM PDT 24
Peak memory 786704 kb
Host smart-82bba244-7e3e-4e5d-aba5-347aba2efa4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515727753 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3515727753
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.1113274639
Short name T318
Test name
Test status
Simulation time 4056942664 ps
CPU time 15.01 seconds
Started Aug 19 05:11:59 PM PDT 24
Finished Aug 19 05:12:15 PM PDT 24
Peak memory 200680 kb
Host smart-b23adabd-72e4-4f64-a93c-6aa325417e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113274639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1113274639
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2710947806
Short name T422
Test name
Test status
Simulation time 17541978 ps
CPU time 0.56 seconds
Started Aug 19 05:10:59 PM PDT 24
Finished Aug 19 05:11:00 PM PDT 24
Peak memory 195736 kb
Host smart-57cdefe0-0f0e-4422-81dc-fe21ee6f3e1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710947806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2710947806
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1241136571
Short name T26
Test name
Test status
Simulation time 1644780264 ps
CPU time 59.53 seconds
Started Aug 19 05:10:59 PM PDT 24
Finished Aug 19 05:11:59 PM PDT 24
Peak memory 200672 kb
Host smart-5ce0652c-5c8d-40c0-8fad-baeb2e7e1d11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1241136571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1241136571
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2964154809
Short name T126
Test name
Test status
Simulation time 1709943316 ps
CPU time 15.44 seconds
Started Aug 19 05:10:59 PM PDT 24
Finished Aug 19 05:11:14 PM PDT 24
Peak memory 200668 kb
Host smart-55340100-15c5-4955-bd32-7abaa2acd7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964154809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2964154809
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1018647668
Short name T201
Test name
Test status
Simulation time 1203113341 ps
CPU time 238.19 seconds
Started Aug 19 05:10:58 PM PDT 24
Finished Aug 19 05:14:57 PM PDT 24
Peak memory 624172 kb
Host smart-7b5ed0b0-ae98-4d43-98a7-faf516274443
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1018647668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1018647668
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2612331626
Short name T231
Test name
Test status
Simulation time 7147759972 ps
CPU time 203.77 seconds
Started Aug 19 05:11:01 PM PDT 24
Finished Aug 19 05:14:25 PM PDT 24
Peak memory 200732 kb
Host smart-ef36844b-e7bc-40d4-8038-6b3d58991b06
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612331626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2612331626
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3071012180
Short name T362
Test name
Test status
Simulation time 12968873344 ps
CPU time 165.29 seconds
Started Aug 19 05:11:02 PM PDT 24
Finished Aug 19 05:13:48 PM PDT 24
Peak memory 200756 kb
Host smart-b0c59c17-e483-4837-ae97-ad2aad2fc412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071012180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3071012180
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_smoke.3665805384
Short name T193
Test name
Test status
Simulation time 266596061 ps
CPU time 5.9 seconds
Started Aug 19 05:11:03 PM PDT 24
Finished Aug 19 05:11:09 PM PDT 24
Peak memory 200672 kb
Host smart-2e251846-d7f5-457a-9292-e932f0847bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665805384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3665805384
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.106084256
Short name T21
Test name
Test status
Simulation time 18393547919 ps
CPU time 337.63 seconds
Started Aug 19 05:11:00 PM PDT 24
Finished Aug 19 05:16:38 PM PDT 24
Peak memory 217168 kb
Host smart-03edb6d9-6c83-4c3f-8677-ef8f1f9d88f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106084256 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.106084256
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.1488758835
Short name T253
Test name
Test status
Simulation time 6171630437 ps
CPU time 66.92 seconds
Started Aug 19 05:10:57 PM PDT 24
Finished Aug 19 05:12:04 PM PDT 24
Peak memory 200760 kb
Host smart-1724ab36-e192-4421-942e-679c01702f70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1488758835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1488758835
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.1072922585
Short name T444
Test name
Test status
Simulation time 6267974803 ps
CPU time 56.5 seconds
Started Aug 19 05:11:05 PM PDT 24
Finished Aug 19 05:12:02 PM PDT 24
Peak memory 200760 kb
Host smart-c8c2a3b1-210d-41b2-a8ba-ebeaf5f0e08f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1072922585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.1072922585
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.816767690
Short name T173
Test name
Test status
Simulation time 8338356041 ps
CPU time 93.83 seconds
Started Aug 19 05:10:55 PM PDT 24
Finished Aug 19 05:12:29 PM PDT 24
Peak memory 200736 kb
Host smart-377b147d-a9db-44a8-a08a-6ab6dfffde68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=816767690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.816767690
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.352839610
Short name T400
Test name
Test status
Simulation time 109668846749 ps
CPU time 681.45 seconds
Started Aug 19 05:10:58 PM PDT 24
Finished Aug 19 05:22:20 PM PDT 24
Peak memory 200684 kb
Host smart-0fdf2579-4883-41d8-a7a1-ecc3f3beefff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=352839610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.352839610
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.2430358734
Short name T499
Test name
Test status
Simulation time 228026560815 ps
CPU time 2694.8 seconds
Started Aug 19 05:10:57 PM PDT 24
Finished Aug 19 05:55:52 PM PDT 24
Peak memory 217040 kb
Host smart-d093e406-2d31-483b-ae1f-0de6c583ebb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2430358734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.2430358734
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.3952610251
Short name T493
Test name
Test status
Simulation time 145551787033 ps
CPU time 2552.5 seconds
Started Aug 19 05:11:05 PM PDT 24
Finished Aug 19 05:53:38 PM PDT 24
Peak memory 216924 kb
Host smart-b51c8862-b80a-4b98-839b-eb54829f9d28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3952610251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.3952610251
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3585212102
Short name T357
Test name
Test status
Simulation time 8883971665 ps
CPU time 100.53 seconds
Started Aug 19 05:10:59 PM PDT 24
Finished Aug 19 05:12:39 PM PDT 24
Peak memory 200720 kb
Host smart-817dc04a-a4bd-4951-9eda-52e686f6431f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585212102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3585212102
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.892017613
Short name T353
Test name
Test status
Simulation time 26679103 ps
CPU time 0.6 seconds
Started Aug 19 05:12:02 PM PDT 24
Finished Aug 19 05:12:03 PM PDT 24
Peak memory 196728 kb
Host smart-3c3a6b6f-3c2a-4692-bda3-d7c169c36bbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892017613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.892017613
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1509655164
Short name T24
Test name
Test status
Simulation time 379555865 ps
CPU time 23.31 seconds
Started Aug 19 05:12:02 PM PDT 24
Finished Aug 19 05:12:26 PM PDT 24
Peak memory 200040 kb
Host smart-bc815e87-2897-4577-bc84-9d22e454edae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1509655164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1509655164
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3855381605
Short name T523
Test name
Test status
Simulation time 1735110739 ps
CPU time 9.12 seconds
Started Aug 19 05:11:58 PM PDT 24
Finished Aug 19 05:12:07 PM PDT 24
Peak memory 200672 kb
Host smart-d8ffa5df-1abd-40d8-9ad6-8b1e17cf5b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855381605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3855381605
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3795087600
Short name T268
Test name
Test status
Simulation time 760013704 ps
CPU time 146.52 seconds
Started Aug 19 05:12:00 PM PDT 24
Finished Aug 19 05:14:27 PM PDT 24
Peak memory 455164 kb
Host smart-bb871027-f66e-4305-b829-827d269caef5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795087600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3795087600
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1512236904
Short name T82
Test name
Test status
Simulation time 8708516459 ps
CPU time 115.13 seconds
Started Aug 19 05:12:00 PM PDT 24
Finished Aug 19 05:13:55 PM PDT 24
Peak memory 200712 kb
Host smart-58a2fab3-c04e-4d6e-8af3-1ccff093d579
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512236904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1512236904
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3562181876
Short name T301
Test name
Test status
Simulation time 569260484 ps
CPU time 32.34 seconds
Started Aug 19 05:12:07 PM PDT 24
Finished Aug 19 05:12:39 PM PDT 24
Peak memory 200736 kb
Host smart-09d81385-a12f-44c3-a2cb-dec67d2b912f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562181876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3562181876
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3292585860
Short name T295
Test name
Test status
Simulation time 733197024 ps
CPU time 10.07 seconds
Started Aug 19 05:12:00 PM PDT 24
Finished Aug 19 05:12:10 PM PDT 24
Peak memory 200668 kb
Host smart-1bddbd3f-1796-44d4-80c8-905711996221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292585860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3292585860
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.208381669
Short name T471
Test name
Test status
Simulation time 270543215043 ps
CPU time 1261.05 seconds
Started Aug 19 05:12:00 PM PDT 24
Finished Aug 19 05:33:02 PM PDT 24
Peak memory 694244 kb
Host smart-c2934a85-b966-416d-aaba-546886211c60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208381669 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.208381669
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1628224351
Short name T105
Test name
Test status
Simulation time 4385164807 ps
CPU time 56.66 seconds
Started Aug 19 05:11:58 PM PDT 24
Finished Aug 19 05:12:54 PM PDT 24
Peak memory 200720 kb
Host smart-2f518ccc-0eed-49b6-903b-5eede2a66f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628224351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1628224351
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1102990064
Short name T174
Test name
Test status
Simulation time 43976346 ps
CPU time 0.6 seconds
Started Aug 19 05:12:03 PM PDT 24
Finished Aug 19 05:12:04 PM PDT 24
Peak memory 196748 kb
Host smart-8941f247-e2e9-4904-93d6-982e293273dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102990064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1102990064
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2931051291
Short name T237
Test name
Test status
Simulation time 6931680473 ps
CPU time 55.46 seconds
Started Aug 19 05:12:00 PM PDT 24
Finished Aug 19 05:12:55 PM PDT 24
Peak memory 200764 kb
Host smart-72a587e9-5244-40bf-9868-dfd00212162c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2931051291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2931051291
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.925210903
Short name T489
Test name
Test status
Simulation time 6044007727 ps
CPU time 22.76 seconds
Started Aug 19 05:11:58 PM PDT 24
Finished Aug 19 05:12:21 PM PDT 24
Peak memory 200732 kb
Host smart-77d00703-ad93-4e98-b284-7a3d0843835b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925210903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.925210903
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1476459169
Short name T361
Test name
Test status
Simulation time 9158698879 ps
CPU time 465.79 seconds
Started Aug 19 05:12:02 PM PDT 24
Finished Aug 19 05:19:48 PM PDT 24
Peak memory 625600 kb
Host smart-340de0c8-fa2b-4144-9aea-abd7a4edf610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1476459169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1476459169
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2430257044
Short name T462
Test name
Test status
Simulation time 665378052 ps
CPU time 8.11 seconds
Started Aug 19 05:12:11 PM PDT 24
Finished Aug 19 05:12:19 PM PDT 24
Peak memory 200544 kb
Host smart-322cd318-0906-4480-8b6a-b0f2b3290b21
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430257044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2430257044
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3116352591
Short name T164
Test name
Test status
Simulation time 390425036 ps
CPU time 22.88 seconds
Started Aug 19 05:11:58 PM PDT 24
Finished Aug 19 05:12:21 PM PDT 24
Peak memory 200684 kb
Host smart-512978ab-4efe-483e-8b10-8eb810c6a1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116352591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3116352591
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1579750827
Short name T321
Test name
Test status
Simulation time 140603906 ps
CPU time 1.95 seconds
Started Aug 19 05:12:04 PM PDT 24
Finished Aug 19 05:12:06 PM PDT 24
Peak memory 200656 kb
Host smart-581e0ff6-bcf2-4857-9bf5-454b65c57541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579750827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1579750827
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1376311649
Short name T350
Test name
Test status
Simulation time 7151256296 ps
CPU time 144.46 seconds
Started Aug 19 05:11:59 PM PDT 24
Finished Aug 19 05:14:23 PM PDT 24
Peak memory 200740 kb
Host smart-923d1c98-b29f-4007-868a-d3a8f042d51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376311649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1376311649
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1525124102
Short name T426
Test name
Test status
Simulation time 47910305 ps
CPU time 0.57 seconds
Started Aug 19 05:12:02 PM PDT 24
Finished Aug 19 05:12:03 PM PDT 24
Peak memory 194752 kb
Host smart-4348c797-e3df-4845-a6a8-185abb3fbb05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525124102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1525124102
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2762371807
Short name T435
Test name
Test status
Simulation time 1220275764 ps
CPU time 20.83 seconds
Started Aug 19 05:11:59 PM PDT 24
Finished Aug 19 05:12:20 PM PDT 24
Peak memory 200716 kb
Host smart-99e17b63-e92d-4056-b968-22b4f8ae2cc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2762371807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2762371807
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3403768871
Short name T291
Test name
Test status
Simulation time 447067270 ps
CPU time 8.43 seconds
Started Aug 19 05:12:06 PM PDT 24
Finished Aug 19 05:12:14 PM PDT 24
Peak memory 200632 kb
Host smart-2d49a1a8-50a1-4b51-adc0-d774d3a80e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403768871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3403768871
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1604788436
Short name T381
Test name
Test status
Simulation time 6578083561 ps
CPU time 499.57 seconds
Started Aug 19 05:12:10 PM PDT 24
Finished Aug 19 05:20:30 PM PDT 24
Peak memory 627684 kb
Host smart-d6159c69-d301-4685-b61b-059d8ffd0904
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1604788436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1604788436
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3864003564
Short name T37
Test name
Test status
Simulation time 18478274513 ps
CPU time 117.31 seconds
Started Aug 19 05:12:03 PM PDT 24
Finished Aug 19 05:14:00 PM PDT 24
Peak memory 200756 kb
Host smart-fe7a09e9-6a5a-4945-babc-c701e8db0ae4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864003564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3864003564
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3202092000
Short name T163
Test name
Test status
Simulation time 16847360315 ps
CPU time 145.33 seconds
Started Aug 19 05:12:04 PM PDT 24
Finished Aug 19 05:14:30 PM PDT 24
Peak memory 200784 kb
Host smart-22a5f1a4-d9d5-4f3a-b31f-9ab0c04498ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202092000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3202092000
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1917873481
Short name T519
Test name
Test status
Simulation time 2014975872 ps
CPU time 9.72 seconds
Started Aug 19 05:11:58 PM PDT 24
Finished Aug 19 05:12:07 PM PDT 24
Peak memory 200628 kb
Host smart-89de0d20-d99b-4dcc-b6fe-22c76f09ff73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917873481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1917873481
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1382877986
Short name T167
Test name
Test status
Simulation time 194339731 ps
CPU time 2.12 seconds
Started Aug 19 05:12:05 PM PDT 24
Finished Aug 19 05:12:07 PM PDT 24
Peak memory 200656 kb
Host smart-3290348e-003f-4138-b67c-147c976fe17b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382877986 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1382877986
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2397151143
Short name T306
Test name
Test status
Simulation time 924605651 ps
CPU time 52.99 seconds
Started Aug 19 05:12:02 PM PDT 24
Finished Aug 19 05:12:55 PM PDT 24
Peak memory 200648 kb
Host smart-5d6cc87e-26e5-4874-a42d-0941c57b133a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397151143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2397151143
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.371729028
Short name T236
Test name
Test status
Simulation time 26949498 ps
CPU time 0.61 seconds
Started Aug 19 05:12:06 PM PDT 24
Finished Aug 19 05:12:06 PM PDT 24
Peak memory 196504 kb
Host smart-ed8502c5-4e71-47fd-8b5f-72063feb0a16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371729028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.371729028
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3347241817
Short name T485
Test name
Test status
Simulation time 1665638427 ps
CPU time 24.52 seconds
Started Aug 19 05:12:04 PM PDT 24
Finished Aug 19 05:12:29 PM PDT 24
Peak memory 200652 kb
Host smart-7cb7fe9e-2628-40ef-858d-66b6d44543e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3347241817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3347241817
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3010907227
Short name T364
Test name
Test status
Simulation time 1113041446 ps
CPU time 30.31 seconds
Started Aug 19 05:12:06 PM PDT 24
Finished Aug 19 05:12:36 PM PDT 24
Peak memory 200400 kb
Host smart-b648318b-e3e9-4d5c-bf08-ecc18b0bc42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010907227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3010907227
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2901429093
Short name T294
Test name
Test status
Simulation time 13392607741 ps
CPU time 589.01 seconds
Started Aug 19 05:11:59 PM PDT 24
Finished Aug 19 05:21:48 PM PDT 24
Peak memory 699148 kb
Host smart-9a1a9d51-cfe3-4d6c-a5d3-40a5af9636d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2901429093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2901429093
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.27515335
Short name T327
Test name
Test status
Simulation time 4994183261 ps
CPU time 152.75 seconds
Started Aug 19 05:12:00 PM PDT 24
Finished Aug 19 05:14:33 PM PDT 24
Peak memory 200732 kb
Host smart-45c905c9-3115-405c-a7c6-21bd622f365a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27515335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.27515335
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1741080001
Short name T437
Test name
Test status
Simulation time 25413035530 ps
CPU time 183.68 seconds
Started Aug 19 05:12:03 PM PDT 24
Finished Aug 19 05:15:07 PM PDT 24
Peak memory 200728 kb
Host smart-72277d5f-1aa7-4c78-bc17-cf40646e0f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741080001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1741080001
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2281965188
Short name T227
Test name
Test status
Simulation time 2116824512 ps
CPU time 9.58 seconds
Started Aug 19 05:11:58 PM PDT 24
Finished Aug 19 05:12:08 PM PDT 24
Peak memory 200736 kb
Host smart-b1e6738d-94f7-42dd-80e6-0604b90d05af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281965188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2281965188
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1650788300
Short name T141
Test name
Test status
Simulation time 10532522516 ps
CPU time 1046.93 seconds
Started Aug 19 05:12:03 PM PDT 24
Finished Aug 19 05:29:30 PM PDT 24
Peak memory 670412 kb
Host smart-5976ed98-3ef9-4a8e-b39a-128018cd75ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650788300 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1650788300
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2984207834
Short name T325
Test name
Test status
Simulation time 11228466812 ps
CPU time 118.26 seconds
Started Aug 19 05:12:00 PM PDT 24
Finished Aug 19 05:13:59 PM PDT 24
Peak memory 200776 kb
Host smart-c95ea7c8-684e-4967-bf0b-998fcce5db41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984207834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2984207834
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2271396007
Short name T442
Test name
Test status
Simulation time 34608082 ps
CPU time 0.56 seconds
Started Aug 19 05:12:06 PM PDT 24
Finished Aug 19 05:12:06 PM PDT 24
Peak memory 196308 kb
Host smart-f8082a7c-7a43-4be1-8843-a65f1c324007
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271396007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2271396007
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.1843447019
Short name T272
Test name
Test status
Simulation time 293767380 ps
CPU time 16.8 seconds
Started Aug 19 05:12:03 PM PDT 24
Finished Aug 19 05:12:20 PM PDT 24
Peak memory 200528 kb
Host smart-de1dec92-4cc3-4863-afa2-fc6e6acc3e94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1843447019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1843447019
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3331520577
Short name T240
Test name
Test status
Simulation time 22837195475 ps
CPU time 67.53 seconds
Started Aug 19 05:12:07 PM PDT 24
Finished Aug 19 05:13:15 PM PDT 24
Peak memory 200752 kb
Host smart-c0797cc7-be54-49df-9125-d6e1381414e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331520577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3331520577
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1566499433
Short name T341
Test name
Test status
Simulation time 44552828424 ps
CPU time 844.52 seconds
Started Aug 19 05:12:03 PM PDT 24
Finished Aug 19 05:26:07 PM PDT 24
Peak memory 669724 kb
Host smart-d6d0ca2b-4560-4bdc-a00a-6bbfd0011095
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1566499433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1566499433
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2723157654
Short name T313
Test name
Test status
Simulation time 2904682817 ps
CPU time 58.55 seconds
Started Aug 19 05:12:03 PM PDT 24
Finished Aug 19 05:13:02 PM PDT 24
Peak memory 200672 kb
Host smart-d9a30168-e91a-4408-91fb-b4ce20c5d1fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723157654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2723157654
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.780278920
Short name T520
Test name
Test status
Simulation time 2132803091 ps
CPU time 91.7 seconds
Started Aug 19 05:12:03 PM PDT 24
Finished Aug 19 05:13:35 PM PDT 24
Peak memory 200664 kb
Host smart-4fb4a97b-3b43-4b23-ac31-e45a569690ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780278920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.780278920
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.512336272
Short name T389
Test name
Test status
Simulation time 723513079 ps
CPU time 12.07 seconds
Started Aug 19 05:11:59 PM PDT 24
Finished Aug 19 05:12:12 PM PDT 24
Peak memory 200672 kb
Host smart-fc3f10c1-87d5-420e-9442-99c3c9dffd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512336272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.512336272
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1432512970
Short name T408
Test name
Test status
Simulation time 100796498005 ps
CPU time 158.19 seconds
Started Aug 19 05:12:10 PM PDT 24
Finished Aug 19 05:14:48 PM PDT 24
Peak memory 200720 kb
Host smart-bff708f7-1275-44d6-84d0-6dd158eaeca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432512970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1432512970
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3773916382
Short name T194
Test name
Test status
Simulation time 12470207 ps
CPU time 0.6 seconds
Started Aug 19 05:12:07 PM PDT 24
Finished Aug 19 05:12:08 PM PDT 24
Peak memory 196368 kb
Host smart-57fd8f33-41f6-4042-8a3d-e421c786819c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773916382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3773916382
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1255659449
Short name T287
Test name
Test status
Simulation time 3634018413 ps
CPU time 46.34 seconds
Started Aug 19 05:12:12 PM PDT 24
Finished Aug 19 05:12:58 PM PDT 24
Peak memory 200760 kb
Host smart-0e350607-6601-4c5b-b8b2-9cbcf9844df4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1255659449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1255659449
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.827257502
Short name T484
Test name
Test status
Simulation time 34710398739 ps
CPU time 54.47 seconds
Started Aug 19 05:12:09 PM PDT 24
Finished Aug 19 05:13:04 PM PDT 24
Peak memory 208940 kb
Host smart-1a6a80f9-9f83-4060-a9fc-572c6ec9a7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827257502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.827257502
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2953140216
Short name T218
Test name
Test status
Simulation time 303280186 ps
CPU time 40.1 seconds
Started Aug 19 05:12:06 PM PDT 24
Finished Aug 19 05:12:46 PM PDT 24
Peak memory 307044 kb
Host smart-01e9eaa3-375e-4cb9-8d40-c7df793e936c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2953140216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2953140216
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.263714
Short name T376
Test name
Test status
Simulation time 10986754276 ps
CPU time 142.66 seconds
Started Aug 19 05:12:07 PM PDT 24
Finished Aug 19 05:14:30 PM PDT 24
Peak memory 200616 kb
Host smart-fbd68e93-3e21-4449-a609-d8bee46e46d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.263714
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.58176343
Short name T351
Test name
Test status
Simulation time 1763320134 ps
CPU time 103.42 seconds
Started Aug 19 05:12:11 PM PDT 24
Finished Aug 19 05:13:55 PM PDT 24
Peak memory 200644 kb
Host smart-49def1ca-3dd7-44c9-98ea-08d70b016843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58176343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.58176343
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2560979996
Short name T293
Test name
Test status
Simulation time 1001777065 ps
CPU time 12 seconds
Started Aug 19 05:12:07 PM PDT 24
Finished Aug 19 05:12:20 PM PDT 24
Peak memory 200676 kb
Host smart-d94e190d-f340-4bb0-96b5-5166680835eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560979996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2560979996
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.922431763
Short name T156
Test name
Test status
Simulation time 106294060205 ps
CPU time 5759.19 seconds
Started Aug 19 05:12:48 PM PDT 24
Finished Aug 19 06:48:49 PM PDT 24
Peak memory 925016 kb
Host smart-8941cd3b-a9a1-4ed9-b8b4-df2e71f4da16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922431763 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.922431763
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.828351591
Short name T402
Test name
Test status
Simulation time 1402324581 ps
CPU time 67.76 seconds
Started Aug 19 05:12:07 PM PDT 24
Finished Aug 19 05:13:15 PM PDT 24
Peak memory 200612 kb
Host smart-ef6c2b2e-e488-4392-aec7-1f835cb49c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828351591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.828351591
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3492869530
Short name T490
Test name
Test status
Simulation time 12833649 ps
CPU time 0.59 seconds
Started Aug 19 05:12:07 PM PDT 24
Finished Aug 19 05:12:08 PM PDT 24
Peak memory 196736 kb
Host smart-101cc347-a9df-49f7-be3f-00772119e4e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492869530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3492869530
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3290988577
Short name T246
Test name
Test status
Simulation time 1371600150 ps
CPU time 76.69 seconds
Started Aug 19 05:12:05 PM PDT 24
Finished Aug 19 05:13:22 PM PDT 24
Peak memory 200744 kb
Host smart-ca971c12-22d6-4d0b-aab3-92612444a3f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3290988577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3290988577
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.969002217
Short name T148
Test name
Test status
Simulation time 10927790803 ps
CPU time 37.83 seconds
Started Aug 19 05:12:07 PM PDT 24
Finished Aug 19 05:12:45 PM PDT 24
Peak memory 200668 kb
Host smart-648cc58b-9999-48f8-9aa2-7402f099ff9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969002217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.969002217
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2727854438
Short name T416
Test name
Test status
Simulation time 16675151011 ps
CPU time 776.83 seconds
Started Aug 19 05:12:09 PM PDT 24
Finished Aug 19 05:25:06 PM PDT 24
Peak memory 684068 kb
Host smart-b88eb2e9-cdfe-4c8a-b7e3-ba3101c966ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2727854438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2727854438
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1710447333
Short name T245
Test name
Test status
Simulation time 652304622 ps
CPU time 37.06 seconds
Started Aug 19 05:12:08 PM PDT 24
Finished Aug 19 05:12:45 PM PDT 24
Peak memory 200700 kb
Host smart-0527b5e6-2885-40a2-813b-a0d2484f4a80
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710447333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1710447333
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3358906314
Short name T32
Test name
Test status
Simulation time 713127170 ps
CPU time 14.38 seconds
Started Aug 19 05:12:01 PM PDT 24
Finished Aug 19 05:12:16 PM PDT 24
Peak memory 200652 kb
Host smart-80af90c2-7f61-4b5d-b8f2-3978008bed99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358906314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3358906314
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1603884869
Short name T337
Test name
Test status
Simulation time 4487292271 ps
CPU time 13.6 seconds
Started Aug 19 05:12:11 PM PDT 24
Finished Aug 19 05:12:25 PM PDT 24
Peak memory 200712 kb
Host smart-71f903f4-b6c7-46dd-90e4-111057f614a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603884869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1603884869
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3247789532
Short name T85
Test name
Test status
Simulation time 44253585714 ps
CPU time 511.33 seconds
Started Aug 19 05:12:10 PM PDT 24
Finished Aug 19 05:20:41 PM PDT 24
Peak memory 657948 kb
Host smart-af7b43e1-f4b1-4e33-b0b6-fc62fad159dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247789532 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3247789532
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.550514176
Short name T184
Test name
Test status
Simulation time 1098903839 ps
CPU time 14.15 seconds
Started Aug 19 05:12:08 PM PDT 24
Finished Aug 19 05:12:23 PM PDT 24
Peak memory 200652 kb
Host smart-6425d011-c729-4632-8156-5e212892f6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550514176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.550514176
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2739899197
Short name T277
Test name
Test status
Simulation time 11983177 ps
CPU time 0.61 seconds
Started Aug 19 05:12:09 PM PDT 24
Finished Aug 19 05:12:09 PM PDT 24
Peak memory 197436 kb
Host smart-8264a071-80cf-4c99-b0fb-36af4d25eae4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739899197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2739899197
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3465154831
Short name T249
Test name
Test status
Simulation time 4070811768 ps
CPU time 60.46 seconds
Started Aug 19 05:12:07 PM PDT 24
Finished Aug 19 05:13:07 PM PDT 24
Peak memory 200744 kb
Host smart-7e36ab22-9229-4fd2-9d7f-bad2af8bacaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3465154831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3465154831
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.832878119
Short name T175
Test name
Test status
Simulation time 22462725392 ps
CPU time 25.55 seconds
Started Aug 19 05:12:08 PM PDT 24
Finished Aug 19 05:12:34 PM PDT 24
Peak memory 200736 kb
Host smart-969545f8-5ccf-40b0-98c1-ba565976c2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832878119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.832878119
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2982825915
Short name T244
Test name
Test status
Simulation time 24395626778 ps
CPU time 389.03 seconds
Started Aug 19 05:12:09 PM PDT 24
Finished Aug 19 05:18:38 PM PDT 24
Peak memory 651808 kb
Host smart-3cc9200e-3eb9-45f4-87cc-0df563c1d7be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2982825915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2982825915
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2765496580
Short name T182
Test name
Test status
Simulation time 130091947412 ps
CPU time 225.12 seconds
Started Aug 19 05:12:08 PM PDT 24
Finished Aug 19 05:15:53 PM PDT 24
Peak memory 200716 kb
Host smart-b0892cbf-1a9c-4205-8c04-5221b7853921
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765496580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2765496580
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2902047848
Short name T219
Test name
Test status
Simulation time 4639119296 ps
CPU time 72.88 seconds
Started Aug 19 05:12:08 PM PDT 24
Finished Aug 19 05:13:21 PM PDT 24
Peak memory 200720 kb
Host smart-5ba4c8d4-311a-42ca-8342-c91d343464af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902047848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2902047848
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1018883492
Short name T145
Test name
Test status
Simulation time 4634765711 ps
CPU time 14.49 seconds
Started Aug 19 05:12:07 PM PDT 24
Finished Aug 19 05:12:22 PM PDT 24
Peak memory 200624 kb
Host smart-88d3fe0e-a7ed-4882-8073-cae1ee332204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018883492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1018883492
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1752646014
Short name T87
Test name
Test status
Simulation time 235242526807 ps
CPU time 2826.77 seconds
Started Aug 19 05:12:12 PM PDT 24
Finished Aug 19 05:59:19 PM PDT 24
Peak memory 753628 kb
Host smart-cd81c4d7-edb3-4092-a3ad-4d6940ba9e4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752646014 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1752646014
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2115350000
Short name T31
Test name
Test status
Simulation time 4445018758 ps
CPU time 40.43 seconds
Started Aug 19 05:12:09 PM PDT 24
Finished Aug 19 05:12:50 PM PDT 24
Peak memory 200724 kb
Host smart-a6992cb1-16c4-4ca8-b75d-76ad3dbe3dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115350000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2115350000
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1030445339
Short name T176
Test name
Test status
Simulation time 15082686 ps
CPU time 0.61 seconds
Started Aug 19 05:12:10 PM PDT 24
Finished Aug 19 05:12:11 PM PDT 24
Peak memory 197396 kb
Host smart-cb3e0edc-5f3a-4619-87a9-69cfdc58b7eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030445339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1030445339
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.75535175
Short name T280
Test name
Test status
Simulation time 1222081907 ps
CPU time 71.34 seconds
Started Aug 19 05:12:09 PM PDT 24
Finished Aug 19 05:13:20 PM PDT 24
Peak memory 200696 kb
Host smart-c706afe4-0974-41e6-9314-f1df01bdc86c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=75535175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.75535175
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3624003631
Short name T502
Test name
Test status
Simulation time 9545164293 ps
CPU time 56.06 seconds
Started Aug 19 05:12:08 PM PDT 24
Finished Aug 19 05:13:04 PM PDT 24
Peak memory 200712 kb
Host smart-3699370f-1ed1-4365-b933-aa8db9ec05a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624003631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3624003631
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1565882830
Short name T524
Test name
Test status
Simulation time 4186602211 ps
CPU time 788.77 seconds
Started Aug 19 05:12:09 PM PDT 24
Finished Aug 19 05:25:17 PM PDT 24
Peak memory 675424 kb
Host smart-0e752e9f-9d7e-4de2-9dd1-cfcc524220bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1565882830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1565882830
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3995622814
Short name T470
Test name
Test status
Simulation time 241858321 ps
CPU time 14.18 seconds
Started Aug 19 05:12:09 PM PDT 24
Finished Aug 19 05:12:23 PM PDT 24
Peak memory 200504 kb
Host smart-7200ed3b-e60c-4dc7-97d8-9dac37f5b4de
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995622814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3995622814
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3794023924
Short name T188
Test name
Test status
Simulation time 7960511229 ps
CPU time 27.18 seconds
Started Aug 19 05:12:08 PM PDT 24
Finished Aug 19 05:12:36 PM PDT 24
Peak memory 200720 kb
Host smart-d50ca9cb-79e4-4b7f-a098-a44c970b5b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794023924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3794023924
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3499301384
Short name T57
Test name
Test status
Simulation time 943220080 ps
CPU time 11.44 seconds
Started Aug 19 05:12:09 PM PDT 24
Finished Aug 19 05:12:21 PM PDT 24
Peak memory 200676 kb
Host smart-f674dc91-943d-4e1f-b32a-860edbab9c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499301384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3499301384
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.4079478306
Short name T84
Test name
Test status
Simulation time 43574294084 ps
CPU time 587.61 seconds
Started Aug 19 05:12:11 PM PDT 24
Finished Aug 19 05:21:58 PM PDT 24
Peak memory 328068 kb
Host smart-c61b96a6-29e4-44e7-b536-4eaeef2a747a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079478306 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.4079478306
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.4142171870
Short name T336
Test name
Test status
Simulation time 4265482341 ps
CPU time 81.91 seconds
Started Aug 19 05:12:12 PM PDT 24
Finished Aug 19 05:13:34 PM PDT 24
Peak memory 200716 kb
Host smart-5e966ec5-096b-472b-a0d9-9793463accc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142171870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.4142171870
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3898919146
Short name T473
Test name
Test status
Simulation time 13047884 ps
CPU time 0.57 seconds
Started Aug 19 05:12:20 PM PDT 24
Finished Aug 19 05:12:21 PM PDT 24
Peak memory 195672 kb
Host smart-f38966c7-0596-4d9a-92ab-d153b8bb9791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898919146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3898919146
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.3867261918
Short name T171
Test name
Test status
Simulation time 91261799 ps
CPU time 4.32 seconds
Started Aug 19 05:12:22 PM PDT 24
Finished Aug 19 05:12:26 PM PDT 24
Peak memory 200568 kb
Host smart-b90f7186-269f-452d-855a-2e26471f5897
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3867261918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3867261918
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1253453965
Short name T496
Test name
Test status
Simulation time 12813341631 ps
CPU time 25.24 seconds
Started Aug 19 05:12:21 PM PDT 24
Finished Aug 19 05:12:46 PM PDT 24
Peak memory 200716 kb
Host smart-d4828387-896e-40ef-9995-4880e1d17904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253453965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1253453965
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2521816771
Short name T372
Test name
Test status
Simulation time 3168578227 ps
CPU time 314.64 seconds
Started Aug 19 05:12:21 PM PDT 24
Finished Aug 19 05:17:36 PM PDT 24
Peak memory 667668 kb
Host smart-a58b3e28-0077-4319-adf8-9c6dd1fbe8e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2521816771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2521816771
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3791879097
Short name T329
Test name
Test status
Simulation time 7655844984 ps
CPU time 131.63 seconds
Started Aug 19 05:12:20 PM PDT 24
Finished Aug 19 05:14:32 PM PDT 24
Peak memory 200780 kb
Host smart-b8be73b8-86dd-4c16-bb48-ff0be1a1eea7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791879097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3791879097
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3366154560
Short name T81
Test name
Test status
Simulation time 61618774815 ps
CPU time 231.45 seconds
Started Aug 19 05:12:20 PM PDT 24
Finished Aug 19 05:16:11 PM PDT 24
Peak memory 200736 kb
Host smart-1582c1e0-05c9-4b35-a349-e07cf7508e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366154560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3366154560
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2006565109
Short name T323
Test name
Test status
Simulation time 74637036 ps
CPU time 1.56 seconds
Started Aug 19 05:12:13 PM PDT 24
Finished Aug 19 05:12:14 PM PDT 24
Peak memory 200680 kb
Host smart-d6469a82-e850-43e4-acac-f7be56d999ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006565109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2006565109
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3778003802
Short name T338
Test name
Test status
Simulation time 9323501135 ps
CPU time 139.61 seconds
Started Aug 19 05:12:22 PM PDT 24
Finished Aug 19 05:14:42 PM PDT 24
Peak memory 217104 kb
Host smart-e099c218-d6e1-4ad5-b554-a2010cec1cd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778003802 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3778003802
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1586998156
Short name T79
Test name
Test status
Simulation time 1872981037 ps
CPU time 110.49 seconds
Started Aug 19 05:12:20 PM PDT 24
Finished Aug 19 05:14:10 PM PDT 24
Peak memory 200656 kb
Host smart-60b39eaf-993a-4e53-9a3a-eb61d141a166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586998156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1586998156
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3503689896
Short name T51
Test name
Test status
Simulation time 16728627 ps
CPU time 0.63 seconds
Started Aug 19 05:11:04 PM PDT 24
Finished Aug 19 05:11:05 PM PDT 24
Peak memory 197440 kb
Host smart-eab0c322-b27b-43cb-aee9-d69f17387c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503689896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3503689896
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.20513281
Short name T424
Test name
Test status
Simulation time 5149103898 ps
CPU time 78.88 seconds
Started Aug 19 05:11:04 PM PDT 24
Finished Aug 19 05:12:23 PM PDT 24
Peak memory 200720 kb
Host smart-3f67cf4d-f05d-4e73-afbd-cb7714984834
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20513281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.20513281
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1617782669
Short name T165
Test name
Test status
Simulation time 1759974332 ps
CPU time 25.04 seconds
Started Aug 19 05:11:00 PM PDT 24
Finished Aug 19 05:11:25 PM PDT 24
Peak memory 200760 kb
Host smart-6aa69eb0-dd93-4a5f-9b6f-64c417396ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617782669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1617782669
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.660319687
Short name T226
Test name
Test status
Simulation time 3003363415 ps
CPU time 33.3 seconds
Started Aug 19 05:10:58 PM PDT 24
Finished Aug 19 05:11:32 PM PDT 24
Peak memory 296408 kb
Host smart-f80c525d-6088-4663-8c9b-3d61331799b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=660319687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.660319687
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.824690650
Short name T414
Test name
Test status
Simulation time 36753309498 ps
CPU time 172.67 seconds
Started Aug 19 05:11:05 PM PDT 24
Finished Aug 19 05:13:58 PM PDT 24
Peak memory 200748 kb
Host smart-07170e80-ffe6-42a4-8ff1-3e3365df9fc9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824690650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.824690650
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.206974927
Short name T385
Test name
Test status
Simulation time 8426401618 ps
CPU time 143.64 seconds
Started Aug 19 05:10:59 PM PDT 24
Finished Aug 19 05:13:23 PM PDT 24
Peak memory 200772 kb
Host smart-cc8b0115-09be-435d-b766-866e08aea862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206974927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.206974927
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2045607938
Short name T438
Test name
Test status
Simulation time 1724058112 ps
CPU time 15.41 seconds
Started Aug 19 05:10:58 PM PDT 24
Finished Aug 19 05:11:13 PM PDT 24
Peak memory 200732 kb
Host smart-b5958f9a-ec28-4ae0-b9db-ffac13ea8b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045607938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2045607938
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.956233137
Short name T429
Test name
Test status
Simulation time 47885235385 ps
CPU time 1815.69 seconds
Started Aug 19 05:11:03 PM PDT 24
Finished Aug 19 05:41:19 PM PDT 24
Peak memory 761352 kb
Host smart-d0a4e626-cecf-422b-8924-d3b8ee739c0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956233137 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.956233137
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2149885670
Short name T210
Test name
Test status
Simulation time 36229101736 ps
CPU time 141.81 seconds
Started Aug 19 05:11:04 PM PDT 24
Finished Aug 19 05:13:26 PM PDT 24
Peak memory 200744 kb
Host smart-35cb21e3-662b-4bfb-96c9-b25dbc655876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149885670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2149885670
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1899200597
Short name T44
Test name
Test status
Simulation time 14280766 ps
CPU time 0.63 seconds
Started Aug 19 05:11:19 PM PDT 24
Finished Aug 19 05:11:20 PM PDT 24
Peak memory 196756 kb
Host smart-ea288f0d-203a-490d-9061-d1c1c9dda571
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899200597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1899200597
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.547181017
Short name T77
Test name
Test status
Simulation time 5724905245 ps
CPU time 83.31 seconds
Started Aug 19 05:11:00 PM PDT 24
Finished Aug 19 05:12:24 PM PDT 24
Peak memory 200720 kb
Host smart-37162aab-352c-4332-be83-705748e43823
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=547181017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.547181017
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3837095076
Short name T17
Test name
Test status
Simulation time 718456426 ps
CPU time 11.14 seconds
Started Aug 19 05:11:02 PM PDT 24
Finished Aug 19 05:11:13 PM PDT 24
Peak memory 200648 kb
Host smart-eb4f7c67-ceb7-4e84-946d-70c00fb4a254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837095076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3837095076
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3572157692
Short name T488
Test name
Test status
Simulation time 2598141516 ps
CPU time 584.02 seconds
Started Aug 19 05:11:03 PM PDT 24
Finished Aug 19 05:20:47 PM PDT 24
Peak memory 706024 kb
Host smart-e3e7f98a-b61e-45b9-b1ed-5d3dd2c80b95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3572157692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3572157692
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1336357219
Short name T279
Test name
Test status
Simulation time 969098016 ps
CPU time 57.01 seconds
Started Aug 19 05:11:01 PM PDT 24
Finished Aug 19 05:11:58 PM PDT 24
Peak memory 200552 kb
Host smart-a218a9af-f7d9-47fd-a556-261085f011b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336357219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1336357219
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3011433330
Short name T269
Test name
Test status
Simulation time 64053507591 ps
CPU time 245.63 seconds
Started Aug 19 05:11:11 PM PDT 24
Finished Aug 19 05:15:17 PM PDT 24
Peak memory 200684 kb
Host smart-c4cd8997-3abc-444d-822d-fa55377b4877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011433330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3011433330
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2246450405
Short name T296
Test name
Test status
Simulation time 114425229 ps
CPU time 1.99 seconds
Started Aug 19 05:10:59 PM PDT 24
Finished Aug 19 05:11:01 PM PDT 24
Peak memory 200580 kb
Host smart-21853b86-d0e8-4c8d-a3bf-178da346c45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246450405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2246450405
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2860302855
Short name T60
Test name
Test status
Simulation time 28861419209 ps
CPU time 576.41 seconds
Started Aug 19 05:11:06 PM PDT 24
Finished Aug 19 05:20:43 PM PDT 24
Peak memory 250008 kb
Host smart-f0655d49-b274-4e3f-9c13-a53ffca4c8b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860302855 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2860302855
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.4133794591
Short name T27
Test name
Test status
Simulation time 5065535998 ps
CPU time 233.2 seconds
Started Aug 19 05:11:06 PM PDT 24
Finished Aug 19 05:15:00 PM PDT 24
Peak memory 495348 kb
Host smart-9006e736-610d-4c78-9ed3-7161153de021
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4133794591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.4133794591
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2214877098
Short name T476
Test name
Test status
Simulation time 8750872477 ps
CPU time 106.56 seconds
Started Aug 19 05:11:05 PM PDT 24
Finished Aug 19 05:12:51 PM PDT 24
Peak memory 200776 kb
Host smart-5d449827-6a65-4d9a-b31f-b245dd07cbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214877098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2214877098
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.477518894
Short name T257
Test name
Test status
Simulation time 21999981 ps
CPU time 0.64 seconds
Started Aug 19 05:11:04 PM PDT 24
Finished Aug 19 05:11:04 PM PDT 24
Peak memory 197424 kb
Host smart-b5f76b6c-4930-4e78-8a6e-50dbaa7c6010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477518894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.477518894
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2916552210
Short name T342
Test name
Test status
Simulation time 2847219979 ps
CPU time 43.37 seconds
Started Aug 19 05:11:04 PM PDT 24
Finished Aug 19 05:11:48 PM PDT 24
Peak memory 200748 kb
Host smart-f7a86dd1-bca4-4b7e-88ba-806e0bc51075
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2916552210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2916552210
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.433223953
Short name T46
Test name
Test status
Simulation time 665142618 ps
CPU time 36.29 seconds
Started Aug 19 05:11:14 PM PDT 24
Finished Aug 19 05:11:51 PM PDT 24
Peak memory 200656 kb
Host smart-ca83e3cc-e6ca-4074-8d88-06dafd47d626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433223953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.433223953
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3673868493
Short name T526
Test name
Test status
Simulation time 3029370234 ps
CPU time 570.25 seconds
Started Aug 19 05:11:28 PM PDT 24
Finished Aug 19 05:20:59 PM PDT 24
Peak memory 604156 kb
Host smart-eb94c843-7907-435e-a45b-ef42204e4e7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3673868493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3673868493
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.56214294
Short name T162
Test name
Test status
Simulation time 47186236785 ps
CPU time 196.35 seconds
Started Aug 19 05:11:11 PM PDT 24
Finished Aug 19 05:14:27 PM PDT 24
Peak memory 200744 kb
Host smart-cbef37db-ec59-4192-b9ab-50dcd568e90a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56214294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.56214294
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2948701934
Short name T266
Test name
Test status
Simulation time 16168503286 ps
CPU time 80.16 seconds
Started Aug 19 05:11:05 PM PDT 24
Finished Aug 19 05:12:35 PM PDT 24
Peak memory 217136 kb
Host smart-24484dcc-923a-475e-b3ae-f0024cbe72e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948701934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2948701934
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1180617007
Short name T189
Test name
Test status
Simulation time 1305087075 ps
CPU time 13.15 seconds
Started Aug 19 05:11:17 PM PDT 24
Finished Aug 19 05:11:31 PM PDT 24
Peak memory 200720 kb
Host smart-570e75d3-6f86-448d-8fb8-3fa920a8aa61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180617007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1180617007
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2531093363
Short name T129
Test name
Test status
Simulation time 14760736502 ps
CPU time 1366.28 seconds
Started Aug 19 05:11:26 PM PDT 24
Finished Aug 19 05:34:12 PM PDT 24
Peak memory 703024 kb
Host smart-ca5f4012-f7ad-462c-b651-e663c22b11e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531093363 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2531093363
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.3814825161
Short name T8
Test name
Test status
Simulation time 9488237815 ps
CPU time 249.43 seconds
Started Aug 19 05:11:34 PM PDT 24
Finished Aug 19 05:15:43 PM PDT 24
Peak memory 434936 kb
Host smart-58069e06-1546-4540-99d1-44559a4d767a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3814825161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.3814825161
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1016480207
Short name T404
Test name
Test status
Simulation time 5304436104 ps
CPU time 118.98 seconds
Started Aug 19 05:11:25 PM PDT 24
Finished Aug 19 05:13:24 PM PDT 24
Peak memory 200672 kb
Host smart-1c43c5e6-1a70-43dc-a0e5-3e7846bf36e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016480207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1016480207
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3812688848
Short name T343
Test name
Test status
Simulation time 46472931 ps
CPU time 0.61 seconds
Started Aug 19 05:11:05 PM PDT 24
Finished Aug 19 05:11:06 PM PDT 24
Peak memory 196748 kb
Host smart-242554d1-c482-43b2-844d-49b69d8ddb1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812688848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3812688848
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1640709977
Short name T47
Test name
Test status
Simulation time 282589588 ps
CPU time 17.51 seconds
Started Aug 19 05:11:15 PM PDT 24
Finished Aug 19 05:11:32 PM PDT 24
Peak memory 200588 kb
Host smart-e11f2928-fcf6-49fc-9b70-0d2a3c05da30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1640709977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1640709977
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2283330903
Short name T377
Test name
Test status
Simulation time 299360926 ps
CPU time 16.01 seconds
Started Aug 19 05:11:11 PM PDT 24
Finished Aug 19 05:11:27 PM PDT 24
Peak memory 200624 kb
Host smart-c87830a1-b7cc-433d-a86e-db19632061ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283330903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2283330903
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1004260673
Short name T211
Test name
Test status
Simulation time 11592934018 ps
CPU time 1187.88 seconds
Started Aug 19 05:11:05 PM PDT 24
Finished Aug 19 05:30:53 PM PDT 24
Peak memory 712188 kb
Host smart-907a09dc-05d5-480d-aed0-b9ccc0fe7c25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004260673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1004260673
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1320609440
Short name T220
Test name
Test status
Simulation time 827145087 ps
CPU time 47.93 seconds
Started Aug 19 05:11:05 PM PDT 24
Finished Aug 19 05:11:53 PM PDT 24
Peak memory 200612 kb
Host smart-a1a94dc1-faf6-4df5-ae29-31756441973e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320609440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1320609440
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2471130793
Short name T363
Test name
Test status
Simulation time 11866009940 ps
CPU time 137.41 seconds
Started Aug 19 05:11:25 PM PDT 24
Finished Aug 19 05:13:43 PM PDT 24
Peak memory 200616 kb
Host smart-bc858b44-0940-4f24-a3c9-696637599f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471130793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2471130793
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1764551957
Short name T16
Test name
Test status
Simulation time 243269351 ps
CPU time 4.39 seconds
Started Aug 19 05:11:18 PM PDT 24
Finished Aug 19 05:11:22 PM PDT 24
Peak memory 200668 kb
Host smart-9c1ecf95-5533-4b8f-8543-157214f687bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764551957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1764551957
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3603863293
Short name T88
Test name
Test status
Simulation time 131399173829 ps
CPU time 2397.02 seconds
Started Aug 19 05:11:15 PM PDT 24
Finished Aug 19 05:51:12 PM PDT 24
Peak memory 740372 kb
Host smart-4db864d0-8219-4de6-8e6f-04b1ddeeebda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603863293 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3603863293
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.903788886
Short name T73
Test name
Test status
Simulation time 5421090509 ps
CPU time 224.36 seconds
Started Aug 19 05:11:17 PM PDT 24
Finished Aug 19 05:15:02 PM PDT 24
Peak memory 551512 kb
Host smart-987c348c-02a6-41e0-a40f-35537daaf100
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=903788886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.903788886
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1772041463
Short name T49
Test name
Test status
Simulation time 397822118 ps
CPU time 7.23 seconds
Started Aug 19 05:11:07 PM PDT 24
Finished Aug 19 05:11:15 PM PDT 24
Peak memory 200548 kb
Host smart-13df9492-c71f-4bc1-9731-898c15d2b0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772041463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1772041463
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2614876401
Short name T247
Test name
Test status
Simulation time 15116999 ps
CPU time 0.58 seconds
Started Aug 19 05:11:08 PM PDT 24
Finished Aug 19 05:11:09 PM PDT 24
Peak memory 196764 kb
Host smart-bc3848ea-97ce-409f-b30a-be8a67504116
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614876401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2614876401
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3923751407
Short name T332
Test name
Test status
Simulation time 2053326765 ps
CPU time 30.24 seconds
Started Aug 19 05:11:03 PM PDT 24
Finished Aug 19 05:11:33 PM PDT 24
Peak memory 200612 kb
Host smart-9113cd40-482b-40a7-9ce5-595e267bc4b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3923751407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3923751407
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3329653805
Short name T511
Test name
Test status
Simulation time 7303558082 ps
CPU time 41.77 seconds
Started Aug 19 05:11:20 PM PDT 24
Finished Aug 19 05:12:02 PM PDT 24
Peak memory 216984 kb
Host smart-5c68a623-6d09-4fad-a063-070a058af57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329653805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3329653805
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2369344502
Short name T258
Test name
Test status
Simulation time 41427495451 ps
CPU time 382.32 seconds
Started Aug 19 05:11:16 PM PDT 24
Finished Aug 19 05:17:38 PM PDT 24
Peak memory 436172 kb
Host smart-12b87a87-2ea9-490b-b2f1-b814efc496fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2369344502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2369344502
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1139502495
Short name T382
Test name
Test status
Simulation time 4172169160 ps
CPU time 85.2 seconds
Started Aug 19 05:11:28 PM PDT 24
Finished Aug 19 05:12:53 PM PDT 24
Peak memory 200640 kb
Host smart-05748e45-27bd-40ee-97a3-3ad2d3461162
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139502495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1139502495
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3217102266
Short name T208
Test name
Test status
Simulation time 55242478252 ps
CPU time 88.38 seconds
Started Aug 19 05:11:13 PM PDT 24
Finished Aug 19 05:12:42 PM PDT 24
Peak memory 200804 kb
Host smart-25b0115e-50ff-497a-929e-77861cef8f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217102266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3217102266
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2473718606
Short name T479
Test name
Test status
Simulation time 159820806 ps
CPU time 2.22 seconds
Started Aug 19 05:11:04 PM PDT 24
Finished Aug 19 05:11:06 PM PDT 24
Peak memory 200656 kb
Host smart-0886caa8-6df5-4b56-a3f0-35fd740ff8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473718606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2473718606
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.4214518159
Short name T466
Test name
Test status
Simulation time 406801637958 ps
CPU time 1634.85 seconds
Started Aug 19 05:11:06 PM PDT 24
Finished Aug 19 05:38:21 PM PDT 24
Peak memory 681892 kb
Host smart-ac78516c-950d-4c2a-aad3-8d402db17e18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214518159 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.4214518159
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.119991767
Short name T224
Test name
Test status
Simulation time 2976338467 ps
CPU time 139.25 seconds
Started Aug 19 05:11:10 PM PDT 24
Finished Aug 19 05:13:30 PM PDT 24
Peak memory 200692 kb
Host smart-21599717-f958-45bc-b5bd-917010662bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119991767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.119991767
Directory /workspace/9.hmac_wipe_secret/latest
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