Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38552110	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36024812

1

T1

2232

T2

4

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35724619	1			T1	1526		T2	1		T3	1
values[0x0]	18253076	1			T1	1022		T2	8		T4	2778
values[0x1]	20599227	1			T1	1112		T2	6		T4	3042

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29747037	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

44829885

1

T1

2502

T2

5

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	237213	1			T5	44		T9	64		T7	69
valid_sources[0x01]	246987	1			T5	53		T9	102		T7	83
valid_sources[0x02]	353252	1			T5	43		T9	63		T7	147
valid_sources[0x03]	238137	1			T2	2		T5	35		T9	85
valid_sources[0x04]	236143	1			T5	36		T9	85		T7	75
valid_sources[0x05]	240961	1			T5	10		T9	67		T7	132
valid_sources[0x06]	258885	1			T5	50		T9	73		T7	68
valid_sources[0x07]	237688	1			T5	68		T9	81		T7	88
valid_sources[0x08]	236099	1			T5	60		T9	100		T7	89
valid_sources[0x09]	316436	1			T5	36		T9	75		T7	206
valid_sources[0x0a]	239822	1			T5	42		T9	78		T7	159
valid_sources[0x0b]	298884	1			T5	34		T9	75		T7	46
valid_sources[0x0c]	323758	1			T5	44		T9	88		T7	28
valid_sources[0x0d]	460409	1			T5	23		T9	72		T7	63
valid_sources[0x0e]	236482	1			T5	42		T9	75		T7	95
valid_sources[0x0f]	237362	1			T5	39		T9	78		T7	71
valid_sources[0x10]	336424	1			T5	40		T9	64		T7	86
valid_sources[0x11]	238156	1			T5	66		T9	74		T7	119
valid_sources[0x12]	255634	1			T5	18		T9	98		T7	135
valid_sources[0x13]	297817	1			T5	39		T9	89		T7	129
valid_sources[0x14]	237017	1			T5	29		T24	2		T9	80
valid_sources[0x15]	424095	1			T2	1		T5	18		T9	92
valid_sources[0x16]	310329	1			T5	51		T9	101		T7	93
valid_sources[0x17]	236761	1			T5	56		T9	84		T7	93
valid_sources[0x18]	271414	1			T5	48		T9	85		T7	109
valid_sources[0x19]	240819	1			T5	24		T9	95		T7	138
valid_sources[0x1a]	356726	1			T5	48		T9	74		T7	108
valid_sources[0x1b]	272359	1			T2	1		T5	20		T9	80
valid_sources[0x1c]	276478	1			T5	43		T9	78		T7	114
valid_sources[0x1d]	240237	1			T5	57		T9	76		T7	67
valid_sources[0x1e]	268926	1			T5	71		T9	69		T7	84
valid_sources[0x1f]	238069	1			T5	49		T9	72		T7	104
valid_sources[0x20]	336088	1			T5	44		T9	94		T7	122
valid_sources[0x21]	238568	1			T5	50		T9	87		T7	111
valid_sources[0x22]	236101	1			T5	55		T9	84		T7	49
valid_sources[0x23]	282277	1			T5	58		T9	85		T7	69
valid_sources[0x24]	275402	1			T5	28		T9	86		T7	80
valid_sources[0x25]	234850	1			T5	26		T9	86		T7	125
valid_sources[0x26]	236975	1			T5	32		T9	62		T7	155
valid_sources[0x27]	339849	1			T5	34		T24	2		T9	91
valid_sources[0x28]	334943	1			T5	24		T9	85		T7	116
valid_sources[0x29]	238150	1			T5	19		T9	78		T7	75
valid_sources[0x2a]	236649	1			T5	56		T9	70		T7	79
valid_sources[0x2b]	238042	1			T5	24		T24	1		T9	79
valid_sources[0x2c]	331086	1			T5	29		T9	81		T7	84
valid_sources[0x2d]	237573	1			T5	44		T9	69		T7	116
valid_sources[0x2e]	379882	1			T5	35		T9	77		T7	49
valid_sources[0x2f]	274989	1			T5	44		T9	78		T7	80
valid_sources[0x30]	238502	1			T5	53		T9	89		T7	99
valid_sources[0x31]	237489	1			T5	42		T9	78		T7	122
valid_sources[0x32]	247197	1			T5	26		T9	81		T7	124
valid_sources[0x33]	332802	1			T5	83		T9	92		T7	138
valid_sources[0x34]	238721	1			T5	61		T9	76		T7	105
valid_sources[0x35]	238009	1			T5	44		T9	76		T7	85
valid_sources[0x36]	238063	1			T5	57		T9	82		T7	65
valid_sources[0x37]	290093	1			T5	39		T9	62		T7	84
valid_sources[0x38]	481961	1			T5	21		T9	67		T7	92
valid_sources[0x39]	236146	1			T5	41		T9	84		T7	61
valid_sources[0x3a]	238936	1			T5	32		T9	109		T7	117
valid_sources[0x3b]	236271	1			T5	18		T9	67		T7	131
valid_sources[0x3c]	445682	1			T5	52		T9	86		T7	106
valid_sources[0x3d]	237266	1			T5	31		T9	78		T7	76
valid_sources[0x3e]	236518	1			T5	57		T9	88		T7	113
valid_sources[0x3f]	238632	1			T5	51		T9	89		T7	72
valid_sources[0x40]	239332	1			T5	53		T9	91		T7	112
valid_sources[0x41]	249768	1			T5	60		T9	98		T7	108
valid_sources[0x42]	235569	1			T5	28		T9	80		T7	71
valid_sources[0x43]	660735	1			T5	31		T9	88		T7	118
valid_sources[0x44]	248121	1			T5	30		T9	96		T7	143
valid_sources[0x45]	298178	1			T5	29		T9	91		T7	72
valid_sources[0x46]	236228	1			T5	44		T9	84		T7	74
valid_sources[0x47]	263006	1			T5	37		T9	71		T7	113
valid_sources[0x48]	272200	1			T5	19		T9	75		T7	85
valid_sources[0x49]	397863	1			T5	24		T9	88		T7	76
valid_sources[0x4a]	248901	1			T5	60		T9	76		T7	100
valid_sources[0x4b]	239188	1			T5	37		T9	88		T7	121
valid_sources[0x4c]	238072	1			T2	1		T5	56		T9	98
valid_sources[0x4d]	236251	1			T5	51		T9	78		T7	93
valid_sources[0x4e]	356697	1			T5	34		T9	79		T7	46
valid_sources[0x4f]	363560	1			T5	58		T9	93		T7	117
valid_sources[0x50]	237575	1			T5	36		T9	88		T7	58
valid_sources[0x51]	235779	1			T5	28		T9	63		T7	73
valid_sources[0x52]	451006	1			T5	32		T9	80		T7	107
valid_sources[0x53]	1044132	1			T5	34		T9	89		T7	107
valid_sources[0x54]	238885	1			T5	79		T9	69		T7	109
valid_sources[0x55]	2175067	1			T5	35		T9	78		T7	70
valid_sources[0x56]	659568	1			T5	45		T9	74		T7	125
valid_sources[0x57]	238010	1			T5	20		T9	71		T7	137
valid_sources[0x58]	239634	1			T5	26		T9	59		T7	93
valid_sources[0x59]	237247	1			T5	42		T9	76		T7	96
valid_sources[0x5a]	236590	1			T5	31		T9	66		T7	70
valid_sources[0x5b]	238476	1			T5	38		T9	89		T7	37
valid_sources[0x5c]	251893	1			T5	40		T9	82		T7	82
valid_sources[0x5d]	237974	1			T5	40		T9	68		T7	34
valid_sources[0x5e]	475569	1			T5	40		T9	63		T7	85
valid_sources[0x5f]	237448	1			T5	35		T9	94		T7	61
valid_sources[0x60]	237355	1			T5	63		T9	73		T7	128
valid_sources[0x61]	235276	1			T5	57		T9	77		T7	127
valid_sources[0x62]	235310	1			T5	34		T9	75		T7	79
valid_sources[0x63]	236417	1			T5	40		T9	90		T7	82
valid_sources[0x64]	237699	1			T5	30		T9	91		T7	119
valid_sources[0x65]	238550	1			T5	20		T9	66		T7	91
valid_sources[0x66]	233182	1			T5	54		T9	99		T7	82
valid_sources[0x67]	237889	1			T5	45		T9	69		T7	153
valid_sources[0x68]	237193	1			T5	43		T9	71		T7	139
valid_sources[0x69]	236944	1			T5	25		T9	76		T7	170
valid_sources[0x6a]	287916	1			T1	3660		T5	44		T9	91
valid_sources[0x6b]	236255	1			T5	28		T9	64		T7	81
valid_sources[0x6c]	239429	1			T5	29		T9	90		T7	80
valid_sources[0x6d]	285446	1			T5	46		T9	84		T7	56
valid_sources[0x6e]	358702	1			T5	32		T9	79		T7	100
valid_sources[0x6f]	236188	1			T5	61		T9	61		T7	77
valid_sources[0x70]	236977	1			T5	32		T9	87		T7	92
valid_sources[0x71]	236110	1			T5	37		T9	75		T7	78
valid_sources[0x72]	239161	1			T5	14		T9	84		T7	138
valid_sources[0x73]	233966	1			T5	58		T9	92		T7	62
valid_sources[0x74]	235683	1			T5	37		T9	71		T7	146
valid_sources[0x75]	237926	1			T5	48		T9	85		T7	102
valid_sources[0x76]	239064	1			T5	41		T9	66		T7	97
valid_sources[0x77]	279164	1			T5	32		T9	68		T7	111
valid_sources[0x78]	300479	1			T5	24		T9	85		T7	99
valid_sources[0x79]	261078	1			T2	1		T5	49		T23	1
valid_sources[0x7a]	237019	1			T5	44		T9	90		T7	113
valid_sources[0x7b]	237184	1			T5	20		T9	94		T7	114
valid_sources[0x7c]	239116	1			T5	61		T9	84		T7	53
valid_sources[0x7d]	281204	1			T5	39		T9	94		T7	118
valid_sources[0x7e]	236702	1			T5	21		T9	79		T7	79
valid_sources[0x7f]	238148	1			T5	24		T9	74		T7	72
valid_sources[0x80]	1079435	1			T5	35		T9	70		T7	60

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17588442

1

T1

762

T3

1

T4

3109

values[0x0]

all_enables

biggest_size

9948673

1

T1

746

T2

3

T4

1788

values[0x1]

all_enables

biggest_size

8487697

1

T1

724

T2

1

T4

1615