Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

38959103

1

T1

1428

T2

11

T4

6194

full_word

36051326

1

T1

2232

T2

4

T3

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	75009969	1			T1	3660		T2	15		T3	1
auto[TlIntgErrCmd]	146	1			T72	9		T73	13		T74	10
auto[TlIntgErrData]	151	1			T72	10		T73	8		T74	7
auto[TlIntgErrBoth]	163	1			T72	11		T73	9		T74	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35863230

1

T1

1526

T2

1

T3

1

auto[1]

39147199

1

T1

2134

T2

14

T4

5820

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18263975	1			T1	764		T2	1		T4	3777
auto[TlIntgErrNone]	partial	auto[1]	20694703	1			T1	664		T2	10		T4	2417
auto[TlIntgErrNone]	full_word	auto[0]	17599073	1			T1	762		T3	1		T4	3109
auto[TlIntgErrNone]	full_word	auto[1]	18452218	1			T1	1470		T2	4		T4	3403
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T72	3		T73	2		T74	5
auto[TlIntgErrCmd]	partial	auto[1]	88	1			T72	5		T73	9		T74	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T73	1		T152	1		T156	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T72	1		T73	1		T74	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T72	3		T73	4		T74	3
auto[TlIntgErrData]	partial	auto[1]	78	1			T72	6		T73	4		T74	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T74	1		T152	1		T156	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T72	1		T152	1		T157	1
auto[TlIntgErrBoth]	partial	auto[0]	58	1			T72	3		T73	4		T74	2
auto[TlIntgErrBoth]	partial	auto[1]	93	1			T72	6		T73	5		T74	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T72	1		T152	1		T156	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T72	1		T158	2		T159	1