Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	353601795	234338	0	0
intr_enable_rd_A	353601795	2493	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	353601795	234338	0	0
T15	228693	5005	0	0
T16	54147	0	0	0
T17	0	5002	0	0
T18	0	6785	0	0
T19	0	4938	0	0
T65	257461	0	0	0
T72	0	8	0	0
T76	0	10465	0	0
T77	0	5168	0	0
T78	0	993	0	0
T79	0	184	0	0
T80	0	14	0	0
T81	1047	0	0	0
T82	688979	0	0	0
T83	54432	0	0	0
T84	106238	0	0	0
T85	7640	0	0	0
T86	1591	0	0	0
T87	22564	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	353601795	2493	0	0
T13	146216	0	0	0
T14	119824	0	0	0
T19	571648	14	0	0
T48	111782	0	0	0
T49	66580	0	0	0
T88	0	4	0	0
T89	0	48	0	0
T90	0	7	0	0
T91	0	20	0	0
T92	0	28	0	0
T93	0	13	0	0
T94	0	11	0	0
T95	0	23	0	0
T96	0	88	0	0
T97	600880	0	0	0
T98	16120	0	0	0
T99	109387	0	0	0
T100	166140	0	0	0
T101	947065	0	0	0