Line Coverage for Module :
prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T4 T5
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Line Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T1 T4 T5
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T1 T4 T5
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T1 T4 T5
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Line Coverage for Module :
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 12 | 80.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
| ALWAYS | 111 | 2 | 1 | 50.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 0/1 ==> assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 0/1 ==> storage[0] <= wdata_i;
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 0/1 ==> assign rdata_int = storage_rdata;
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Line Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 13 | 86.67 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
| ALWAYS | 111 | 2 | 1 | 50.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 0/1 ==> assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 0/1 ==> storage[0] <= wdata_i;
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Line Coverage for Module :
prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 5 | 31.25 |
| Logical | 16 | 5 | 31.25 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 24 | 20 | 83.33 |
| Logical | 24 | 20 | 83.33 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T25,T26,T27 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T28,T20,T21 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T1,T4,T5 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (36'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 24 | 8 | 33.33 |
| Logical | 24 | 8 | 33.33 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Not Covered | |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 11 | 68.75 |
| Logical | 16 | 11 | 68.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T1,T4,T5 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
9 |
9 |
100.00 |
| TERNARY |
130 |
2 |
2 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T4,T5 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T4,T5 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
435679338 |
0 |
0 |
| T1 |
65224 |
16761 |
0 |
0 |
| T2 |
9032 |
60 |
0 |
0 |
| T3 |
76624 |
16 |
0 |
0 |
| T4 |
256992 |
57643 |
0 |
0 |
| T5 |
790440 |
91606 |
0 |
0 |
| T6 |
1274808 |
132002 |
0 |
0 |
| T7 |
417816 |
127765 |
0 |
0 |
| T8 |
0 |
16891 |
0 |
0 |
| T9 |
1159720 |
91822 |
0 |
0 |
| T12 |
0 |
13220 |
0 |
0 |
| T23 |
43384 |
4 |
0 |
0 |
| T24 |
8936 |
44 |
0 |
0 |
| T29 |
0 |
118 |
0 |
0 |
| T30 |
0 |
52682 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
2147483647 |
0 |
0 |
| T1 |
81530 |
80910 |
0 |
0 |
| T2 |
11290 |
10660 |
0 |
0 |
| T3 |
95780 |
72430 |
0 |
0 |
| T4 |
321240 |
320350 |
0 |
0 |
| T5 |
988050 |
987170 |
0 |
0 |
| T6 |
1593510 |
1592880 |
0 |
0 |
| T7 |
522270 |
521570 |
0 |
0 |
| T9 |
1449650 |
1448970 |
0 |
0 |
| T23 |
54230 |
38970 |
0 |
0 |
| T24 |
11170 |
10310 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
2147483647 |
0 |
0 |
| T1 |
81530 |
80910 |
0 |
0 |
| T2 |
11290 |
10660 |
0 |
0 |
| T3 |
95780 |
72430 |
0 |
0 |
| T4 |
321240 |
320350 |
0 |
0 |
| T5 |
988050 |
987170 |
0 |
0 |
| T6 |
1593510 |
1592880 |
0 |
0 |
| T7 |
522270 |
521570 |
0 |
0 |
| T9 |
1449650 |
1448970 |
0 |
0 |
| T23 |
54230 |
38970 |
0 |
0 |
| T24 |
11170 |
10310 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
2147483647 |
0 |
0 |
| T1 |
81530 |
80910 |
0 |
0 |
| T2 |
11290 |
10660 |
0 |
0 |
| T3 |
95780 |
72430 |
0 |
0 |
| T4 |
321240 |
320350 |
0 |
0 |
| T5 |
988050 |
987170 |
0 |
0 |
| T6 |
1593510 |
1592880 |
0 |
0 |
| T7 |
522270 |
521570 |
0 |
0 |
| T9 |
1449650 |
1448970 |
0 |
0 |
| T23 |
54230 |
38970 |
0 |
0 |
| T24 |
11170 |
10310 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1381574004 |
48384736 |
0 |
0 |
| T1 |
16306 |
2121 |
0 |
0 |
| T2 |
2258 |
0 |
0 |
0 |
| T3 |
19156 |
0 |
0 |
0 |
| T4 |
64248 |
6819 |
0 |
0 |
| T5 |
197610 |
7828 |
0 |
0 |
| T6 |
318702 |
43086 |
0 |
0 |
| T7 |
104454 |
27941 |
0 |
0 |
| T8 |
0 |
9767 |
0 |
0 |
| T9 |
289930 |
9798 |
0 |
0 |
| T12 |
0 |
6668 |
0 |
0 |
| T23 |
10846 |
0 |
0 |
0 |
| T24 |
2234 |
0 |
0 |
0 |
| T29 |
0 |
56 |
0 |
0 |
| T30 |
0 |
40458 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3924 |
3924 |
0 |
0 |
| T1 |
6 |
6 |
0 |
0 |
| T2 |
6 |
6 |
0 |
0 |
| T3 |
6 |
6 |
0 |
0 |
| T4 |
6 |
6 |
0 |
0 |
| T5 |
6 |
6 |
0 |
0 |
| T6 |
6 |
6 |
0 |
0 |
| T7 |
6 |
6 |
0 |
0 |
| T9 |
6 |
6 |
0 |
0 |
| T23 |
6 |
6 |
0 |
0 |
| T24 |
6 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 13 | 92.86 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
| ALWAYS | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 0/1 ==> assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 excluded storage[0] <= wdata_i;
Exclude Annotation: VC_COV_UNR
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
VC_COV_UNR |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
6 |
85.71 |
| TERNARY |
130 |
1 |
1 |
100.00 |
| TERNARY |
138 |
1 |
1 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
1 |
50.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==> (Excluded)
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==> (Excluded)
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Covered |
T1,T2,T3 |
|
| 0 |
Excluded |
|
VC_COV_UNR |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
0 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
345328591 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
345328591 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
345328591 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 12 | 85.71 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
| ALWAYS | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 0/1 ==> assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 excluded storage[0] <= wdata_i;
Exclude Annotation: VC_COV_UNR
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 0/1 ==> assign rdata_int = storage_rdata;
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
| Total | Covered | Percent |
|---|
| Conditions | 5 | 5 | 100.00 |
| Logical | 5 | 5 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
VC_COV_UNR |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
138 |
1 |
1 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
1 |
1 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==> (Excluded)
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Covered |
T1,T2,T3 |
|
| 0 |
Excluded |
|
VC_COV_UNR |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
0 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
345328591 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
345328591 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
345328591 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_msg_fifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T4 T5
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_msg_fifo
| Total | Covered | Percent |
|---|
| Conditions | 20 | 20 | 100.00 |
| Logical | 20 | 20 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T25,T26,T27 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T28,T20,T21 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Covered | T1,T4,T5 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (36'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_msg_fifo
| Line No. | Total | Covered | Percent |
| Branches |
|
9 |
9 |
100.00 |
| TERNARY |
130 |
2 |
2 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T4,T5 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_msg_fifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
21626976 |
0 |
0 |
| T1 |
8153 |
787 |
0 |
0 |
| T2 |
1129 |
0 |
0 |
0 |
| T3 |
9578 |
0 |
0 |
0 |
| T4 |
32124 |
4899 |
0 |
0 |
| T5 |
98805 |
2726 |
0 |
0 |
| T6 |
159351 |
29128 |
0 |
0 |
| T7 |
52227 |
18580 |
0 |
0 |
| T8 |
0 |
6205 |
0 |
0 |
| T9 |
144965 |
4794 |
0 |
0 |
| T12 |
0 |
1734 |
0 |
0 |
| T23 |
5423 |
0 |
0 |
0 |
| T24 |
1117 |
0 |
0 |
0 |
| T29 |
0 |
25 |
0 |
0 |
| T30 |
0 |
34346 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
345328591 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
345328591 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
345328591 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
21626976 |
0 |
0 |
| T1 |
8153 |
787 |
0 |
0 |
| T2 |
1129 |
0 |
0 |
0 |
| T3 |
9578 |
0 |
0 |
0 |
| T4 |
32124 |
4899 |
0 |
0 |
| T5 |
98805 |
2726 |
0 |
0 |
| T6 |
159351 |
29128 |
0 |
0 |
| T7 |
52227 |
18580 |
0 |
0 |
| T8 |
0 |
6205 |
0 |
0 |
| T9 |
144965 |
4794 |
0 |
0 |
| T12 |
0 |
1734 |
0 |
0 |
| T23 |
5423 |
0 |
0 |
0 |
| T24 |
1117 |
0 |
0 |
0 |
| T29 |
0 |
25 |
0 |
0 |
| T30 |
0 |
34346 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T1 T4 T5
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T1 T4 T5
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T1 T4 T5
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
| Total | Covered | Percent |
|---|
| Conditions | 11 | 11 | 100.00 |
| Logical | 11 | 11 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Covered | T1,T4,T5 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T4,T5 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
26757760 |
0 |
0 |
| T1 |
8153 |
1334 |
0 |
0 |
| T2 |
1129 |
0 |
0 |
0 |
| T3 |
9578 |
0 |
0 |
0 |
| T4 |
32124 |
1920 |
0 |
0 |
| T5 |
98805 |
5102 |
0 |
0 |
| T6 |
159351 |
13958 |
0 |
0 |
| T7 |
52227 |
9361 |
0 |
0 |
| T8 |
0 |
3562 |
0 |
0 |
| T9 |
144965 |
5004 |
0 |
0 |
| T12 |
0 |
4934 |
0 |
0 |
| T23 |
5423 |
0 |
0 |
0 |
| T24 |
1117 |
0 |
0 |
0 |
| T29 |
0 |
31 |
0 |
0 |
| T30 |
0 |
6112 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
345328591 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
345328591 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
345328591 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345393501 |
26757760 |
0 |
0 |
| T1 |
8153 |
1334 |
0 |
0 |
| T2 |
1129 |
0 |
0 |
0 |
| T3 |
9578 |
0 |
0 |
0 |
| T4 |
32124 |
1920 |
0 |
0 |
| T5 |
98805 |
5102 |
0 |
0 |
| T6 |
159351 |
13958 |
0 |
0 |
| T7 |
52227 |
9361 |
0 |
0 |
| T8 |
0 |
3562 |
0 |
0 |
| T9 |
144965 |
5004 |
0 |
0 |
| T12 |
0 |
4934 |
0 |
0 |
| T23 |
5423 |
0 |
0 |
0 |
| T24 |
1117 |
0 |
0 |
0 |
| T29 |
0 |
31 |
0 |
0 |
| T30 |
0 |
6112 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
75889880 |
0 |
0 |
| T1 |
8153 |
3660 |
0 |
0 |
| T2 |
1129 |
15 |
0 |
0 |
| T3 |
9578 |
1 |
0 |
0 |
| T4 |
32124 |
12706 |
0 |
0 |
| T5 |
98805 |
10273 |
0 |
0 |
| T6 |
159351 |
22229 |
0 |
0 |
| T7 |
52227 |
24956 |
0 |
0 |
| T9 |
144965 |
20506 |
0 |
0 |
| T23 |
5423 |
1 |
0 |
0 |
| T24 |
1117 |
11 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
353487893 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
353487893 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
353487893 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
654 |
654 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T23 |
1 |
1 |
0 |
0 |
| T24 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
117893848 |
0 |
0 |
| T1 |
8153 |
3660 |
0 |
0 |
| T2 |
1129 |
15 |
0 |
0 |
| T3 |
9578 |
7 |
0 |
0 |
| T4 |
32124 |
12706 |
0 |
0 |
| T5 |
98805 |
31616 |
0 |
0 |
| T6 |
159351 |
22229 |
0 |
0 |
| T7 |
52227 |
24956 |
0 |
0 |
| T9 |
144965 |
20506 |
0 |
0 |
| T23 |
5423 |
1 |
0 |
0 |
| T24 |
1117 |
11 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
353487893 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
353487893 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
353487893 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
654 |
654 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T23 |
1 |
1 |
0 |
0 |
| T24 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
17512269 |
0 |
0 |
| T1 |
8153 |
1334 |
0 |
0 |
| T2 |
1129 |
0 |
0 |
0 |
| T3 |
9578 |
0 |
0 |
0 |
| T4 |
32124 |
1920 |
0 |
0 |
| T5 |
98805 |
1651 |
0 |
0 |
| T6 |
159351 |
13958 |
0 |
0 |
| T7 |
52227 |
9361 |
0 |
0 |
| T8 |
0 |
3562 |
0 |
0 |
| T9 |
144965 |
5004 |
0 |
0 |
| T12 |
0 |
1618 |
0 |
0 |
| T23 |
5423 |
0 |
0 |
0 |
| T24 |
1117 |
0 |
0 |
0 |
| T29 |
0 |
31 |
0 |
0 |
| T30 |
0 |
6112 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
353487893 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
353487893 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
353487893 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
654 |
654 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T23 |
1 |
1 |
0 |
0 |
| T24 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
27406302 |
0 |
0 |
| T1 |
8153 |
1334 |
0 |
0 |
| T2 |
1129 |
0 |
0 |
0 |
| T3 |
9578 |
0 |
0 |
0 |
| T4 |
32124 |
1920 |
0 |
0 |
| T5 |
98805 |
5102 |
0 |
0 |
| T6 |
159351 |
13958 |
0 |
0 |
| T7 |
52227 |
9361 |
0 |
0 |
| T8 |
0 |
3562 |
0 |
0 |
| T9 |
144965 |
5004 |
0 |
0 |
| T12 |
0 |
4934 |
0 |
0 |
| T23 |
5423 |
0 |
0 |
0 |
| T24 |
1117 |
0 |
0 |
0 |
| T29 |
0 |
31 |
0 |
0 |
| T30 |
0 |
6112 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
353487893 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
353487893 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
353487893 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
654 |
654 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T23 |
1 |
1 |
0 |
0 |
| T24 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
58104757 |
0 |
0 |
| T1 |
8153 |
2326 |
0 |
0 |
| T2 |
1129 |
15 |
0 |
0 |
| T3 |
9578 |
1 |
0 |
0 |
| T4 |
32124 |
10786 |
0 |
0 |
| T5 |
98805 |
8622 |
0 |
0 |
| T6 |
159351 |
8271 |
0 |
0 |
| T7 |
52227 |
15595 |
0 |
0 |
| T9 |
144965 |
15502 |
0 |
0 |
| T23 |
5423 |
1 |
0 |
0 |
| T24 |
1117 |
11 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
353487893 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
353487893 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
353487893 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
654 |
654 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T23 |
1 |
1 |
0 |
0 |
| T24 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
90487546 |
0 |
0 |
| T1 |
8153 |
2326 |
0 |
0 |
| T2 |
1129 |
15 |
0 |
0 |
| T3 |
9578 |
7 |
0 |
0 |
| T4 |
32124 |
10786 |
0 |
0 |
| T5 |
98805 |
26514 |
0 |
0 |
| T6 |
159351 |
8271 |
0 |
0 |
| T7 |
52227 |
15595 |
0 |
0 |
| T9 |
144965 |
15502 |
0 |
0 |
| T23 |
5423 |
1 |
0 |
0 |
| T24 |
1117 |
11 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
353487893 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
353487893 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
353601795 |
353487893 |
0 |
0 |
| T1 |
8153 |
8091 |
0 |
0 |
| T2 |
1129 |
1066 |
0 |
0 |
| T3 |
9578 |
7243 |
0 |
0 |
| T4 |
32124 |
32035 |
0 |
0 |
| T5 |
98805 |
98717 |
0 |
0 |
| T6 |
159351 |
159288 |
0 |
0 |
| T7 |
52227 |
52157 |
0 |
0 |
| T9 |
144965 |
144897 |
0 |
0 |
| T23 |
5423 |
3897 |
0 |
0 |
| T24 |
1117 |
1031 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
654 |
654 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T23 |
1 |
1 |
0 |
0 |
| T24 |
1 |
1 |
0 |
0 |