Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39126006	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36396539

1

T1

3327

T2

6942

T3

5349

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36225188	1			T1	3355		T2	2411		T3	6157
values[0x0]	18463438	1			T1	1442		T2	3233		T3	2789
values[0x1]	20833919	1			T1	1614		T2	3184		T3	3299

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30219988	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

45302557

1

T1

4035

T2

7454

T3

6888

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	278210	1			T1	31		T2	44		T3	59
valid_sources[0x01]	234578	1			T1	19		T2	32		T3	48
valid_sources[0x02]	263755	1			T1	23		T2	31		T3	44
valid_sources[0x03]	235677	1			T1	24		T2	33		T3	50
valid_sources[0x04]	234668	1			T1	22		T2	43		T3	61
valid_sources[0x05]	742910	1			T1	29		T2	37		T3	47
valid_sources[0x06]	236682	1			T1	30		T2	28		T3	60
valid_sources[0x07]	232607	1			T1	25		T2	26		T3	45
valid_sources[0x08]	232310	1			T1	29		T2	37		T3	33
valid_sources[0x09]	234196	1			T1	32		T2	33		T3	50
valid_sources[0x0a]	476978	1			T1	20		T2	31		T3	40
valid_sources[0x0b]	444260	1			T1	18		T2	44		T3	40
valid_sources[0x0c]	241962	1			T1	34		T2	48		T3	52
valid_sources[0x0d]	235817	1			T1	27		T2	35		T3	57
valid_sources[0x0e]	235876	1			T1	20		T2	33		T3	68
valid_sources[0x0f]	239914	1			T1	40		T2	40		T3	52
valid_sources[0x10]	235639	1			T1	27		T2	17		T3	45
valid_sources[0x11]	238987	1			T1	19		T2	30		T3	45
valid_sources[0x12]	540401	1			T1	26		T2	43		T3	50
valid_sources[0x13]	265569	1			T1	24		T2	44		T3	47
valid_sources[0x14]	235037	1			T1	28		T2	34		T3	43
valid_sources[0x15]	458410	1			T1	31		T2	29		T3	55
valid_sources[0x16]	233957	1			T1	17		T2	39		T3	60
valid_sources[0x17]	245970	1			T1	26		T2	39		T3	61
valid_sources[0x18]	235933	1			T1	19		T2	42		T3	51
valid_sources[0x19]	236401	1			T1	26		T2	41		T3	60
valid_sources[0x1a]	235411	1			T1	19		T2	35		T3	57
valid_sources[0x1b]	236052	1			T1	40		T2	30		T3	56
valid_sources[0x1c]	232510	1			T1	36		T2	37		T3	36
valid_sources[0x1d]	235329	1			T1	35		T2	35		T3	44
valid_sources[0x1e]	233137	1			T1	18		T2	42		T3	39
valid_sources[0x1f]	233560	1			T1	32		T2	31		T3	45
valid_sources[0x20]	234155	1			T1	23		T2	33		T3	50
valid_sources[0x21]	233372	1			T1	26		T2	32		T3	35
valid_sources[0x22]	236036	1			T1	23		T2	38		T3	54
valid_sources[0x23]	374244	1			T1	28		T2	37		T3	65
valid_sources[0x24]	234730	1			T1	23		T2	26		T3	46
valid_sources[0x25]	234040	1			T1	37		T2	33		T3	31
valid_sources[0x26]	234421	1			T1	24		T2	28		T3	44
valid_sources[0x27]	239454	1			T1	24		T2	39		T3	35
valid_sources[0x28]	270257	1			T1	34		T2	44		T3	33
valid_sources[0x29]	234734	1			T1	31		T2	34		T3	49
valid_sources[0x2a]	299376	1			T1	23		T2	32		T3	43
valid_sources[0x2b]	241535	1			T1	34		T2	34		T3	51
valid_sources[0x2c]	234924	1			T1	26		T2	31		T3	41
valid_sources[0x2d]	236578	1			T1	27		T2	37		T3	30
valid_sources[0x2e]	234261	1			T1	25		T2	36		T3	62
valid_sources[0x2f]	234965	1			T1	20		T2	37		T3	48
valid_sources[0x30]	235877	1			T1	30		T2	29		T3	45
valid_sources[0x31]	322758	1			T1	27		T2	27		T3	50
valid_sources[0x32]	250955	1			T1	34		T2	29		T3	49
valid_sources[0x33]	235539	1			T1	24		T2	40		T3	59
valid_sources[0x34]	281919	1			T1	28		T2	31		T3	60
valid_sources[0x35]	236080	1			T1	40		T2	28		T3	37
valid_sources[0x36]	236053	1			T1	35		T2	26		T3	47
valid_sources[0x37]	2157513	1			T1	19		T2	26		T3	48
valid_sources[0x38]	237204	1			T1	10		T2	29		T3	42
valid_sources[0x39]	235548	1			T1	26		T2	41		T3	31
valid_sources[0x3a]	235240	1			T1	19		T2	35		T3	33
valid_sources[0x3b]	235843	1			T1	30		T2	33		T3	52
valid_sources[0x3c]	316064	1			T1	35		T2	30		T3	49
valid_sources[0x3d]	274968	1			T1	26		T2	39		T3	61
valid_sources[0x3e]	235783	1			T1	13		T2	43		T3	33
valid_sources[0x3f]	234102	1			T1	35		T2	27		T3	40
valid_sources[0x40]	400014	1			T1	37		T2	27		T3	58
valid_sources[0x41]	275547	1			T1	13		T2	32		T3	59
valid_sources[0x42]	233291	1			T1	23		T2	38		T3	67
valid_sources[0x43]	234244	1			T1	25		T2	32		T3	39
valid_sources[0x44]	315534	1			T1	16		T2	40		T3	68
valid_sources[0x45]	235462	1			T1	21		T2	26		T3	56
valid_sources[0x46]	234373	1			T1	24		T2	28		T3	53
valid_sources[0x47]	234273	1			T1	36		T2	32		T3	39
valid_sources[0x48]	233056	1			T1	24		T2	39		T3	47
valid_sources[0x49]	318218	1			T1	34		T2	34		T3	50
valid_sources[0x4a]	296889	1			T1	26		T2	47		T3	41
valid_sources[0x4b]	286239	1			T1	26		T2	39		T3	38
valid_sources[0x4c]	233601	1			T1	23		T2	41		T3	45
valid_sources[0x4d]	276621	1			T1	28		T2	53		T3	50
valid_sources[0x4e]	234291	1			T1	22		T2	39		T3	48
valid_sources[0x4f]	234145	1			T1	20		T2	36		T3	57
valid_sources[0x50]	982290	1			T1	26		T2	30		T3	47
valid_sources[0x51]	233728	1			T1	23		T2	37		T3	46
valid_sources[0x52]	235598	1			T1	34		T2	28		T3	42
valid_sources[0x53]	234797	1			T1	20		T2	35		T3	49
valid_sources[0x54]	328034	1			T1	18		T2	21		T3	55
valid_sources[0x55]	236712	1			T1	16		T2	42		T3	62
valid_sources[0x56]	235373	1			T1	24		T2	23		T3	44
valid_sources[0x57]	235303	1			T1	21		T2	45		T3	49
valid_sources[0x58]	236722	1			T1	30		T2	30		T3	64
valid_sources[0x59]	235634	1			T1	34		T2	43		T3	46
valid_sources[0x5a]	351353	1			T1	28		T2	36		T3	40
valid_sources[0x5b]	234329	1			T1	30		T2	37		T3	51
valid_sources[0x5c]	234899	1			T1	38		T2	44		T3	41
valid_sources[0x5d]	234557	1			T1	25		T2	33		T3	45
valid_sources[0x5e]	234625	1			T1	17		T2	30		T3	58
valid_sources[0x5f]	233847	1			T1	23		T2	44		T3	42
valid_sources[0x60]	464269	1			T1	28		T2	41		T3	79
valid_sources[0x61]	344212	1			T1	22		T2	36		T3	57
valid_sources[0x62]	233819	1			T1	27		T2	27		T3	51
valid_sources[0x63]	244996	1			T1	25		T2	36		T3	36
valid_sources[0x64]	262384	1			T1	26		T2	46		T3	29
valid_sources[0x65]	234818	1			T1	29		T2	40		T3	54
valid_sources[0x66]	236257	1			T1	21		T2	23		T3	45
valid_sources[0x67]	235079	1			T1	26		T2	33		T3	38
valid_sources[0x68]	233417	1			T1	20		T2	32		T3	52
valid_sources[0x69]	321290	1			T1	24		T2	37		T3	46
valid_sources[0x6a]	381702	1			T1	24		T2	34		T3	47
valid_sources[0x6b]	249847	1			T1	39		T2	25		T3	56
valid_sources[0x6c]	270883	1			T1	27		T2	32		T3	54
valid_sources[0x6d]	232892	1			T1	36		T2	42		T3	47
valid_sources[0x6e]	235963	1			T1	23		T2	32		T3	36
valid_sources[0x6f]	248257	1			T1	26		T2	32		T3	58
valid_sources[0x70]	235309	1			T1	29		T2	28		T3	27
valid_sources[0x71]	233650	1			T1	28		T2	27		T3	49
valid_sources[0x72]	234661	1			T1	21		T2	36		T3	57
valid_sources[0x73]	233703	1			T1	22		T2	36		T3	48
valid_sources[0x74]	235370	1			T1	20		T2	34		T3	34
valid_sources[0x75]	234954	1			T1	26		T2	34		T3	25
valid_sources[0x76]	239213	1			T1	30		T2	25		T3	49
valid_sources[0x77]	342397	1			T1	20		T2	30		T3	34
valid_sources[0x78]	642429	1			T1	31		T2	37		T3	49
valid_sources[0x79]	233792	1			T1	31		T2	29		T3	48
valid_sources[0x7a]	236742	1			T1	29		T2	35		T3	30
valid_sources[0x7b]	236386	1			T1	30		T2	32		T3	65
valid_sources[0x7c]	236058	1			T1	22		T2	22		T3	50
valid_sources[0x7d]	235778	1			T1	28		T2	36		T3	52
valid_sources[0x7e]	234366	1			T1	22		T2	39		T3	45
valid_sources[0x7f]	325000	1			T1	19		T2	25		T3	60
valid_sources[0x80]	234601	1			T1	23		T2	42		T3	52

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17889715

1

T1

1649

T2

971

T3

3084

values[0x0]

all_enables

biggest_size

10000225

1

T1

866

T2

3035

T3

1234

values[0x1]

all_enables

biggest_size

8506599

1

T1

812

T2

2936

T3

1031