Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

39209118

1

T1

3084

T2

1886

T3

6896

full_word

36401890

1

T1

3327

T2

6942

T3

5349

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	75610578	1			T1	6411		T2	8828		T3	12245
auto[TlIntgErrCmd]	153	1			T68	9		T69	12		T70	9
auto[TlIntgErrData]	149	1			T68	9		T69	12		T70	8
auto[TlIntgErrBoth]	128	1			T68	12		T69	6		T70	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36252666

1

T1

3355

T2

2411

T3

6157

auto[1]

39358342

1

T1

3056

T2

6417

T3

6088

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18360732	1			T1	1706		T2	1440		T3	3073
auto[TlIntgErrNone]	partial	auto[1]	20847989	1			T1	1378		T2	446		T3	3823
auto[TlIntgErrNone]	full_word	auto[0]	17891768	1			T1	1649		T2	971		T3	3084
auto[TlIntgErrNone]	full_word	auto[1]	18510089	1			T1	1678		T2	5971		T3	2265
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T68	3		T69	4		T135	1
auto[TlIntgErrCmd]	partial	auto[1]	91	1			T68	5		T69	8		T70	8
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T68	1		T70	1		T139	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T140	1		T134	1		T136	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T68	4		T69	3		T70	5
auto[TlIntgErrData]	partial	auto[1]	76	1			T68	5		T69	8		T70	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T134	1		T137	1		T141	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T69	1		T140	1		T137	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T68	4		T69	2		T135	4
auto[TlIntgErrBoth]	partial	auto[1]	76	1			T68	8		T69	4		T70	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T134	1		T142	1		T143	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T134	2		T144	1		T143	1