Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	448132825	49321	0	0
intr_enable_rd_A	448132825	2179	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448132825	49321	0	0
T10	755244	6446	0	0
T11	0	9402	0	0
T12	0	4479	0	0
T15	0	4715	0	0
T25	0	11243	0	0
T59	168467	0	0	0
T61	1114	0	0	0
T63	21443	0	0	0
T65	5251	0	0	0
T68	0	10	0	0
T71	0	624	0	0
T72	0	5	0	0
T73	0	776	0	0
T74	0	13	0	0
T75	682823	0	0	0
T76	427951	0	0	0
T77	40066	0	0	0
T78	206085	0	0	0
T79	213081	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448132825	2179	0	0
T12	333912	24	0	0
T15	0	38	0	0
T27	29595	0	0	0
T80	0	55	0	0
T81	0	16	0	0
T82	0	28	0	0
T83	0	69	0	0
T84	0	12	0	0
T85	0	9	0	0
T86	0	5	0	0
T87	0	9	0	0
T88	275862	0	0	0
T89	773774	0	0	0
T90	1121	0	0	0
T91	61038	0	0	0
T92	60581	0	0	0
T93	53940	0	0	0
T94	54859	0	0	0
T95	48921	0	0	0