Line Coverage for Module :
prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T2 T4
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Line Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T1 T2 T3
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T1 T2 T3
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T1 T2 T3
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Line Coverage for Module :
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 12 | 80.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
| ALWAYS | 111 | 2 | 1 | 50.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 0/1 ==> assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 0/1 ==> storage[0] <= wdata_i;
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 0/1 ==> assign rdata_int = storage_rdata;
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Line Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 13 | 86.67 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
| ALWAYS | 111 | 2 | 1 | 50.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 0/1 ==> assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 0/1 ==> storage[0] <= wdata_i;
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Line Coverage for Module :
prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 5 | 31.25 |
| Logical | 16 | 5 | 31.25 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 24 | 20 | 83.33 |
| Logical | 24 | 20 | 83.33 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T13,T14,T29 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T1,T2,T4 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T4 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | Covered | T1,T2,T4 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (36'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 24 | 8 | 33.33 |
| Logical | 24 | 8 | 33.33 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Not Covered | |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 11 | 68.75 |
| Logical | 16 | 11 | 68.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
9 |
9 |
100.00 |
| TERNARY |
130 |
2 |
2 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T4 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
488859180 |
0 |
0 |
| T1 |
378936 |
27369 |
0 |
0 |
| T2 |
761072 |
132478 |
0 |
0 |
| T3 |
693376 |
51972 |
0 |
0 |
| T4 |
634984 |
46967 |
0 |
0 |
| T5 |
114408 |
30670 |
0 |
0 |
| T6 |
592744 |
182166 |
0 |
0 |
| T7 |
0 |
23430 |
0 |
0 |
| T16 |
28216 |
10 |
0 |
0 |
| T17 |
11816 |
130 |
0 |
0 |
| T18 |
2611688 |
322488 |
0 |
0 |
| T19 |
943608 |
192118 |
0 |
0 |
| T22 |
0 |
23875 |
0 |
0 |
| T30 |
0 |
103412 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
2147483647 |
0 |
0 |
| T1 |
473670 |
472970 |
0 |
0 |
| T2 |
951340 |
950580 |
0 |
0 |
| T3 |
866720 |
866210 |
0 |
0 |
| T4 |
793730 |
792910 |
0 |
0 |
| T5 |
143010 |
142160 |
0 |
0 |
| T6 |
740930 |
740070 |
0 |
0 |
| T16 |
35270 |
26580 |
0 |
0 |
| T17 |
14770 |
13960 |
0 |
0 |
| T18 |
3264610 |
3263760 |
0 |
0 |
| T19 |
1179510 |
1178660 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
2147483647 |
0 |
0 |
| T1 |
473670 |
472970 |
0 |
0 |
| T2 |
951340 |
950580 |
0 |
0 |
| T3 |
866720 |
866210 |
0 |
0 |
| T4 |
793730 |
792910 |
0 |
0 |
| T5 |
143010 |
142160 |
0 |
0 |
| T6 |
740930 |
740070 |
0 |
0 |
| T16 |
35270 |
26580 |
0 |
0 |
| T17 |
14770 |
13960 |
0 |
0 |
| T18 |
3264610 |
3263760 |
0 |
0 |
| T19 |
1179510 |
1178660 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
2147483647 |
0 |
0 |
| T1 |
473670 |
472970 |
0 |
0 |
| T2 |
951340 |
950580 |
0 |
0 |
| T3 |
866720 |
866210 |
0 |
0 |
| T4 |
793730 |
792910 |
0 |
0 |
| T5 |
143010 |
142160 |
0 |
0 |
| T6 |
740930 |
740070 |
0 |
0 |
| T16 |
35270 |
26580 |
0 |
0 |
| T17 |
14770 |
13960 |
0 |
0 |
| T18 |
3264610 |
3263760 |
0 |
0 |
| T19 |
1179510 |
1178660 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1787220096 |
50210313 |
0 |
0 |
| T1 |
94734 |
1725 |
0 |
0 |
| T2 |
190268 |
34548 |
0 |
0 |
| T3 |
173344 |
2992 |
0 |
0 |
| T4 |
158746 |
5159 |
0 |
0 |
| T5 |
28602 |
5386 |
0 |
0 |
| T6 |
148186 |
38094 |
0 |
0 |
| T7 |
0 |
23430 |
0 |
0 |
| T16 |
7054 |
0 |
0 |
0 |
| T17 |
2954 |
0 |
0 |
0 |
| T18 |
652922 |
31571 |
0 |
0 |
| T19 |
235902 |
40422 |
0 |
0 |
| T22 |
0 |
14585 |
0 |
0 |
| T30 |
0 |
69821 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3918 |
3918 |
0 |
0 |
| T1 |
6 |
6 |
0 |
0 |
| T2 |
6 |
6 |
0 |
0 |
| T3 |
6 |
6 |
0 |
0 |
| T4 |
6 |
6 |
0 |
0 |
| T5 |
6 |
6 |
0 |
0 |
| T6 |
6 |
6 |
0 |
0 |
| T16 |
6 |
6 |
0 |
0 |
| T17 |
6 |
6 |
0 |
0 |
| T18 |
6 |
6 |
0 |
0 |
| T19 |
6 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 13 | 92.86 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
| ALWAYS | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 0/1 ==> assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 excluded storage[0] <= wdata_i;
Exclude Annotation: VC_COV_UNR
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
VC_COV_UNR |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
6 |
85.71 |
| TERNARY |
130 |
1 |
1 |
100.00 |
| TERNARY |
138 |
1 |
1 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
1 |
50.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==> (Excluded)
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==> (Excluded)
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Covered |
T1,T2,T3 |
|
| 0 |
Excluded |
|
VC_COV_UNR |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
0 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
446739977 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
446739977 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
446739977 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 12 | 85.71 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
| ALWAYS | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 0/1 ==> assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 excluded storage[0] <= wdata_i;
Exclude Annotation: VC_COV_UNR
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 0/1 ==> assign rdata_int = storage_rdata;
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
| Total | Covered | Percent |
|---|
| Conditions | 5 | 5 | 100.00 |
| Logical | 5 | 5 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
VC_COV_UNR |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
138 |
1 |
1 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
1 |
1 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==> (Excluded)
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Covered |
T1,T2,T3 |
|
| 0 |
Excluded |
|
VC_COV_UNR |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
0 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
446739977 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
446739977 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
446739977 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_msg_fifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T2 T4
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_msg_fifo
| Total | Covered | Percent |
|---|
| Conditions | 20 | 20 | 100.00 |
| Logical | 20 | 20 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T13,T14,T29 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Covered | T1,T2,T4 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T4 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | Covered | T1,T2,T4 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (36'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_msg_fifo
| Line No. | Total | Covered | Percent |
| Branches |
|
9 |
9 |
100.00 |
| TERNARY |
130 |
2 |
2 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T4 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_msg_fifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
19548856 |
0 |
0 |
| T1 |
47367 |
688 |
0 |
0 |
| T2 |
95134 |
9758 |
0 |
0 |
| T3 |
86672 |
0 |
0 |
0 |
| T4 |
79373 |
3338 |
0 |
0 |
| T5 |
14301 |
3858 |
0 |
0 |
| T6 |
74093 |
24262 |
0 |
0 |
| T7 |
0 |
23430 |
0 |
0 |
| T16 |
3527 |
0 |
0 |
0 |
| T17 |
1477 |
0 |
0 |
0 |
| T18 |
326461 |
5478 |
0 |
0 |
| T19 |
117951 |
34364 |
0 |
0 |
| T22 |
0 |
9940 |
0 |
0 |
| T30 |
0 |
44354 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
446739977 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
446739977 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
446739977 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
19548856 |
0 |
0 |
| T1 |
47367 |
688 |
0 |
0 |
| T2 |
95134 |
9758 |
0 |
0 |
| T3 |
86672 |
0 |
0 |
0 |
| T4 |
79373 |
3338 |
0 |
0 |
| T5 |
14301 |
3858 |
0 |
0 |
| T6 |
74093 |
24262 |
0 |
0 |
| T7 |
0 |
23430 |
0 |
0 |
| T16 |
3527 |
0 |
0 |
0 |
| T17 |
1477 |
0 |
0 |
0 |
| T18 |
326461 |
5478 |
0 |
0 |
| T19 |
117951 |
34364 |
0 |
0 |
| T22 |
0 |
9940 |
0 |
0 |
| T30 |
0 |
44354 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T1 T2 T3
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T1 T2 T3
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T1 T2 T3
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
| Total | Covered | Percent |
|---|
| Conditions | 11 | 11 | 100.00 |
| Logical | 11 | 11 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
30661457 |
0 |
0 |
| T1 |
47367 |
1037 |
0 |
0 |
| T2 |
95134 |
24790 |
0 |
0 |
| T3 |
86672 |
2992 |
0 |
0 |
| T4 |
79373 |
1821 |
0 |
0 |
| T5 |
14301 |
1528 |
0 |
0 |
| T6 |
74093 |
13832 |
0 |
0 |
| T16 |
3527 |
0 |
0 |
0 |
| T17 |
1477 |
0 |
0 |
0 |
| T18 |
326461 |
26093 |
0 |
0 |
| T19 |
117951 |
6058 |
0 |
0 |
| T22 |
0 |
4645 |
0 |
0 |
| T30 |
0 |
25467 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
446739977 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
446739977 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
446739977 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
446805024 |
30661457 |
0 |
0 |
| T1 |
47367 |
1037 |
0 |
0 |
| T2 |
95134 |
24790 |
0 |
0 |
| T3 |
86672 |
2992 |
0 |
0 |
| T4 |
79373 |
1821 |
0 |
0 |
| T5 |
14301 |
1528 |
0 |
0 |
| T6 |
74093 |
13832 |
0 |
0 |
| T16 |
3527 |
0 |
0 |
0 |
| T17 |
1477 |
0 |
0 |
0 |
| T18 |
326461 |
26093 |
0 |
0 |
| T19 |
117951 |
6058 |
0 |
0 |
| T22 |
0 |
4645 |
0 |
0 |
| T30 |
0 |
25467 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
75811311 |
0 |
0 |
| T1 |
47367 |
6411 |
0 |
0 |
| T2 |
95134 |
8828 |
0 |
0 |
| T3 |
86672 |
12245 |
0 |
0 |
| T4 |
79373 |
10452 |
0 |
0 |
| T5 |
14301 |
6321 |
0 |
0 |
| T6 |
74093 |
36018 |
0 |
0 |
| T16 |
3527 |
1 |
0 |
0 |
| T17 |
1477 |
13 |
0 |
0 |
| T18 |
326461 |
35538 |
0 |
0 |
| T19 |
117951 |
37924 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
448021768 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
448021768 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
448021768 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
653 |
653 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
143535836 |
0 |
0 |
| T1 |
47367 |
6411 |
0 |
0 |
| T2 |
95134 |
40137 |
0 |
0 |
| T3 |
86672 |
12245 |
0 |
0 |
| T4 |
79373 |
10452 |
0 |
0 |
| T5 |
14301 |
6321 |
0 |
0 |
| T6 |
74093 |
36018 |
0 |
0 |
| T16 |
3527 |
4 |
0 |
0 |
| T17 |
1477 |
52 |
0 |
0 |
| T18 |
326461 |
109921 |
0 |
0 |
| T19 |
117951 |
37924 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
448021768 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
448021768 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
448021768 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
653 |
653 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
16997316 |
0 |
0 |
| T1 |
47367 |
1037 |
0 |
0 |
| T2 |
95134 |
5461 |
0 |
0 |
| T3 |
86672 |
2992 |
0 |
0 |
| T4 |
79373 |
1821 |
0 |
0 |
| T5 |
14301 |
1528 |
0 |
0 |
| T6 |
74093 |
13832 |
0 |
0 |
| T16 |
3527 |
0 |
0 |
0 |
| T17 |
1477 |
0 |
0 |
0 |
| T18 |
326461 |
8419 |
0 |
0 |
| T19 |
117951 |
6058 |
0 |
0 |
| T22 |
0 |
4645 |
0 |
0 |
| T30 |
0 |
8124 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
448021768 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
448021768 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
448021768 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
653 |
653 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
30702495 |
0 |
0 |
| T1 |
47367 |
1037 |
0 |
0 |
| T2 |
95134 |
24790 |
0 |
0 |
| T3 |
86672 |
2992 |
0 |
0 |
| T4 |
79373 |
1821 |
0 |
0 |
| T5 |
14301 |
1528 |
0 |
0 |
| T6 |
74093 |
13832 |
0 |
0 |
| T16 |
3527 |
0 |
0 |
0 |
| T17 |
1477 |
0 |
0 |
0 |
| T18 |
326461 |
26093 |
0 |
0 |
| T19 |
117951 |
6058 |
0 |
0 |
| T22 |
0 |
4645 |
0 |
0 |
| T30 |
0 |
25467 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
448021768 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
448021768 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
448021768 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
653 |
653 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
58768568 |
0 |
0 |
| T1 |
47367 |
5374 |
0 |
0 |
| T2 |
95134 |
3367 |
0 |
0 |
| T3 |
86672 |
9253 |
0 |
0 |
| T4 |
79373 |
8631 |
0 |
0 |
| T5 |
14301 |
4793 |
0 |
0 |
| T6 |
74093 |
22186 |
0 |
0 |
| T16 |
3527 |
1 |
0 |
0 |
| T17 |
1477 |
13 |
0 |
0 |
| T18 |
326461 |
27118 |
0 |
0 |
| T19 |
117951 |
31866 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
448021768 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
448021768 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
448021768 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
653 |
653 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
112833341 |
0 |
0 |
| T1 |
47367 |
5374 |
0 |
0 |
| T2 |
95134 |
15347 |
0 |
0 |
| T3 |
86672 |
9253 |
0 |
0 |
| T4 |
79373 |
8631 |
0 |
0 |
| T5 |
14301 |
4793 |
0 |
0 |
| T6 |
74093 |
22186 |
0 |
0 |
| T16 |
3527 |
4 |
0 |
0 |
| T17 |
1477 |
52 |
0 |
0 |
| T18 |
326461 |
83828 |
0 |
0 |
| T19 |
117951 |
31866 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
448021768 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
448021768 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
448132825 |
448021768 |
0 |
0 |
| T1 |
47367 |
47297 |
0 |
0 |
| T2 |
95134 |
95058 |
0 |
0 |
| T3 |
86672 |
86621 |
0 |
0 |
| T4 |
79373 |
79291 |
0 |
0 |
| T5 |
14301 |
14216 |
0 |
0 |
| T6 |
74093 |
74007 |
0 |
0 |
| T16 |
3527 |
2658 |
0 |
0 |
| T17 |
1477 |
1396 |
0 |
0 |
| T18 |
326461 |
326376 |
0 |
0 |
| T19 |
117951 |
117866 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
653 |
653 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |