Unified Coverage Report :: Module :: hmac_core

Module : hmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.68	99.41	93.90		100.00	93.41

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_hmac	98.46	100.00	96.15		100.00	97.70

---

Module Instance : tb.dut.u_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.46	100.00	96.15		100.00	97.70

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.46	100.00	96.15		100.00	97.70

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : hmac_core

	Line No.	Total	Covered	Percent
TOTAL		170	169	99.41
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
ALWAYS	132	25	25	100.00
CONT_ASSIGN	189	1	1	100.00
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
ALWAYS	208	16	15	93.75
CONT_ASSIGN	232	1	1	100.00
ALWAYS	235	5	5	100.00
CONT_ASSIGN	245	1	1	100.00
ALWAYS	253	10	10	100.00
ALWAYS	271	3	3	100.00
ALWAYS	277	6	6	100.00
ALWAYS	287	4	4	100.00
ALWAYS	295	6	6	100.00
CONT_ASSIGN	304	1	1	100.00
ALWAYS	307	3	3	100.00
ALWAYS	312	71	71	100.00
CONT_ASSIGN	458	1	1	100.00
ALWAYS	463	3	3	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
ALWAYS	485	3	3	100.00

119                     
120        1/1            assign sha_hash_start_o    = (hmac_en_i) ? hash_start    : reg_hash_start_i;
           Tests:       T1 T2 T3 
121        1/1            assign sha_hash_continue_o = (hmac_en_i) ? hash_continue : reg_hash_continue_i;
           Tests:       T1 T2 T3 
122                     
123        1/1            assign sha_hash_process_o  = (hmac_en_i) ? reg_hash_process_i | hash_process : reg_hash_process_i;
           Tests:       T1 T2 T3 
124        1/1            assign hash_done_o         = (hmac_en_i) ? hmac_hash_done                    : sha_hash_done_i;
           Tests:       T1 T2 T3 
125                     
126        1/1            assign pad_index_512 = txcount[BlockSizeBitsSHA512-1:HashWordBitsSHA256];
           Tests:       T1 T2 T3 
127        1/1            assign pad_index_256 = txcount[BlockSizeBitsSHA256-1:HashWordBitsSHA256];
           Tests:       T1 T2 T3 
128                     
129                       // adjust inner and outer padding depending on key length and block size
130                       always_comb begin : adjust_key_pad_length
131                         // set defaults
132        1/1              i_pad_256 = '{default: '0};
           Tests:       T1 T2 T3 
133        1/1              i_pad_512 = '{default: '0};
           Tests:       T1 T2 T3 
134        1/1              o_pad_256 = '{default: '0};
           Tests:       T1 T2 T3 
135        1/1              o_pad_512 = '{default: '0};
           Tests:       T1 T2 T3 
136                     
137        1/1              unique case (key_length_i)
           Tests:       T1 T2 T3 
138                           Key_128: begin
139        1/1                  i_pad_256 = {secret_key_i[1023:896],
           Tests:       T1 T2 T4 
140                                         {(BlockSizeSHA256-128){1'b0}}} ^ {(BlockSizeSHA256/8){8'h36}};
141        1/1                  i_pad_512 = {secret_key_i[1023:896],
           Tests:       T1 T2 T4 
142                                         {(BlockSizeSHA512-128){1'b0}}} ^ {(BlockSizeSHA512/8){8'h36}};
143        1/1                  o_pad_256 = {secret_key_i[1023:896],
           Tests:       T1 T2 T4 
144                                         {(BlockSizeSHA256-128){1'b0}}} ^ {(BlockSizeSHA256/8){8'h5c}};
145        1/1                  o_pad_512 = {secret_key_i[1023:896],
           Tests:       T1 T2 T4 
146                                         {(BlockSizeSHA512-128){1'b0}}} ^ {(BlockSizeSHA512/8){8'h5c}};
147                           end
148                           Key_256: begin
149        1/1                  i_pad_256 = {secret_key_i[1023:768],
           Tests:       T1 T2 T4 
150                                         {(BlockSizeSHA256-256){1'b0}}} ^ {(BlockSizeSHA256/8){8'h36}};
151        1/1                  i_pad_512 = {secret_key_i[1023:768],
           Tests:       T1 T2 T4 
152                                         {(BlockSizeSHA512-256){1'b0}}} ^ {(BlockSizeSHA512/8){8'h36}};
153        1/1                  o_pad_256 = {secret_key_i[1023:768],
           Tests:       T1 T2 T4 
154                                         {(BlockSizeSHA256-256){1'b0}}} ^ {(BlockSizeSHA256/8){8'h5c}};
155        1/1                  o_pad_512 = {secret_key_i[1023:768],
           Tests:       T1 T2 T4 
156                                         {(BlockSizeSHA512-256){1'b0}}} ^ {(BlockSizeSHA512/8){8'h5c}};
157                           end
158                           Key_384: begin
159        1/1                  i_pad_256 = {secret_key_i[1023:640],
           Tests:       T1 T2 T4 
160                                         {(BlockSizeSHA256-384){1'b0}}} ^ {(BlockSizeSHA256/8){8'h36}};
161        1/1                  i_pad_512 = {secret_key_i[1023:640],
           Tests:       T1 T2 T4 
162                                         {(BlockSizeSHA512-384){1'b0}}} ^ {(BlockSizeSHA512/8){8'h36}};
163        1/1                  o_pad_256 = {secret_key_i[1023:640],
           Tests:       T1 T2 T4 
164                                         {(BlockSizeSHA256-384){1'b0}}} ^ {(BlockSizeSHA256/8){8'h5c}};
165        1/1                  o_pad_512 = {secret_key_i[1023:640],
           Tests:       T1 T2 T4 
166                                         {(BlockSizeSHA512-384){1'b0}}} ^ {(BlockSizeSHA512/8){8'h5c}};
167                           end
168                           Key_512: begin
169        1/1                  i_pad_256 = secret_key_i[1023:512] ^ {(BlockSizeSHA256/8){8'h36}};
           Tests:       T1 T4 T6 
170        1/1                  i_pad_512 = {secret_key_i[1023:512],
           Tests:       T1 T4 T6 
171                                         {(BlockSizeSHA512-512){1'b0}}} ^ {(BlockSizeSHA512/8){8'h36}};
172        1/1                  o_pad_256 = secret_key_i[1023:512] ^ {(BlockSizeSHA256/8){8'h5c}};
           Tests:       T1 T4 T6 
173        1/1                  o_pad_512 = {secret_key_i[1023:512],
           Tests:       T1 T4 T6 
174                                         {(BlockSizeSHA512-512){1'b0}}} ^ {(BlockSizeSHA512/8){8'h5c}};
175                           end
176                           Key_1024: begin // not allowed to be configured for SHA-2 256
177                             // zero out for SHA-2 256
178        1/1                  i_pad_256 = '{default: '0};
           Tests:       T1 T2 T4 
179        1/1                  i_pad_512 = secret_key_i[1023:0]   ^ {(BlockSizeSHA512/8){8'h36}};
           Tests:       T1 T2 T4 
180                             // zero out for SHA-2 256
181        1/1                  o_pad_256 = '{default: '0};
           Tests:       T1 T2 T4 
182        1/1                  o_pad_512 = secret_key_i[1023:0]   ^ {(BlockSizeSHA512/8){8'h5c}};
           Tests:       T1 T2 T4 
183                           end
184                           default: begin
185                           end
186                         endcase
187                       end
188                     
189        1/1            assign fifo_rready_o = (hmac_en_i) ? (st_q == StMsg) & sha_rready_i : sha_rready_i ;
           Tests:       T1 T2 T3 
190                       // sha_rvalid is controlled by State Machine below.
191        1/1            assign sha_rvalid_o  = (!hmac_en_i) ? fifo_rvalid_i : hmac_sha_rvalid ;
           Tests:       T1 T2 T3 
192        1/1            assign sha_rdata_o =
           Tests:       T1 T2 T3 
193                         (!hmac_en_i)    ? fifo_rdata_i                                                             :
194                         (sel_rdata == SelIPad && digest_size_i == SHA2_256)
195                                       ? '{data: i_pad_256[(BlockSizeSHA256-1)-32*pad_index_256-:32], mask: '1} :
196                         (sel_rdata == SelIPad && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
197                                       ? '{data: i_pad_512[(BlockSizeSHA512-1)-32*pad_index_512-:32], mask: '1} :
198                         (sel_rdata == SelOPad && digest_size_i == SHA2_256)
199                                       ? '{data: o_pad_256[(BlockSizeSHA256-1)-32*pad_index_256-:32], mask: '1} :
200                         (sel_rdata == SelOPad && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
201                                       ? '{data: o_pad_512[(BlockSizeSHA512-1)-32*pad_index_512-:32], mask: '1} :
202                         (sel_rdata == SelFifo) ? fifo_rdata_i                                                    :
203                                       '{default: '0};
204                     
205                       logic [63:0] sha_msg_len;
206                     
207                       always_comb begin: assign_sha_message_length
208        1/1              sha_msg_len = '0;
           Tests:       T1 T2 T3 
209        1/1              if (!hmac_en_i) begin
           Tests:       T1 T2 T3 
210        1/1                sha_msg_len = message_length_i;
           Tests:       T1 T2 T3 
211                         // HASH = (o_pad || HASH_INTERMEDIATE (i_pad || msg))
212                         // message length for HASH_INTERMEDIATE = block size (i_pad) + message length
213        1/1              end else if (sel_msglen == SelIPadMsg) begin
           Tests:       T1 T2 T3 
214        1/1                if (digest_size_i == SHA2_256) begin
           Tests:       T1 T2 T3 
215        1/1                  sha_msg_len = message_length_i + BlockSizeSHA256in64;
           Tests:       T2 T4 T6 
216        1/1                end else if ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)) begin
           Tests:       T1 T2 T3 
217        1/1                  sha_msg_len = message_length_i + BlockSizeSHA512in64;
           Tests:       T1 T2 T3 
218                           end
                        MISSING_ELSE
219        1/1              end else if (sel_msglen == SelOPadMsg) begin
           Tests:       T1 T2 T4 
220                         // message length for HASH = block size (o_pad) + HASH_INTERMEDIATE digest length
221        1/1                if (digest_size_i == SHA2_256) begin
           Tests:       T1 T2 T4 
222        1/1                  sha_msg_len = BlockSizeSHA256in64 + 64'd256;
           Tests:       T4 T6 T19 
223        1/1                end else if (digest_size_i == SHA2_384) begin
           Tests:       T1 T2 T4 
224        1/1                  sha_msg_len = BlockSizeSHA512in64 + 64'd384;
           Tests:       T2 T4 T18 
225        1/1                end else if (digest_size_i == SHA2_512) begin
           Tests:       T1 T4 T18 
226        1/1                  sha_msg_len = BlockSizeSHA512in64 + 64'd512;
           Tests:       T1 T4 T18 
227                           end
                   ==>  MISSING_ELSE
228                         end else
229        0/1     ==>        sha_msg_len = '0;
230                       end
231                     
232        1/1            assign sha_message_length_o = sha_msg_len;
           Tests:       T1 T2 T3 
233                     
234                       always_comb begin
235        1/1              txcnt_eq_blksz = '0;
           Tests:       T1 T2 T3 
236                     
237        1/1              unique case (digest_size_i)
           Tests:       T1 T2 T3 
238        1/1                SHA2_256: txcnt_eq_blksz = (txcount[BlockSizeBitsSHA256-1:0] == '0) && (txcount != '0);
           Tests:       T1 T2 T4 
239        1/1                SHA2_384: txcnt_eq_blksz = (txcount[BlockSizeBitsSHA512-1:0] == '0) && (txcount != '0);
           Tests:       T1 T2 T4 
240        1/1                SHA2_512: txcnt_eq_blksz = (txcount[BlockSizeBitsSHA512-1:0] == '0) && (txcount != '0);
           Tests:       T1 T2 T3 
241                           default;
242                         endcase
243                       end
244                     
245        1/1            assign inc_txcount = sha_rready_i && sha_rvalid_o;
           Tests:       T1 T2 T3 
246                     
247                       // txcount
248                       //    Looks like txcount can be removed entirely here in hmac_core
249                       //    In the first round (InnerPaddedKey), it can just watch process and hash_done
250                       //    In the second round, it only needs count 256 bits for hash digest to trigger
251                       //    hash_process to SHA2
252                       always_comb begin
253        1/1              txcount_d = txcount;
           Tests:       T1 T2 T3 
254        1/1              if (clr_txcount) begin
           Tests:       T1 T2 T3 
255        1/1                txcount_d = '0;
           Tests:       T1 T2 T4 
256        1/1              end else if (load_txcount) begin
           Tests:       T1 T2 T3 
257                           // When loading, add block size to the message length because the SW-visible message length
258                           // does not include the block containing the key xor'ed with the inner pad.
259        1/1                unique case (digest_size_i)
           Tests:       T7 T8 T9 
260        1/1                  SHA2_256: txcount_d = message_length_i + BlockSizeSHA256in64;
           Tests:       T8 T9 T50 
261        1/1                  SHA2_384: txcount_d = message_length_i + BlockSizeSHA512in64;
           Tests:       T10 T50 T51 
262        1/1                  SHA2_512: txcount_d = message_length_i + BlockSizeSHA512in64;
           Tests:       T7 T9 T20 
263                             default : txcount_d = message_length_i + '0;
264                           endcase
265        1/1              end else if (inc_txcount) begin
           Tests:       T1 T2 T3 
266        1/1                txcount_d[63:5] = txcount[63:5] + 1'b1; // increment by 32 (data word size)
           Tests:       T1 T2 T4 
267                         end
                        MISSING_ELSE
268                       end
269                     
270                       always_ff @(posedge clk_i or negedge rst_ni) begin
271        2/2              if (!rst_ni) txcount <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
272        1/1              else         txcount <= txcount_d;
           Tests:       T1 T2 T3 
273                       end
274                     
275                       // reg_hash_process_i trigger logic
276                       always_ff @(posedge clk_i or negedge rst_ni) begin
277        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
278        1/1                reg_hash_process_flag <= 1'b0;
           Tests:       T1 T2 T3 
279        1/1              end else if (reg_hash_process_i) begin
           Tests:       T1 T2 T3 
280        1/1                reg_hash_process_flag <= 1'b1;
           Tests:       T1 T2 T4 
281        1/1              end else if (hmac_hash_done || reg_hash_start_i || reg_hash_continue_i) begin
           Tests:       T1 T2 T3 
282        1/1                reg_hash_process_flag <= 1'b0;
           Tests:       T1 T2 T4 
283                         end
                        MISSING_ELSE
284                       end
285                     
286                       always_ff @(posedge clk_i or negedge rst_ni) begin
287        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
288        1/1                round_q <= Inner;
           Tests:       T1 T2 T3 
289        1/1              end else if (update_round) begin
           Tests:       T1 T2 T3 
290        1/1                round_q <= round_d;
           Tests:       T1 T2 T3 
291                         end
                        MISSING_ELSE
292                       end
293                     
294                       always_ff @(posedge clk_i or negedge rst_ni) begin
295        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
296        1/1                fifo_wdata_sel_o <= 3'h 0;
           Tests:       T1 T2 T3 
297        1/1              end else if (clr_fifo_wdata_sel) begin
           Tests:       T1 T2 T3 
298        1/1                fifo_wdata_sel_o <= 3'h 0;
           Tests:       T1 T2 T3 
299        1/1              end else if (fifo_wsel_o && fifo_wvalid_o) begin
           Tests:       T1 T2 T4 
300        1/1                fifo_wdata_sel_o <= fifo_wdata_sel_o + 1'b1; // increment by 1
           Tests:       T1 T2 T4 
301                         end
                   ==>  MISSING_ELSE
302                       end
303                     
304        1/1            assign sel_msglen = (round_q == Inner) ? SelIPadMsg : SelOPadMsg ;
           Tests:       T1 T2 T3 
305                     
306                       always_ff @(posedge clk_i or negedge rst_ni) begin : state_ff
307        2/2              if (!rst_ni) st_q <= StIdle;
           Tests:       T1 T2 T3  | T1 T2 T3 
308        1/1              else         st_q <= st_d;
           Tests:       T1 T2 T3 
309                       end
310                     
311                       always_comb begin : next_state
312        1/1              hmac_hash_done     = 1'b0;
           Tests:       T1 T2 T3 
313        1/1              hmac_sha_rvalid    = 1'b0;
           Tests:       T1 T2 T3 
314        1/1              clr_txcount        = 1'b0;
           Tests:       T1 T2 T3 
315        1/1              load_txcount       = 1'b0;
           Tests:       T1 T2 T3 
316        1/1              update_round       = 1'b0;
           Tests:       T1 T2 T3 
317        1/1              round_d            = Inner;
           Tests:       T1 T2 T3 
318        1/1              fifo_wsel_o        = 1'b0;   // from register
           Tests:       T1 T2 T3 
319        1/1              fifo_wvalid_o      = 1'b0;
           Tests:       T1 T2 T3 
320        1/1              clr_fifo_wdata_sel = 1'b1;
           Tests:       T1 T2 T3 
321        1/1              sel_rdata          = SelFifo;
           Tests:       T1 T2 T3 
322        1/1              hash_start         = 1'b0;
           Tests:       T1 T2 T3 
323        1/1              hash_continue      = 1'b0;
           Tests:       T1 T2 T3 
324        1/1              hash_process       = 1'b0;
           Tests:       T1 T2 T3 
325        1/1              st_d               = st_q;
           Tests:       T1 T2 T3 
326                     
327        1/1              unique case (st_q)
           Tests:       T1 T2 T3 
328                           StIdle: begin
329                             // reset round to Inner
330                             // we always switch context into inner round since outer round computes once over
331                             // single block at the end (outer key pad + inner hash)
332        1/1                  update_round = 1'b1;
           Tests:       T1 T2 T3 
333        1/1                  round_d      = Inner;
           Tests:       T1 T2 T3 
334        1/1                  if (hmac_en_i && reg_hash_start_i) begin
           Tests:       T1 T2 T3 
335        1/1                    st_d = StIPad; // start at StIPad if told to start
           Tests:       T1 T2 T4 
336                     
337        1/1                    clr_txcount  = 1'b1;
           Tests:       T1 T2 T4 
338        1/1                    hash_start   = 1'b1;
           Tests:       T1 T2 T4 
339        1/1                  end else if (hmac_en_i && reg_hash_continue_i) begin
           Tests:       T1 T2 T3 
340        1/1                    st_d = StMsg; // skip StIPad if told to continue - assumed it finished StIPad
           Tests:       T7 T8 T9 
341                     
342        1/1                    load_txcount  = 1'b1;
           Tests:       T7 T8 T9 
343        1/1                    hash_continue = 1'b1;
           Tests:       T7 T8 T9 
344                             end else begin
345        1/1                    st_d = StIdle;
           Tests:       T1 T2 T3 
346                             end
347                           end
348                     
349                           StIPad: begin
350        1/1                  sel_rdata = SelIPad;
           Tests:       T1 T2 T4 
351                     
352        1/1                  if (txcnt_eq_blksz) begin
           Tests:       T1 T2 T4 
353        1/1                    st_d = StMsg;
           Tests:       T1 T2 T4 
354                     
355        1/1                    hmac_sha_rvalid = 1'b0; // block new read request
           Tests:       T1 T2 T4 
356                             end else begin
357        1/1                    st_d = StIPad;
           Tests:       T1 T2 T4 
358                     
359        1/1                    hmac_sha_rvalid = 1'b1;
           Tests:       T1 T2 T4 
360                             end
361                           end
362                     
363                           StMsg: begin
364        1/1                  sel_rdata   = SelFifo;
           Tests:       T1 T2 T4 
365        1/1                  fifo_wsel_o = (round_q == Outer);
           Tests:       T1 T2 T4 
366                     
367        1/1                  if ( (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
           Tests:       T1 T2 T4 
368                                 && (txcount >= sha_message_length_o)) begin
369        1/1                    st_d    = StWaitResp;
           Tests:       T1 T2 T4 
370                     
371        1/1                    hmac_sha_rvalid = 1'b0; // block reading words from MSG FIFO
           Tests:       T1 T2 T4 
372        1/1                    hash_process    = (round_q == Outer);
           Tests:       T1 T2 T4 
373        1/1                  end else if (txcnt_eq_blksz && (txcount >= sha_message_length_o)
           Tests:       T1 T2 T4 
374                                          && reg_hash_stop_q && (round_q == Inner)) begin
375                               // wait till all MSG words are pushed out from FIFO (txcount reaches msg length)
376                               // before transitioning to StWaitResp to wait on sha_hash_done_i and disabling
377                               // reading from MSG FIFO
378        1/1                    st_d =  StWaitResp;
           Tests:       T7 T8 T9 
379                     
380        1/1                    hmac_sha_rvalid = 1'b0;
           Tests:       T7 T8 T9 
381                             end else begin
382        1/1                    st_d            = StMsg;
           Tests:       T1 T2 T4 
383        1/1                    hmac_sha_rvalid = fifo_rvalid_i;
           Tests:       T1 T2 T4 
384                             end
385                           end
386                     
387                           StWaitResp: begin
388        1/1                  hmac_sha_rvalid = 1'b0;
           Tests:       T1 T2 T4 
389                     
390        1/1                  if (sha_hash_done_i) begin
           Tests:       T1 T2 T4 
391        1/1                    if (round_q == Outer) begin
           Tests:       T1 T2 T4 
392        1/1                      st_d = StDone;
           Tests:       T1 T2 T4 
393                               end else begin // round_q == Inner
394        1/1                      if (reg_hash_stop_q) begin
           Tests:       T1 T2 T4 
395        1/1                        st_d = StDone;
           Tests:       T7 T8 T9 
396                                 end else begin
397        1/1                        st_d = StPushToMsgFifo;
           Tests:       T1 T2 T4 
398                                 end
399                               end
400                             end else begin
401        1/1                    st_d = StWaitResp;
           Tests:       T1 T2 T4 
402                             end
403                           end
404                     
405                           StPushToMsgFifo: begin
406        1/1                  hmac_sha_rvalid    = 1'b0;
           Tests:       T1 T2 T4 
407        1/1                  fifo_wsel_o        = 1'b1;
           Tests:       T1 T2 T4 
408        1/1                  fifo_wvalid_o      = 1'b1;
           Tests:       T1 T2 T4 
409        1/1                  clr_fifo_wdata_sel = 1'b0;
           Tests:       T1 T2 T4 
410                     
411        1/1                  if (fifo_wready_i && (((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) ||
           Tests:       T1 T2 T4 
412                                                  ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) ||
413                                                  ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384)))) begin
414                     
415        1/1                    st_d = StOPad;
           Tests:       T1 T2 T4 
416                     
417        1/1                    clr_txcount  = 1'b1;
           Tests:       T1 T2 T4 
418        1/1                    update_round = 1'b1;
           Tests:       T1 T2 T4 
419        1/1                    round_d      = Outer;
           Tests:       T1 T2 T4 
420        1/1                    hash_start   = 1'b1;
           Tests:       T1 T2 T4 
421                             end else begin
422        1/1                    st_d = StPushToMsgFifo;
           Tests:       T1 T2 T4 
423                     
424                             end
425                           end
426                     
427                           StOPad: begin
428        1/1                  sel_rdata   = SelOPad;
           Tests:       T1 T2 T4 
429        1/1                  fifo_wsel_o = 1'b1; // Remained HMAC select to indicate HMAC is in second stage
           Tests:       T1 T2 T4 
430                     
431        1/1                  if (txcnt_eq_blksz) begin
           Tests:       T1 T2 T4 
432        1/1                    st_d = StMsg;
           Tests:       T1 T2 T4 
433                     
434        1/1                    hmac_sha_rvalid = 1'b0; // block new read request
           Tests:       T1 T2 T4 
435                             end else begin
436        1/1                    st_d = StOPad;
           Tests:       T1 T2 T4 
437                     
438        1/1                    hmac_sha_rvalid = 1'b1;
           Tests:       T1 T2 T4 
439                             end
440                           end
441                     
442                           StDone: begin
443                             // raise interrupt (hash_done)
444        1/1                  st_d = StIdle;
           Tests:       T1 T2 T4 
445                     
446        1/1                  hmac_hash_done = 1'b1;
           Tests:       T1 T2 T4 
447                           end
448                     
449                           default: begin
450                             st_d = StIdle;
451                           end
452                     
453                         endcase
454                       end
455                     
456                       // raise reg_hash_stop_d flag at reg_hash_stop_i and keep it until sha_hash_done_i is asserted
457                       // to indicate the hashing operation on current block has completed
458        1/1            assign reg_hash_stop_d = (reg_hash_stop_i == 1'b1)                            ? 1'b1 :
           Tests:       T1 T2 T3 
459                                                (sha_hash_done_i == 1'b1 && reg_hash_stop_q == 1'b1) ? 1'b0 :
460                                                                                                       reg_hash_stop_q;
461                     
462                       always_ff @(posedge clk_i or negedge rst_ni) begin
463        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
464        1/1                reg_hash_stop_q <= 1'b0;
           Tests:       T1 T2 T3 
465                         end else begin
466        1/1                reg_hash_stop_q <= reg_hash_stop_d;
           Tests:       T1 T2 T3 
467                         end
468                       end
469                     
470                       // Idle status signaling: This module ..
471        1/1            assign idle_d =
           Tests:       T1 T2 T3 
472                           // .. is not idle when told to start or continue
473                           (reg_hash_start_i || reg_hash_continue_i) ? 1'b0 :
474                           // .. is idle when the FSM is in the Idle state
475                           (st_q == StIdle) ? 1'b1 :
476                           // .. is idle when it has processed a complete block of a message and is told to stop in any
477                           // FSM state
478                           (txcnt_eq_blksz && reg_hash_stop_d) ? 1'b1 :
479                           // .. and keeps the current idle state in all other cases.
480                           idle_q;
481                     
482        1/1            assign idle_o = idle_d;
           Tests:       T1 T2 T3 
483                     
484                       always_ff @(posedge clk_i or negedge rst_ni) begin
485        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
486        1/1                idle_q <= 1'b1;
           Tests:       T1 T2 T3 
487                         end else begin
488        1/1                idle_q <= idle_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : hmac_core

	Total	Covered	Percent
Conditions	213	200	93.90
Logical	213	200	93.90
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (hmac_en_i ? hash_start : reg_hash_start_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       121
 EXPRESSION (hmac_en_i ? hash_continue : reg_hash_continue_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION (hmac_en_i ? (reg_hash_process_i | hash_process) : reg_hash_process_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       123
 SUB-EXPRESSION (reg_hash_process_i | hash_process)
                 ---------1--------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       124
 EXPRESSION (hmac_en_i ? hmac_hash_done : sha_hash_done_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       189
 EXPRESSION (hmac_en_i ? ((st_q == StMsg) & sha_rready_i) : sha_rready_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       189
 SUB-EXPRESSION ((st_q == StMsg) & sha_rready_i)
                 -------1-------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       189
 SUB-EXPRESSION (st_q == StMsg)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       191
 EXPRESSION (((!hmac_en_i)) ? fifo_rvalid_i : hmac_sha_rvalid)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION 
 Number  Term
      1  ((!hmac_en_i)) ? fifo_rdata_i : (((sel_rdata == SelIPad) && (digest_size_i == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && (digest_size_i == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T19

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelIPad) && (digest_size_i == SHA2_256))
                 -----------1----------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T4,T6,T19

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       192
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                 -----------1----------    ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T4

 LINE       192
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T19

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelOPad) && (digest_size_i == SHA2_256))
                 -----------1----------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T4,T6,T19

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       192
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                 -----------1----------    ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T4

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))
                 -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelFifo)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION (sel_msglen == SelIPadMsg)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       214
 EXPRESSION (digest_size_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       216
 EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
             -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T4

 LINE       216
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       216
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T4

 LINE       219
 EXPRESSION (sel_msglen == SelOPadMsg)
            -------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T4

 LINE       221
 EXPRESSION (digest_size_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T6,T19

 LINE       223
 EXPRESSION (digest_size_i == SHA2_384)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T18
1	Covered	T2,T4,T18

 LINE       225
 EXPRESSION (digest_size_i == SHA2_512)
            -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T4,T18

 LINE       238
 EXPRESSION ((txcount[(BlockSizeBitsSHA256 - 1):0] == '0) && (txcount != '0))
             ----------------------1---------------------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T4

 LINE       238
 SUB-EXPRESSION (txcount[(BlockSizeBitsSHA256 - 1):0] == '0)
                ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       238
 SUB-EXPRESSION (txcount != '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T4

 LINE       239
 EXPRESSION ((txcount[(BlockSizeBitsSHA512 - 1):0] == '0) && (txcount != '0))
             ----------------------1---------------------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T18
1	1	Covered	T1,T2,T4

 LINE       239
 SUB-EXPRESSION (txcount[(BlockSizeBitsSHA512 - 1):0] == '0)
                ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       239
 SUB-EXPRESSION (txcount != '0)
                -------1-------

-1-	Status	Tests
0	Covered	T2,T4,T18
1	Covered	T1,T2,T4

 LINE       240
 EXPRESSION ((txcount[(BlockSizeBitsSHA512 - 1):0] == '0) && (txcount != '0))
             ----------------------1---------------------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T5

 LINE       240
 SUB-EXPRESSION (txcount[(BlockSizeBitsSHA512 - 1):0] == '0)
                ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T4

 LINE       240
 SUB-EXPRESSION (txcount != '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T4

 LINE       245
 EXPRESSION (sha_rready_i && sha_rvalid_o)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       281
 EXPRESSION (hmac_hash_done || reg_hash_start_i || reg_hash_continue_i)
             -------1------    --------2-------    ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T5
0	1	0	Covered	T1,T2,T4
1	0	0	Covered	T1,T2,T4

 LINE       299
 EXPRESSION (fifo_wsel_o && fifo_wvalid_o)
             -----1-----    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       304
 EXPRESSION ((round_q == Inner) ? SelIPadMsg : SelOPadMsg)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       304
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       334
 EXPRESSION (hmac_en_i && reg_hash_start_i)
             ----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       339
 EXPRESSION (hmac_en_i && reg_hash_continue_i)
             ----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       365
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       367
 EXPRESSION ((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length_o))
             ----------------------------------1----------------------------------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       367
 SUB-EXPRESSION (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
                 ----------------------1----------------------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       367
 SUB-EXPRESSION ((round_q == Inner) && reg_hash_process_flag)
                 ---------1--------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       367
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       367
 SUB-EXPRESSION (round_q == Outer)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       372
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       373
 EXPRESSION (txcnt_eq_blksz && (txcount >= sha_message_length_o) && reg_hash_stop_q && (round_q == Inner))
             -------1------    ----------------2----------------    -------3-------    ---------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Covered	T52,T53,T54
1	1	0	1	Covered	T2,T4,T6
1	1	1	0	Not Covered
1	1	1	1	Covered	T7,T8,T9

 LINE       373
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       391
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       411
 EXPRESSION 
 Number  Term
      1  fifo_wready_i && 
      2  (((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) || ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384))))

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       411
 SUB-EXPRESSION 
 Number  Term
      1  ((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || 
      2  ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) || 
      3  ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384)))

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T4
0	0	1	Covered	T2,T4,T18
0	1	0	Covered	T1,T4,T18
1	0	0	Covered	T4,T6,T19

 LINE       411
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256))
                 -------------1------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T19
1	0	Covered	T1,T2,T4
1	1	Covered	T4,T6,T19

 LINE       411
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd7)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       411
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T6,T19

 LINE       411
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T18
1	0	Not Covered
1	1	Covered	T1,T4,T18

 LINE       411
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd15)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T4,T18

 LINE       411
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T4,T18

 LINE       411
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T18
1	0	Covered	T1,T4,T18
1	1	Covered	T2,T4,T18

 LINE       411
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd11)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       411
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T2,T4,T18

 LINE       458
 EXPRESSION ((reg_hash_stop_i == 1'b1) ? 1'b1 : (((sha_hash_done_i == 1'b1) && (reg_hash_stop_q == 1'b1)) ? 1'b0 : reg_hash_stop_q))
             ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       458
 SUB-EXPRESSION (reg_hash_stop_i == 1'b1)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       458
 SUB-EXPRESSION (((sha_hash_done_i == 1'b1) && (reg_hash_stop_q == 1'b1)) ? 1'b0 : reg_hash_stop_q)
                 ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       458
 SUB-EXPRESSION ((sha_hash_done_i == 1'b1) && (reg_hash_stop_q == 1'b1))
                 ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       458
 SUB-EXPRESSION (sha_hash_done_i == 1'b1)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       458
 SUB-EXPRESSION (reg_hash_stop_q == 1'b1)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       471
 EXPRESSION ((reg_hash_start_i || reg_hash_continue_i) ? 1'b0 : ((st_q == StIdle) ? 1'b1 : ((txcnt_eq_blksz && reg_hash_stop_d) ? 1'b1 : idle_q)))
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       471
 SUB-EXPRESSION (reg_hash_start_i || reg_hash_continue_i)
                 --------1-------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T4

 LINE       471
 SUB-EXPRESSION ((st_q == StIdle) ? 1'b1 : ((txcnt_eq_blksz && reg_hash_stop_d) ? 1'b1 : idle_q))
                 --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       471
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       471
 SUB-EXPRESSION ((txcnt_eq_blksz && reg_hash_stop_d) ? 1'b1 : idle_q)
                 -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T7,T8,T9

 LINE       471
 SUB-EXPRESSION (txcnt_eq_blksz && reg_hash_stop_d)
                 -------1------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T8,T24,T55
1	0	Covered	T1,T2,T4
1	1	Covered	T7,T8,T9

---

FSM Coverage for Module : hmac_core

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	9	9	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StDone	392	Covered	T1,T2,T4
StIPad	335	Covered	T1,T2,T4
StIdle	345	Covered	T1,T2,T3
StMsg	340	Covered	T1,T2,T4
StOPad	415	Covered	T1,T2,T4
StPushToMsgFifo	397	Covered	T1,T2,T4
StWaitResp	369	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
StDone->StIdle	444	Covered	T1,T2,T4
StIPad->StMsg	353	Covered	T1,T2,T4
StIdle->StIPad	335	Covered	T1,T2,T4
StIdle->StMsg	340	Covered	T7,T8,T9
StMsg->StWaitResp	369	Covered	T1,T2,T4
StOPad->StMsg	432	Covered	T1,T2,T4
StPushToMsgFifo->StOPad	415	Covered	T1,T2,T4
StWaitResp->StDone	392	Covered	T1,T2,T4
StWaitResp->StPushToMsgFifo	397	Covered	T1,T2,T4

---

Branch Coverage for Module : hmac_core

	Line No.	Total	Covered	Percent
Branches		91	85	93.41
TERNARY	120	2	2	100.00
TERNARY	121	2	2	100.00
TERNARY	123	2	2	100.00
TERNARY	124	2	2	100.00
TERNARY	189	2	2	100.00
TERNARY	191	2	2	100.00
TERNARY	192	7	6	85.71
TERNARY	304	2	2	100.00
TERNARY	458	3	3	100.00
TERNARY	471	4	4	100.00
CASE	137	6	6	100.00
IF	209	9	7	77.78
CASE	237	4	4	100.00
IF	254	7	6	85.71
IF	271	2	2	100.00
IF	277	4	4	100.00
IF	287	3	3	100.00
IF	295	4	3	75.00
IF	307	2	2	100.00
CASE	327	18	17	94.44
IF	463	2	2	100.00
IF	485	2	2	100.00

120          assign sha_hash_start_o    = (hmac_en_i) ? hash_start    : reg_hash_start_i;
                                                      -1-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

121          assign sha_hash_continue_o = (hmac_en_i) ? hash_continue : reg_hash_continue_i;
                                                      -1-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

123          assign sha_hash_process_o  = (hmac_en_i) ? reg_hash_process_i | hash_process : reg_hash_process_i;
                                                      -1-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

124          assign hash_done_o         = (hmac_en_i) ? hmac_hash_done                    : sha_hash_done_i;
                                                      -1-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

189          assign fifo_rready_o = (hmac_en_i) ? (st_q == StMsg) & sha_rready_i : sha_rready_i ;
                                                -1-  
                                                ==>  
                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

191          assign sha_rvalid_o  = (!hmac_en_i) ? fifo_rvalid_i : hmac_sha_rvalid ;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

192          assign sha_rdata_o =
                                 
193            (!hmac_en_i)    ? fifo_rdata_i                                                             :
                               -1-  
                               ==>  
194            (sel_rdata == SelIPad && digest_size_i == SHA2_256)
                                                                  
195                          ? '{data: i_pad_256[(BlockSizeSHA256-1)-32*pad_index_256-:32], mask: '1} :
                             -2-  
                             ==>  
196            (sel_rdata == SelIPad && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                                                                                                     
197                          ? '{data: i_pad_512[(BlockSizeSHA512-1)-32*pad_index_512-:32], mask: '1} :
                             -3-  
                             ==>  
198            (sel_rdata == SelOPad && digest_size_i == SHA2_256)
                                                                  
199                          ? '{data: o_pad_256[(BlockSizeSHA256-1)-32*pad_index_256-:32], mask: '1} :
                             -4-  
                             ==>  
200            (sel_rdata == SelOPad && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                                                                                                     
201                          ? '{data: o_pad_512[(BlockSizeSHA512-1)-32*pad_index_512-:32], mask: '1} :
                             -5-  
                             ==>  
202            (sel_rdata == SelFifo) ? fifo_rdata_i                                                    :
                                      -6-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T4,T6,T19
0	0	1	-	-	-	Covered	T1,T2,T4
0	0	0	1	-	-	Covered	T4,T6,T19
0	0	0	0	1	-	Covered	T1,T2,T4
0	0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	0	Not Covered

304          assign sel_msglen = (round_q == Inner) ? SelIPadMsg : SelOPadMsg ;
                                                    -1-  
                                                    ==>  
                                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

458          assign reg_hash_stop_d = (reg_hash_stop_i == 1'b1)                            ? 1'b1 :
                                                                                           -1-  
                                                                                           ==>  
459                                   (sha_hash_done_i == 1'b1 && reg_hash_stop_q == 1'b1) ? 1'b0 :
                                                                                           -2-  
                                                                                           ==>  
                                                                                           ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

471          assign idle_d =
                            
472              // .. is not idle when told to start or continue
                                                                 
473              (reg_hash_start_i || reg_hash_continue_i) ? 1'b0 :
                                                           -1-  
                                                           ==>  
474              // .. is idle when the FSM is in the Idle state
                                                                
475              (st_q == StIdle) ? 1'b1 :
                                  -2-  
                                  ==>  
476              // .. is idle when it has processed a complete block of a message and is told to stop in any
                                                                                                             
477              // FSM state
                             
478              (txcnt_eq_blksz && reg_hash_stop_d) ? 1'b1 :
                                                     -3-  
                                                     ==>  
                                                     ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T4
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T4

137            unique case (key_length_i)
                      -1-  
138              Key_128: begin
139                i_pad_256 = {secret_key_i[1023:896],
                   ==>
140                            {(BlockSizeSHA256-128){1'b0}}} ^ {(BlockSizeSHA256/8){8'h36}};
141                i_pad_512 = {secret_key_i[1023:896],
142                            {(BlockSizeSHA512-128){1'b0}}} ^ {(BlockSizeSHA512/8){8'h36}};
143                o_pad_256 = {secret_key_i[1023:896],
144                            {(BlockSizeSHA256-128){1'b0}}} ^ {(BlockSizeSHA256/8){8'h5c}};
145                o_pad_512 = {secret_key_i[1023:896],
146                            {(BlockSizeSHA512-128){1'b0}}} ^ {(BlockSizeSHA512/8){8'h5c}};
147              end
148              Key_256: begin
149                i_pad_256 = {secret_key_i[1023:768],
                   ==>
150                            {(BlockSizeSHA256-256){1'b0}}} ^ {(BlockSizeSHA256/8){8'h36}};
151                i_pad_512 = {secret_key_i[1023:768],
152                            {(BlockSizeSHA512-256){1'b0}}} ^ {(BlockSizeSHA512/8){8'h36}};
153                o_pad_256 = {secret_key_i[1023:768],
154                            {(BlockSizeSHA256-256){1'b0}}} ^ {(BlockSizeSHA256/8){8'h5c}};
155                o_pad_512 = {secret_key_i[1023:768],
156                            {(BlockSizeSHA512-256){1'b0}}} ^ {(BlockSizeSHA512/8){8'h5c}};
157              end
158              Key_384: begin
159                i_pad_256 = {secret_key_i[1023:640],
                   ==>
160                            {(BlockSizeSHA256-384){1'b0}}} ^ {(BlockSizeSHA256/8){8'h36}};
161                i_pad_512 = {secret_key_i[1023:640],
162                            {(BlockSizeSHA512-384){1'b0}}} ^ {(BlockSizeSHA512/8){8'h36}};
163                o_pad_256 = {secret_key_i[1023:640],
164                            {(BlockSizeSHA256-384){1'b0}}} ^ {(BlockSizeSHA256/8){8'h5c}};
165                o_pad_512 = {secret_key_i[1023:640],
166                            {(BlockSizeSHA512-384){1'b0}}} ^ {(BlockSizeSHA512/8){8'h5c}};
167              end
168              Key_512: begin
169                i_pad_256 = secret_key_i[1023:512] ^ {(BlockSizeSHA256/8){8'h36}};
                   ==>
170                i_pad_512 = {secret_key_i[1023:512],
171                            {(BlockSizeSHA512-512){1'b0}}} ^ {(BlockSizeSHA512/8){8'h36}};
172                o_pad_256 = secret_key_i[1023:512] ^ {(BlockSizeSHA256/8){8'h5c}};
173                o_pad_512 = {secret_key_i[1023:512],
174                            {(BlockSizeSHA512-512){1'b0}}} ^ {(BlockSizeSHA512/8){8'h5c}};
175              end
176              Key_1024: begin // not allowed to be configured for SHA-2 256
177                // zero out for SHA-2 256
178                i_pad_256 = '{default: '0};
                   ==>
179                i_pad_512 = secret_key_i[1023:0]   ^ {(BlockSizeSHA512/8){8'h36}};
180                // zero out for SHA-2 256
181                o_pad_256 = '{default: '0};
182                o_pad_512 = secret_key_i[1023:0]   ^ {(BlockSizeSHA512/8){8'h5c}};
183              end
184              default: begin
                 ==>

Branches:

-1-	Status	Tests
Key_128	Covered	T1,T2,T4
Key_256	Covered	T1,T2,T4
Key_384	Covered	T1,T2,T4
Key_512	Covered	T1,T4,T6
Key_1024	Covered	T1,T2,T4
default	Covered	T1,T2,T3

209            if (!hmac_en_i) begin
               -1-  
210              sha_msg_len = message_length_i;
                 ==>
211            // HASH = (o_pad || HASH_INTERMEDIATE (i_pad || msg))
212            // message length for HASH_INTERMEDIATE = block size (i_pad) + message length
213            end else if (sel_msglen == SelIPadMsg) begin
                        -2-  
214              if (digest_size_i == SHA2_256) begin
                 -3-  
215                sha_msg_len = message_length_i + BlockSizeSHA256in64;
                   ==>
216              end else if ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)) begin
                          -4-  
217                sha_msg_len = message_length_i + BlockSizeSHA512in64;
                   ==>
218              end
                 MISSING_ELSE
                 ==>
219            end else if (sel_msglen == SelOPadMsg) begin
                        -5-  
220            // message length for HASH = block size (o_pad) + HASH_INTERMEDIATE digest length
221              if (digest_size_i == SHA2_256) begin
                 -6-  
222                sha_msg_len = BlockSizeSHA256in64 + 64'd256;
                   ==>
223              end else if (digest_size_i == SHA2_384) begin
                          -7-  
224                sha_msg_len = BlockSizeSHA512in64 + 64'd384;
                   ==>
225              end else if (digest_size_i == SHA2_512) begin
                          -8-  
226                sha_msg_len = BlockSizeSHA512in64 + 64'd512;
                   ==>
227              end
                 MISSING_ELSE
                 ==>
228            end else
229              sha_msg_len = '0;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
1	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	-	-	Covered	T2,T4,T6
0	1	0	1	-	-	-	-	Covered	T1,T2,T3
0	1	0	0	-	-	-	-	Covered	T1,T2,T4
0	0	-	-	1	1	-	-	Covered	T4,T6,T19
0	0	-	-	1	0	1	-	Covered	T2,T4,T18
0	0	-	-	1	0	0	1	Covered	T1,T4,T18
0	0	-	-	1	0	0	0	Not Covered
0	0	-	-	0	-	-	-	Not Covered

237            unique case (digest_size_i)
                      -1-  
238              SHA2_256: txcnt_eq_blksz = (txcount[BlockSizeBitsSHA256-1:0] == '0) && (txcount != '0);
                 ==>
239              SHA2_384: txcnt_eq_blksz = (txcount[BlockSizeBitsSHA512-1:0] == '0) && (txcount != '0);
                 ==>
240              SHA2_512: txcnt_eq_blksz = (txcount[BlockSizeBitsSHA512-1:0] == '0) && (txcount != '0);
                 ==>
241              default;
                 ==>

Branches:

-1-	Status	Tests
SHA2_256	Covered	T1,T2,T4
SHA2_384	Covered	T1,T2,T4
SHA2_512	Covered	T1,T2,T3
default	Covered	T1,T2,T3

254            if (clr_txcount) begin
               -1-  
255              txcount_d = '0;
                 ==>
256            end else if (load_txcount) begin
                        -2-  
257              // When loading, add block size to the message length because the SW-visible message length
258              // does not include the block containing the key xor'ed with the inner pad.
259              unique case (digest_size_i)
                        -3-  
260                SHA2_256: txcount_d = message_length_i + BlockSizeSHA256in64;
                   ==>
261                SHA2_384: txcount_d = message_length_i + BlockSizeSHA512in64;
                   ==>
262                SHA2_512: txcount_d = message_length_i + BlockSizeSHA512in64;
                   ==>
263                default : txcount_d = message_length_i + '0;
                   ==>
264              endcase
265            end else if (inc_txcount) begin
                        -4-  
266              txcount_d[63:5] = txcount[63:5] + 1'b1; // increment by 32 (data word size)
                 ==>
267            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T4
0	1	SHA2_256	-	Covered	T8,T9,T50
0	1	SHA2_384	-	Covered	T10,T50,T51
0	1	SHA2_512	-	Covered	T7,T9,T20
0	1	default	-	Not Covered
0	0	-	1	Covered	T1,T2,T4
0	0	-	0	Covered	T1,T2,T3

271            if (!rst_ni) txcount <= '0;
               -1-  
               ==>
272            else         txcount <= txcount_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

277            if (!rst_ni) begin
               -1-  
278              reg_hash_process_flag <= 1'b0;
                 ==>
279            end else if (reg_hash_process_i) begin
                        -2-  
280              reg_hash_process_flag <= 1'b1;
                 ==>
281            end else if (hmac_hash_done || reg_hash_start_i || reg_hash_continue_i) begin
                        -3-  
282              reg_hash_process_flag <= 1'b0;
                 ==>
283            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

287            if (!rst_ni) begin
               -1-  
288              round_q <= Inner;
                 ==>
289            end else if (update_round) begin
                        -2-  
290              round_q <= round_d;
                 ==>
291            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T4

295            if (!rst_ni) begin
               -1-  
296              fifo_wdata_sel_o <= 3'h 0;
                 ==>
297            end else if (clr_fifo_wdata_sel) begin
                        -2-         
298              fifo_wdata_sel_o <= 3'h 0;
                 ==>
299            end else if (fifo_wsel_o && fifo_wvalid_o) begin
                        -3-                    
300              fifo_wdata_sel_o <= fifo_wdata_sel_o + 1'b1; // increment by 1
                 ==>
301            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Not Covered

307            if (!rst_ni) st_q <= StIdle;
               -1-  
               ==>
308            else         st_q <= st_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

327            unique case (st_q)
                      -1-  
328              StIdle: begin
329                // reset round to Inner
330                // we always switch context into inner round since outer round computes once over
331                // single block at the end (outer key pad + inner hash)
332                update_round = 1'b1;
333                round_d      = Inner;
334                if (hmac_en_i && reg_hash_start_i) begin
                   -2-  
335                  st_d = StIPad; // start at StIPad if told to start
                     ==>
336        
337                  clr_txcount  = 1'b1;
338                  hash_start   = 1'b1;
339                end else if (hmac_en_i && reg_hash_continue_i) begin
                            -3-  
340                  st_d = StMsg; // skip StIPad if told to continue - assumed it finished StIPad
                     ==>
341        
342                  load_txcount  = 1'b1;
343                  hash_continue = 1'b1;
344                end else begin
345                  st_d = StIdle;
                     ==>
346                end
347              end
348        
349              StIPad: begin
350                sel_rdata = SelIPad;
351        
352                if (txcnt_eq_blksz) begin
                   -4-  
353                  st_d = StMsg;
                     ==>
354        
355                  hmac_sha_rvalid = 1'b0; // block new read request
356                end else begin
357                  st_d = StIPad;
                     ==>
358        
359                  hmac_sha_rvalid = 1'b1;
360                end
361              end
362        
363              StMsg: begin
364                sel_rdata   = SelFifo;
365                fifo_wsel_o = (round_q == Outer);
366        
367                if ( (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
                   -5-  
368                    && (txcount >= sha_message_length_o)) begin
369                  st_d    = StWaitResp;
                     ==>
370        
371                  hmac_sha_rvalid = 1'b0; // block reading words from MSG FIFO
372                  hash_process    = (round_q == Outer);
373                end else if (txcnt_eq_blksz && (txcount >= sha_message_length_o)
                            -6-  
374                             && reg_hash_stop_q && (round_q == Inner)) begin
375                  // wait till all MSG words are pushed out from FIFO (txcount reaches msg length)
376                  // before transitioning to StWaitResp to wait on sha_hash_done_i and disabling
377                  // reading from MSG FIFO
378                  st_d =  StWaitResp;
                     ==>
379        
380                  hmac_sha_rvalid = 1'b0;
381                end else begin
382                  st_d            = StMsg;
                     ==>
383                  hmac_sha_rvalid = fifo_rvalid_i;
384                end
385              end
386        
387              StWaitResp: begin
388                hmac_sha_rvalid = 1'b0;
389        
390                if (sha_hash_done_i) begin
                   -7-  
391                  if (round_q == Outer) begin
                     -8-  
392                    st_d = StDone;
                       ==>
393                  end else begin // round_q == Inner
394                    if (reg_hash_stop_q) begin
                       -9-  
395                      st_d = StDone;
                         ==>
396                    end else begin
397                      st_d = StPushToMsgFifo;
                         ==>
398                    end
399                  end
400                end else begin
401                  st_d = StWaitResp;
                     ==>
402                end
403              end
404        
405              StPushToMsgFifo: begin
406                hmac_sha_rvalid    = 1'b0;
407                fifo_wsel_o        = 1'b1;
408                fifo_wvalid_o      = 1'b1;
409                clr_fifo_wdata_sel = 1'b0;
410        
411                if (fifo_wready_i && (((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) ||
                   -10-                         
412                                     ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) ||
413                                     ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384)))) begin
414        
415                  st_d = StOPad;
                     ==>
416        
417                  clr_txcount  = 1'b1;
418                  update_round = 1'b1;
419                  round_d      = Outer;
420                  hash_start   = 1'b1;
421                end else begin
422                  st_d = StPushToMsgFifo;
                     ==>
423        
424                end
425              end
426        
427              StOPad: begin
428                sel_rdata   = SelOPad;
429                fifo_wsel_o = 1'b1; // Remained HMAC select to indicate HMAC is in second stage
430        
431                if (txcnt_eq_blksz) begin
                   -11-  
432                  st_d = StMsg;
                     ==>
433        
434                  hmac_sha_rvalid = 1'b0; // block new read request
435                end else begin
436                  st_d = StOPad;
                     ==>
437        
438                  hmac_sha_rvalid = 1'b1;
439                end
440              end
441        
442              StDone: begin
443                // raise interrupt (hash_done)
444                st_d = StIdle;
                   ==>
445        
446                hmac_hash_done = 1'b1;
447              end
448        
449              default: begin
450                st_d = StIdle;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StIdle	0	1	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
StIdle	0	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIPad	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
StIPad	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
StMsg	-	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T4
StMsg	-	-	-	0	1	-	-	-	-	-	Covered	T7,T8,T9
StMsg	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
StWaitResp	-	-	-	-	-	1	1	-	-	-	Covered	T1,T2,T4
StWaitResp	-	-	-	-	-	1	0	1	-	-	Covered	T7,T8,T9
StWaitResp	-	-	-	-	-	1	0	0	-	-	Covered	T1,T2,T4
StWaitResp	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T4
StPushToMsgFifo	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T4
StPushToMsgFifo	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T4
StOPad	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
StOPad	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
StDone	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	-	-	-	-	-	-	Not Covered

463            if (!rst_ni) begin
               -1-  
464              reg_hash_stop_q <= 1'b0;
                 ==>
465            end else begin
466              reg_hash_stop_q <= reg_hash_stop_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

485            if (!rst_ni) begin
               -1-  
486              idle_q <= 1'b1;
                 ==>
487            end else begin
488              idle_q <= idle_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_hmac

	Line No.	Total	Covered	Percent
TOTAL		169	169	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
ALWAYS	132	25	25	100.00
CONT_ASSIGN	189	1	1	100.00
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
ALWAYS	208	15	15	100.00
CONT_ASSIGN	232	1	1	100.00
ALWAYS	235	5	5	100.00
CONT_ASSIGN	245	1	1	100.00
ALWAYS	253	10	10	100.00
ALWAYS	271	3	3	100.00
ALWAYS	277	6	6	100.00
ALWAYS	287	4	4	100.00
ALWAYS	295	6	6	100.00
CONT_ASSIGN	304	1	1	100.00
ALWAYS	307	3	3	100.00
ALWAYS	312	71	71	100.00
CONT_ASSIGN	458	1	1	100.00
ALWAYS	463	3	3	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
ALWAYS	485	3	3	100.00

119                     
120        1/1            assign sha_hash_start_o    = (hmac_en_i) ? hash_start    : reg_hash_start_i;
           Tests:       T1 T2 T3 
121        1/1            assign sha_hash_continue_o = (hmac_en_i) ? hash_continue : reg_hash_continue_i;
           Tests:       T1 T2 T3 
122                     
123        1/1            assign sha_hash_process_o  = (hmac_en_i) ? reg_hash_process_i | hash_process : reg_hash_process_i;
           Tests:       T1 T2 T3 
124        1/1            assign hash_done_o         = (hmac_en_i) ? hmac_hash_done                    : sha_hash_done_i;
           Tests:       T1 T2 T3 
125                     
126        1/1            assign pad_index_512 = txcount[BlockSizeBitsSHA512-1:HashWordBitsSHA256];
           Tests:       T1 T2 T3 
127        1/1            assign pad_index_256 = txcount[BlockSizeBitsSHA256-1:HashWordBitsSHA256];
           Tests:       T1 T2 T3 
128                     
129                       // adjust inner and outer padding depending on key length and block size
130                       always_comb begin : adjust_key_pad_length
131                         // set defaults
132        1/1              i_pad_256 = '{default: '0};
           Tests:       T1 T2 T3 
133        1/1              i_pad_512 = '{default: '0};
           Tests:       T1 T2 T3 
134        1/1              o_pad_256 = '{default: '0};
           Tests:       T1 T2 T3 
135        1/1              o_pad_512 = '{default: '0};
           Tests:       T1 T2 T3 
136                     
137        1/1              unique case (key_length_i)
           Tests:       T1 T2 T3 
138                           Key_128: begin
139        1/1                  i_pad_256 = {secret_key_i[1023:896],
           Tests:       T1 T2 T4 
140                                         {(BlockSizeSHA256-128){1'b0}}} ^ {(BlockSizeSHA256/8){8'h36}};
141        1/1                  i_pad_512 = {secret_key_i[1023:896],
           Tests:       T1 T2 T4 
142                                         {(BlockSizeSHA512-128){1'b0}}} ^ {(BlockSizeSHA512/8){8'h36}};
143        1/1                  o_pad_256 = {secret_key_i[1023:896],
           Tests:       T1 T2 T4 
144                                         {(BlockSizeSHA256-128){1'b0}}} ^ {(BlockSizeSHA256/8){8'h5c}};
145        1/1                  o_pad_512 = {secret_key_i[1023:896],
           Tests:       T1 T2 T4 
146                                         {(BlockSizeSHA512-128){1'b0}}} ^ {(BlockSizeSHA512/8){8'h5c}};
147                           end
148                           Key_256: begin
149        1/1                  i_pad_256 = {secret_key_i[1023:768],
           Tests:       T1 T2 T4 
150                                         {(BlockSizeSHA256-256){1'b0}}} ^ {(BlockSizeSHA256/8){8'h36}};
151        1/1                  i_pad_512 = {secret_key_i[1023:768],
           Tests:       T1 T2 T4 
152                                         {(BlockSizeSHA512-256){1'b0}}} ^ {(BlockSizeSHA512/8){8'h36}};
153        1/1                  o_pad_256 = {secret_key_i[1023:768],
           Tests:       T1 T2 T4 
154                                         {(BlockSizeSHA256-256){1'b0}}} ^ {(BlockSizeSHA256/8){8'h5c}};
155        1/1                  o_pad_512 = {secret_key_i[1023:768],
           Tests:       T1 T2 T4 
156                                         {(BlockSizeSHA512-256){1'b0}}} ^ {(BlockSizeSHA512/8){8'h5c}};
157                           end
158                           Key_384: begin
159        1/1                  i_pad_256 = {secret_key_i[1023:640],
           Tests:       T1 T2 T4 
160                                         {(BlockSizeSHA256-384){1'b0}}} ^ {(BlockSizeSHA256/8){8'h36}};
161        1/1                  i_pad_512 = {secret_key_i[1023:640],
           Tests:       T1 T2 T4 
162                                         {(BlockSizeSHA512-384){1'b0}}} ^ {(BlockSizeSHA512/8){8'h36}};
163        1/1                  o_pad_256 = {secret_key_i[1023:640],
           Tests:       T1 T2 T4 
164                                         {(BlockSizeSHA256-384){1'b0}}} ^ {(BlockSizeSHA256/8){8'h5c}};
165        1/1                  o_pad_512 = {secret_key_i[1023:640],
           Tests:       T1 T2 T4 
166                                         {(BlockSizeSHA512-384){1'b0}}} ^ {(BlockSizeSHA512/8){8'h5c}};
167                           end
168                           Key_512: begin
169        1/1                  i_pad_256 = secret_key_i[1023:512] ^ {(BlockSizeSHA256/8){8'h36}};
           Tests:       T1 T4 T6 
170        1/1                  i_pad_512 = {secret_key_i[1023:512],
           Tests:       T1 T4 T6 
171                                         {(BlockSizeSHA512-512){1'b0}}} ^ {(BlockSizeSHA512/8){8'h36}};
172        1/1                  o_pad_256 = secret_key_i[1023:512] ^ {(BlockSizeSHA256/8){8'h5c}};
           Tests:       T1 T4 T6 
173        1/1                  o_pad_512 = {secret_key_i[1023:512],
           Tests:       T1 T4 T6 
174                                         {(BlockSizeSHA512-512){1'b0}}} ^ {(BlockSizeSHA512/8){8'h5c}};
175                           end
176                           Key_1024: begin // not allowed to be configured for SHA-2 256
177                             // zero out for SHA-2 256
178        1/1                  i_pad_256 = '{default: '0};
           Tests:       T1 T2 T4 
179        1/1                  i_pad_512 = secret_key_i[1023:0]   ^ {(BlockSizeSHA512/8){8'h36}};
           Tests:       T1 T2 T4 
180                             // zero out for SHA-2 256
181        1/1                  o_pad_256 = '{default: '0};
           Tests:       T1 T2 T4 
182        1/1                  o_pad_512 = secret_key_i[1023:0]   ^ {(BlockSizeSHA512/8){8'h5c}};
           Tests:       T1 T2 T4 
183                           end
184                           default: begin
185                           end
186                         endcase
187                       end
188                     
189        1/1            assign fifo_rready_o = (hmac_en_i) ? (st_q == StMsg) & sha_rready_i : sha_rready_i ;
           Tests:       T1 T2 T3 
190                       // sha_rvalid is controlled by State Machine below.
191        1/1            assign sha_rvalid_o  = (!hmac_en_i) ? fifo_rvalid_i : hmac_sha_rvalid ;
           Tests:       T1 T2 T3 
192        1/1            assign sha_rdata_o =
           Tests:       T1 T2 T3 
193                         (!hmac_en_i)    ? fifo_rdata_i                                                             :
194                         (sel_rdata == SelIPad && digest_size_i == SHA2_256)
195                                       ? '{data: i_pad_256[(BlockSizeSHA256-1)-32*pad_index_256-:32], mask: '1} :
196                         (sel_rdata == SelIPad && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
197                                       ? '{data: i_pad_512[(BlockSizeSHA512-1)-32*pad_index_512-:32], mask: '1} :
198                         (sel_rdata == SelOPad && digest_size_i == SHA2_256)
199                                       ? '{data: o_pad_256[(BlockSizeSHA256-1)-32*pad_index_256-:32], mask: '1} :
200                         (sel_rdata == SelOPad && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
201                                       ? '{data: o_pad_512[(BlockSizeSHA512-1)-32*pad_index_512-:32], mask: '1} :
202                         (sel_rdata == SelFifo) ? fifo_rdata_i                                                    :
203                                       '{default: '0};
204                     
205                       logic [63:0] sha_msg_len;
206                     
207                       always_comb begin: assign_sha_message_length
208        1/1              sha_msg_len = '0;
           Tests:       T1 T2 T3 
209        1/1              if (!hmac_en_i) begin
           Tests:       T1 T2 T3 
210        1/1                sha_msg_len = message_length_i;
           Tests:       T1 T2 T3 
211                         // HASH = (o_pad || HASH_INTERMEDIATE (i_pad || msg))
212                         // message length for HASH_INTERMEDIATE = block size (i_pad) + message length
213        1/1              end else if (sel_msglen == SelIPadMsg) begin
           Tests:       T1 T2 T3 
214        1/1                if (digest_size_i == SHA2_256) begin
           Tests:       T1 T2 T3 
215        1/1                  sha_msg_len = message_length_i + BlockSizeSHA256in64;
           Tests:       T2 T4 T6 
216        1/1                end else if ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)) begin
           Tests:       T1 T2 T3 
217        1/1                  sha_msg_len = message_length_i + BlockSizeSHA512in64;
           Tests:       T1 T2 T3 
218                           end
                        MISSING_ELSE
219        1/1              end else if (sel_msglen == SelOPadMsg) begin
           Tests:       T1 T2 T4 
220                         // message length for HASH = block size (o_pad) + HASH_INTERMEDIATE digest length
221        1/1                if (digest_size_i == SHA2_256) begin
           Tests:       T1 T2 T4 
222        1/1                  sha_msg_len = BlockSizeSHA256in64 + 64'd256;
           Tests:       T4 T6 T19 
223        1/1                end else if (digest_size_i == SHA2_384) begin
           Tests:       T1 T2 T4 
224        1/1                  sha_msg_len = BlockSizeSHA512in64 + 64'd384;
           Tests:       T2 T4 T18 
225        1/1                end else if (digest_size_i == SHA2_512) begin
           Tests:       T1 T4 T18 
226        1/1                  sha_msg_len = BlockSizeSHA512in64 + 64'd512;
           Tests:       T1 T4 T18 
227                           end
                   ==>  MISSING_ELSE
228                         end else
229        excluded           sha_msg_len = '0;
Exclude Annotation: VC_COV_UNR
230                       end
231                     
232        1/1            assign sha_message_length_o = sha_msg_len;
           Tests:       T1 T2 T3 
233                     
234                       always_comb begin
235        1/1              txcnt_eq_blksz = '0;
           Tests:       T1 T2 T3 
236                     
237        1/1              unique case (digest_size_i)
           Tests:       T1 T2 T3 
238        1/1                SHA2_256: txcnt_eq_blksz = (txcount[BlockSizeBitsSHA256-1:0] == '0) && (txcount != '0);
           Tests:       T1 T2 T4 
239        1/1                SHA2_384: txcnt_eq_blksz = (txcount[BlockSizeBitsSHA512-1:0] == '0) && (txcount != '0);
           Tests:       T1 T2 T4 
240        1/1                SHA2_512: txcnt_eq_blksz = (txcount[BlockSizeBitsSHA512-1:0] == '0) && (txcount != '0);
           Tests:       T1 T2 T3 
241                           default;
242                         endcase
243                       end
244                     
245        1/1            assign inc_txcount = sha_rready_i && sha_rvalid_o;
           Tests:       T1 T2 T3 
246                     
247                       // txcount
248                       //    Looks like txcount can be removed entirely here in hmac_core
249                       //    In the first round (InnerPaddedKey), it can just watch process and hash_done
250                       //    In the second round, it only needs count 256 bits for hash digest to trigger
251                       //    hash_process to SHA2
252                       always_comb begin
253        1/1              txcount_d = txcount;
           Tests:       T1 T2 T3 
254        1/1              if (clr_txcount) begin
           Tests:       T1 T2 T3 
255        1/1                txcount_d = '0;
           Tests:       T1 T2 T4 
256        1/1              end else if (load_txcount) begin
           Tests:       T1 T2 T3 
257                           // When loading, add block size to the message length because the SW-visible message length
258                           // does not include the block containing the key xor'ed with the inner pad.
259        1/1                unique case (digest_size_i)
           Tests:       T7 T8 T9 
260        1/1                  SHA2_256: txcount_d = message_length_i + BlockSizeSHA256in64;
           Tests:       T8 T9 T50 
261        1/1                  SHA2_384: txcount_d = message_length_i + BlockSizeSHA512in64;
           Tests:       T10 T50 T51 
262        1/1                  SHA2_512: txcount_d = message_length_i + BlockSizeSHA512in64;
           Tests:       T7 T9 T20 
263                             default : txcount_d = message_length_i + '0;
Exclude Annotation: VC_COV_UNR
264                           endcase
265        1/1              end else if (inc_txcount) begin
           Tests:       T1 T2 T3 
266        1/1                txcount_d[63:5] = txcount[63:5] + 1'b1; // increment by 32 (data word size)
           Tests:       T1 T2 T4 
267                         end
                        MISSING_ELSE
268                       end
269                     
270                       always_ff @(posedge clk_i or negedge rst_ni) begin
271        2/2              if (!rst_ni) txcount <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
272        1/1              else         txcount <= txcount_d;
           Tests:       T1 T2 T3 
273                       end
274                     
275                       // reg_hash_process_i trigger logic
276                       always_ff @(posedge clk_i or negedge rst_ni) begin
277        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
278        1/1                reg_hash_process_flag <= 1'b0;
           Tests:       T1 T2 T3 
279        1/1              end else if (reg_hash_process_i) begin
           Tests:       T1 T2 T3 
280        1/1                reg_hash_process_flag <= 1'b1;
           Tests:       T1 T2 T4 
281        1/1              end else if (hmac_hash_done || reg_hash_start_i || reg_hash_continue_i) begin
           Tests:       T1 T2 T3 
282        1/1                reg_hash_process_flag <= 1'b0;
           Tests:       T1 T2 T4 
283                         end
                        MISSING_ELSE
284                       end
285                     
286                       always_ff @(posedge clk_i or negedge rst_ni) begin
287        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
288        1/1                round_q <= Inner;
           Tests:       T1 T2 T3 
289        1/1              end else if (update_round) begin
           Tests:       T1 T2 T3 
290        1/1                round_q <= round_d;
           Tests:       T1 T2 T3 
291                         end
                        MISSING_ELSE
292                       end
293                     
294                       always_ff @(posedge clk_i or negedge rst_ni) begin
295        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
296        1/1                fifo_wdata_sel_o <= 3'h 0;
           Tests:       T1 T2 T3 
297        1/1              end else if (clr_fifo_wdata_sel) begin
           Tests:       T1 T2 T3 
298        1/1                fifo_wdata_sel_o <= 3'h 0;
           Tests:       T1 T2 T3 
299        1/1              end else if (fifo_wsel_o && fifo_wvalid_o) begin
           Tests:       T1 T2 T4 
300        1/1                fifo_wdata_sel_o <= fifo_wdata_sel_o + 1'b1; // increment by 1
           Tests:       T1 T2 T4 
301                         end
                   ==>  MISSING_ELSE
302                       end
303                     
304        1/1            assign sel_msglen = (round_q == Inner) ? SelIPadMsg : SelOPadMsg ;
           Tests:       T1 T2 T3 
305                     
306                       always_ff @(posedge clk_i or negedge rst_ni) begin : state_ff
307        2/2              if (!rst_ni) st_q <= StIdle;
           Tests:       T1 T2 T3  | T1 T2 T3 
308        1/1              else         st_q <= st_d;
           Tests:       T1 T2 T3 
309                       end
310                     
311                       always_comb begin : next_state
312        1/1              hmac_hash_done     = 1'b0;
           Tests:       T1 T2 T3 
313        1/1              hmac_sha_rvalid    = 1'b0;
           Tests:       T1 T2 T3 
314        1/1              clr_txcount        = 1'b0;
           Tests:       T1 T2 T3 
315        1/1              load_txcount       = 1'b0;
           Tests:       T1 T2 T3 
316        1/1              update_round       = 1'b0;
           Tests:       T1 T2 T3 
317        1/1              round_d            = Inner;
           Tests:       T1 T2 T3 
318        1/1              fifo_wsel_o        = 1'b0;   // from register
           Tests:       T1 T2 T3 
319        1/1              fifo_wvalid_o      = 1'b0;
           Tests:       T1 T2 T3 
320        1/1              clr_fifo_wdata_sel = 1'b1;
           Tests:       T1 T2 T3 
321        1/1              sel_rdata          = SelFifo;
           Tests:       T1 T2 T3 
322        1/1              hash_start         = 1'b0;
           Tests:       T1 T2 T3 
323        1/1              hash_continue      = 1'b0;
           Tests:       T1 T2 T3 
324        1/1              hash_process       = 1'b0;
           Tests:       T1 T2 T3 
325        1/1              st_d               = st_q;
           Tests:       T1 T2 T3 
326                     
327        1/1              unique case (st_q)
           Tests:       T1 T2 T3 
328                           StIdle: begin
329                             // reset round to Inner
330                             // we always switch context into inner round since outer round computes once over
331                             // single block at the end (outer key pad + inner hash)
332        1/1                  update_round = 1'b1;
           Tests:       T1 T2 T3 
333        1/1                  round_d      = Inner;
           Tests:       T1 T2 T3 
334        1/1                  if (hmac_en_i && reg_hash_start_i) begin
           Tests:       T1 T2 T3 
335        1/1                    st_d = StIPad; // start at StIPad if told to start
           Tests:       T1 T2 T4 
336                     
337        1/1                    clr_txcount  = 1'b1;
           Tests:       T1 T2 T4 
338        1/1                    hash_start   = 1'b1;
           Tests:       T1 T2 T4 
339        1/1                  end else if (hmac_en_i && reg_hash_continue_i) begin
           Tests:       T1 T2 T3 
340        1/1                    st_d = StMsg; // skip StIPad if told to continue - assumed it finished StIPad
           Tests:       T7 T8 T9 
341                     
342        1/1                    load_txcount  = 1'b1;
           Tests:       T7 T8 T9 
343        1/1                    hash_continue = 1'b1;
           Tests:       T7 T8 T9 
344                             end else begin
345        1/1                    st_d = StIdle;
           Tests:       T1 T2 T3 
346                             end
347                           end
348                     
349                           StIPad: begin
350        1/1                  sel_rdata = SelIPad;
           Tests:       T1 T2 T4 
351                     
352        1/1                  if (txcnt_eq_blksz) begin
           Tests:       T1 T2 T4 
353        1/1                    st_d = StMsg;
           Tests:       T1 T2 T4 
354                     
355        1/1                    hmac_sha_rvalid = 1'b0; // block new read request
           Tests:       T1 T2 T4 
356                             end else begin
357        1/1                    st_d = StIPad;
           Tests:       T1 T2 T4 
358                     
359        1/1                    hmac_sha_rvalid = 1'b1;
           Tests:       T1 T2 T4 
360                             end
361                           end
362                     
363                           StMsg: begin
364        1/1                  sel_rdata   = SelFifo;
           Tests:       T1 T2 T4 
365        1/1                  fifo_wsel_o = (round_q == Outer);
           Tests:       T1 T2 T4 
366                     
367        1/1                  if ( (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
           Tests:       T1 T2 T4 
368                                 && (txcount >= sha_message_length_o)) begin
369        1/1                    st_d    = StWaitResp;
           Tests:       T1 T2 T4 
370                     
371        1/1                    hmac_sha_rvalid = 1'b0; // block reading words from MSG FIFO
           Tests:       T1 T2 T4 
372        1/1                    hash_process    = (round_q == Outer);
           Tests:       T1 T2 T4 
373        1/1                  end else if (txcnt_eq_blksz && (txcount >= sha_message_length_o)
           Tests:       T1 T2 T4 
374                                          && reg_hash_stop_q && (round_q == Inner)) begin
375                               // wait till all MSG words are pushed out from FIFO (txcount reaches msg length)
376                               // before transitioning to StWaitResp to wait on sha_hash_done_i and disabling
377                               // reading from MSG FIFO
378        1/1                    st_d =  StWaitResp;
           Tests:       T7 T8 T9 
379                     
380        1/1                    hmac_sha_rvalid = 1'b0;
           Tests:       T7 T8 T9 
381                             end else begin
382        1/1                    st_d            = StMsg;
           Tests:       T1 T2 T4 
383        1/1                    hmac_sha_rvalid = fifo_rvalid_i;
           Tests:       T1 T2 T4 
384                             end
385                           end
386                     
387                           StWaitResp: begin
388        1/1                  hmac_sha_rvalid = 1'b0;
           Tests:       T1 T2 T4 
389                     
390        1/1                  if (sha_hash_done_i) begin
           Tests:       T1 T2 T4 
391        1/1                    if (round_q == Outer) begin
           Tests:       T1 T2 T4 
392        1/1                      st_d = StDone;
           Tests:       T1 T2 T4 
393                               end else begin // round_q == Inner
394        1/1                      if (reg_hash_stop_q) begin
           Tests:       T1 T2 T4 
395        1/1                        st_d = StDone;
           Tests:       T7 T8 T9 
396                                 end else begin
397        1/1                        st_d = StPushToMsgFifo;
           Tests:       T1 T2 T4 
398                                 end
399                               end
400                             end else begin
401        1/1                    st_d = StWaitResp;
           Tests:       T1 T2 T4 
402                             end
403                           end
404                     
405                           StPushToMsgFifo: begin
406        1/1                  hmac_sha_rvalid    = 1'b0;
           Tests:       T1 T2 T4 
407        1/1                  fifo_wsel_o        = 1'b1;
           Tests:       T1 T2 T4 
408        1/1                  fifo_wvalid_o      = 1'b1;
           Tests:       T1 T2 T4 
409        1/1                  clr_fifo_wdata_sel = 1'b0;
           Tests:       T1 T2 T4 
410                     
411        1/1                  if (fifo_wready_i && (((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) ||
           Tests:       T1 T2 T4 
412                                                  ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) ||
413                                                  ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384)))) begin
414                     
415        1/1                    st_d = StOPad;
           Tests:       T1 T2 T4 
416                     
417        1/1                    clr_txcount  = 1'b1;
           Tests:       T1 T2 T4 
418        1/1                    update_round = 1'b1;
           Tests:       T1 T2 T4 
419        1/1                    round_d      = Outer;
           Tests:       T1 T2 T4 
420        1/1                    hash_start   = 1'b1;
           Tests:       T1 T2 T4 
421                             end else begin
422        1/1                    st_d = StPushToMsgFifo;
           Tests:       T1 T2 T4 
423                     
424                             end
425                           end
426                     
427                           StOPad: begin
428        1/1                  sel_rdata   = SelOPad;
           Tests:       T1 T2 T4 
429        1/1                  fifo_wsel_o = 1'b1; // Remained HMAC select to indicate HMAC is in second stage
           Tests:       T1 T2 T4 
430                     
431        1/1                  if (txcnt_eq_blksz) begin
           Tests:       T1 T2 T4 
432        1/1                    st_d = StMsg;
           Tests:       T1 T2 T4 
433                     
434        1/1                    hmac_sha_rvalid = 1'b0; // block new read request
           Tests:       T1 T2 T4 
435                             end else begin
436        1/1                    st_d = StOPad;
           Tests:       T1 T2 T4 
437                     
438        1/1                    hmac_sha_rvalid = 1'b1;
           Tests:       T1 T2 T4 
439                             end
440                           end
441                     
442                           StDone: begin
443                             // raise interrupt (hash_done)
444        1/1                  st_d = StIdle;
           Tests:       T1 T2 T4 
445                     
446        1/1                  hmac_hash_done = 1'b1;
           Tests:       T1 T2 T4 
447                           end
448                     
449                           default: begin
450                             st_d = StIdle;
Exclude Annotation: VC_COV_UNR
451                           end
452                     
453                         endcase
454                       end
455                     
456                       // raise reg_hash_stop_d flag at reg_hash_stop_i and keep it until sha_hash_done_i is asserted
457                       // to indicate the hashing operation on current block has completed
458        1/1            assign reg_hash_stop_d = (reg_hash_stop_i == 1'b1)                            ? 1'b1 :
           Tests:       T1 T2 T3 
459                                                (sha_hash_done_i == 1'b1 && reg_hash_stop_q == 1'b1) ? 1'b0 :
460                                                                                                       reg_hash_stop_q;
461                     
462                       always_ff @(posedge clk_i or negedge rst_ni) begin
463        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
464        1/1                reg_hash_stop_q <= 1'b0;
           Tests:       T1 T2 T3 
465                         end else begin
466        1/1                reg_hash_stop_q <= reg_hash_stop_d;
           Tests:       T1 T2 T3 
467                         end
468                       end
469                     
470                       // Idle status signaling: This module ..
471        1/1            assign idle_d =
           Tests:       T1 T2 T3 
472                           // .. is not idle when told to start or continue
473                           (reg_hash_start_i || reg_hash_continue_i) ? 1'b0 :
474                           // .. is idle when the FSM is in the Idle state
475                           (st_q == StIdle) ? 1'b1 :
476                           // .. is idle when it has processed a complete block of a message and is told to stop in any
477                           // FSM state
478                           (txcnt_eq_blksz && reg_hash_stop_d) ? 1'b1 :
479                           // .. and keeps the current idle state in all other cases.
480                           idle_q;
481                     
482        1/1            assign idle_o = idle_d;
           Tests:       T1 T2 T3 
483                     
484                       always_ff @(posedge clk_i or negedge rst_ni) begin
485        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
486        1/1                idle_q <= 1'b1;
           Tests:       T1 T2 T3 
487                         end else begin
488        1/1                idle_q <= idle_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_hmac

	Total	Covered	Percent
Conditions	208	200	96.15
Logical	208	200	96.15
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (hmac_en_i ? hash_start : reg_hash_start_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       121
 EXPRESSION (hmac_en_i ? hash_continue : reg_hash_continue_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION (hmac_en_i ? (reg_hash_process_i | hash_process) : reg_hash_process_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       123
 SUB-EXPRESSION (reg_hash_process_i | hash_process)
                 ---------1--------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       124
 EXPRESSION (hmac_en_i ? hmac_hash_done : sha_hash_done_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       189
 EXPRESSION (hmac_en_i ? ((st_q == StMsg) & sha_rready_i) : sha_rready_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       189
 SUB-EXPRESSION ((st_q == StMsg) & sha_rready_i)
                 -------1-------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       189
 SUB-EXPRESSION (st_q == StMsg)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       191
 EXPRESSION (((!hmac_en_i)) ? fifo_rvalid_i : hmac_sha_rvalid)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION 
 Number  Term
      1  ((!hmac_en_i)) ? fifo_rdata_i : (((sel_rdata == SelIPad) && (digest_size_i == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && (digest_size_i == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T19

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelIPad) && (digest_size_i == SHA2_256))
                 -----------1----------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T4,T6,T19

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       192
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                 -----------1----------    ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T4

 LINE       192
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T19

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelOPad) && (digest_size_i == SHA2_256))
                 -----------1----------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T4,T6,T19

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       192
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                 -----------1----------    ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T4

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))
                 -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelFifo)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION (sel_msglen == SelIPadMsg)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       214
 EXPRESSION (digest_size_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       216
 EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
             -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T4

 LINE       216
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       216
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T4

 LINE       219
 EXPRESSION (sel_msglen == SelOPadMsg)
            -------------1------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T2,T4

 LINE       221
 EXPRESSION (digest_size_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T6,T19

 LINE       223
 EXPRESSION (digest_size_i == SHA2_384)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T18
1	Covered	T2,T4,T18

 LINE       225
 EXPRESSION (digest_size_i == SHA2_512)
            -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T4,T18

 LINE       238
 EXPRESSION ((txcount[(BlockSizeBitsSHA256 - 1):0] == '0) && (txcount != '0))
             ----------------------1---------------------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T4

 LINE       238
 SUB-EXPRESSION (txcount[(BlockSizeBitsSHA256 - 1):0] == '0)
                ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       238
 SUB-EXPRESSION (txcount != '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T4

 LINE       239
 EXPRESSION ((txcount[(BlockSizeBitsSHA512 - 1):0] == '0) && (txcount != '0))
             ----------------------1---------------------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T18
1	1	Covered	T1,T2,T4

 LINE       239
 SUB-EXPRESSION (txcount[(BlockSizeBitsSHA512 - 1):0] == '0)
                ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       239
 SUB-EXPRESSION (txcount != '0)
                -------1-------

-1-	Status	Tests
0	Covered	T2,T4,T18
1	Covered	T1,T2,T4

 LINE       240
 EXPRESSION ((txcount[(BlockSizeBitsSHA512 - 1):0] == '0) && (txcount != '0))
             ----------------------1---------------------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T5

 LINE       240
 SUB-EXPRESSION (txcount[(BlockSizeBitsSHA512 - 1):0] == '0)
                ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T4

 LINE       240
 SUB-EXPRESSION (txcount != '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T4

 LINE       245
 EXPRESSION (sha_rready_i && sha_rvalid_o)
             ------1-----    ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T4
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T4

 LINE       281
 EXPRESSION (hmac_hash_done || reg_hash_start_i || reg_hash_continue_i)
             -------1------    --------2-------    ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T5
0	1	0	Covered	T1,T2,T4
1	0	0	Covered	T1,T2,T4

 LINE       299
 EXPRESSION (fifo_wsel_o && fifo_wvalid_o)
             -----1-----    ------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T4

 LINE       304
 EXPRESSION ((round_q == Inner) ? SelIPadMsg : SelOPadMsg)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       304
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       334
 EXPRESSION (hmac_en_i && reg_hash_start_i)
             ----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       339
 EXPRESSION (hmac_en_i && reg_hash_continue_i)
             ----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       365
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       367
 EXPRESSION ((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length_o))
             ----------------------------------1----------------------------------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       367
 SUB-EXPRESSION (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
                 ----------------------1----------------------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       367
 SUB-EXPRESSION ((round_q == Inner) && reg_hash_process_flag)
                 ---------1--------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       367
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       367
 SUB-EXPRESSION (round_q == Outer)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       372
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       373
 EXPRESSION (txcnt_eq_blksz && (txcount >= sha_message_length_o) && reg_hash_stop_q && (round_q == Inner))
             -------1------    ----------------2----------------    -------3-------    ---------4--------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Not Covered
1	0	1	1	Covered	T52,T53,T54
1	1	0	1	Covered	T2,T4,T6
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T7,T8,T9

 LINE       373
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       391
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       411
 EXPRESSION 
 Number  Term
      1  fifo_wready_i && 
      2  (((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) || ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384))))

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       411
 SUB-EXPRESSION 
 Number  Term
      1  ((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || 
      2  ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) || 
      3  ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384)))

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T4
0	0	1	Covered	T2,T4,T18
0	1	0	Covered	T1,T4,T18
1	0	0	Covered	T4,T6,T19

 LINE       411
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256))
                 -------------1------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T19
1	0	Covered	T1,T2,T4
1	1	Covered	T4,T6,T19

 LINE       411
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd7)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       411
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T6,T19

 LINE       411
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T18
1	0	Not Covered
1	1	Covered	T1,T4,T18

 LINE       411
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd15)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T4,T18

 LINE       411
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T4,T18

 LINE       411
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T18
1	0	Covered	T1,T4,T18
1	1	Covered	T2,T4,T18

 LINE       411
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd11)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       411
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T2,T4,T18

 LINE       458
 EXPRESSION ((reg_hash_stop_i == 1'b1) ? 1'b1 : (((sha_hash_done_i == 1'b1) && (reg_hash_stop_q == 1'b1)) ? 1'b0 : reg_hash_stop_q))
             ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       458
 SUB-EXPRESSION (reg_hash_stop_i == 1'b1)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       458
 SUB-EXPRESSION (((sha_hash_done_i == 1'b1) && (reg_hash_stop_q == 1'b1)) ? 1'b0 : reg_hash_stop_q)
                 ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       458
 SUB-EXPRESSION ((sha_hash_done_i == 1'b1) && (reg_hash_stop_q == 1'b1))
                 ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       458
 SUB-EXPRESSION (sha_hash_done_i == 1'b1)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       458
 SUB-EXPRESSION (reg_hash_stop_q == 1'b1)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       471
 EXPRESSION ((reg_hash_start_i || reg_hash_continue_i) ? 1'b0 : ((st_q == StIdle) ? 1'b1 : ((txcnt_eq_blksz && reg_hash_stop_d) ? 1'b1 : idle_q)))
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       471
 SUB-EXPRESSION (reg_hash_start_i || reg_hash_continue_i)
                 --------1-------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T4

 LINE       471
 SUB-EXPRESSION ((st_q == StIdle) ? 1'b1 : ((txcnt_eq_blksz && reg_hash_stop_d) ? 1'b1 : idle_q))
                 --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       471
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       471
 SUB-EXPRESSION ((txcnt_eq_blksz && reg_hash_stop_d) ? 1'b1 : idle_q)
                 -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T7,T8,T9

 LINE       471
 SUB-EXPRESSION (txcnt_eq_blksz && reg_hash_stop_d)
                 -------1------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T8,T24,T55
1	0	Covered	T1,T2,T4
1	1	Covered	T7,T8,T9

---

FSM Coverage for Instance : tb.dut.u_hmac

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	9	9	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StDone	392	Covered	T1,T2,T4
StIPad	335	Covered	T1,T2,T4
StIdle	345	Covered	T1,T2,T3
StMsg	340	Covered	T1,T2,T4
StOPad	415	Covered	T1,T2,T4
StPushToMsgFifo	397	Covered	T1,T2,T4
StWaitResp	369	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
StDone->StIdle	444	Covered	T1,T2,T4
StIPad->StMsg	353	Covered	T1,T2,T4
StIdle->StIPad	335	Covered	T1,T2,T4
StIdle->StMsg	340	Covered	T7,T8,T9
StMsg->StWaitResp	369	Covered	T1,T2,T4
StOPad->StMsg	432	Covered	T1,T2,T4
StPushToMsgFifo->StOPad	415	Covered	T1,T2,T4
StWaitResp->StDone	392	Covered	T1,T2,T4
StWaitResp->StPushToMsgFifo	397	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_hmac

	Line No.	Total	Covered	Percent
Branches		87	85	97.70
TERNARY	120	2	2	100.00
TERNARY	121	2	2	100.00
TERNARY	123	2	2	100.00
TERNARY	124	2	2	100.00
TERNARY	189	2	2	100.00
TERNARY	191	2	2	100.00
TERNARY	192	7	6	85.71
TERNARY	304	2	2	100.00
TERNARY	458	3	3	100.00
TERNARY	471	4	4	100.00
CASE	137	6	6	100.00
IF	209	8	7	87.50
CASE	237	4	4	100.00
IF	254	6	6	100.00
IF	271	2	2	100.00
IF	277	4	4	100.00
IF	287	3	3	100.00
IF	295	3	3	100.00
IF	307	2	2	100.00
CASE	327	17	17	100.00
IF	463	2	2	100.00
IF	485	2	2	100.00

120          assign sha_hash_start_o    = (hmac_en_i) ? hash_start    : reg_hash_start_i;
                                                      -1-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

121          assign sha_hash_continue_o = (hmac_en_i) ? hash_continue : reg_hash_continue_i;
                                                      -1-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

123          assign sha_hash_process_o  = (hmac_en_i) ? reg_hash_process_i | hash_process : reg_hash_process_i;
                                                      -1-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

124          assign hash_done_o         = (hmac_en_i) ? hmac_hash_done                    : sha_hash_done_i;
                                                      -1-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

189          assign fifo_rready_o = (hmac_en_i) ? (st_q == StMsg) & sha_rready_i : sha_rready_i ;
                                                -1-  
                                                ==>  
                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

191          assign sha_rvalid_o  = (!hmac_en_i) ? fifo_rvalid_i : hmac_sha_rvalid ;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

192          assign sha_rdata_o =
                                 
193            (!hmac_en_i)    ? fifo_rdata_i                                                             :
                               -1-  
                               ==>  
194            (sel_rdata == SelIPad && digest_size_i == SHA2_256)
                                                                  
195                          ? '{data: i_pad_256[(BlockSizeSHA256-1)-32*pad_index_256-:32], mask: '1} :
                             -2-  
                             ==>  
196            (sel_rdata == SelIPad && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                                                                                                     
197                          ? '{data: i_pad_512[(BlockSizeSHA512-1)-32*pad_index_512-:32], mask: '1} :
                             -3-  
                             ==>  
198            (sel_rdata == SelOPad && digest_size_i == SHA2_256)
                                                                  
199                          ? '{data: o_pad_256[(BlockSizeSHA256-1)-32*pad_index_256-:32], mask: '1} :
                             -4-  
                             ==>  
200            (sel_rdata == SelOPad && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                                                                                                     
201                          ? '{data: o_pad_512[(BlockSizeSHA512-1)-32*pad_index_512-:32], mask: '1} :
                             -5-  
                             ==>  
202            (sel_rdata == SelFifo) ? fifo_rdata_i                                                    :
                                      -6-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T4,T6,T19
0	0	1	-	-	-	Covered	T1,T2,T4
0	0	0	1	-	-	Covered	T4,T6,T19
0	0	0	0	1	-	Covered	T1,T2,T4
0	0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	0	Not Covered

304          assign sel_msglen = (round_q == Inner) ? SelIPadMsg : SelOPadMsg ;
                                                    -1-  
                                                    ==>  
                                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

458          assign reg_hash_stop_d = (reg_hash_stop_i == 1'b1)                            ? 1'b1 :
                                                                                           -1-  
                                                                                           ==>  
459                                   (sha_hash_done_i == 1'b1 && reg_hash_stop_q == 1'b1) ? 1'b0 :
                                                                                           -2-  
                                                                                           ==>  
                                                                                           ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

471          assign idle_d =
                            
472              // .. is not idle when told to start or continue
                                                                 
473              (reg_hash_start_i || reg_hash_continue_i) ? 1'b0 :
                                                           -1-  
                                                           ==>  
474              // .. is idle when the FSM is in the Idle state
                                                                
475              (st_q == StIdle) ? 1'b1 :
                                  -2-  
                                  ==>  
476              // .. is idle when it has processed a complete block of a message and is told to stop in any
                                                                                                             
477              // FSM state
                             
478              (txcnt_eq_blksz && reg_hash_stop_d) ? 1'b1 :
                                                     -3-  
                                                     ==>  
                                                     ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T4
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T4

137            unique case (key_length_i)
                      -1-  
138              Key_128: begin
139                i_pad_256 = {secret_key_i[1023:896],
                   ==>
140                            {(BlockSizeSHA256-128){1'b0}}} ^ {(BlockSizeSHA256/8){8'h36}};
141                i_pad_512 = {secret_key_i[1023:896],
142                            {(BlockSizeSHA512-128){1'b0}}} ^ {(BlockSizeSHA512/8){8'h36}};
143                o_pad_256 = {secret_key_i[1023:896],
144                            {(BlockSizeSHA256-128){1'b0}}} ^ {(BlockSizeSHA256/8){8'h5c}};
145                o_pad_512 = {secret_key_i[1023:896],
146                            {(BlockSizeSHA512-128){1'b0}}} ^ {(BlockSizeSHA512/8){8'h5c}};
147              end
148              Key_256: begin
149                i_pad_256 = {secret_key_i[1023:768],
                   ==>
150                            {(BlockSizeSHA256-256){1'b0}}} ^ {(BlockSizeSHA256/8){8'h36}};
151                i_pad_512 = {secret_key_i[1023:768],
152                            {(BlockSizeSHA512-256){1'b0}}} ^ {(BlockSizeSHA512/8){8'h36}};
153                o_pad_256 = {secret_key_i[1023:768],
154                            {(BlockSizeSHA256-256){1'b0}}} ^ {(BlockSizeSHA256/8){8'h5c}};
155                o_pad_512 = {secret_key_i[1023:768],
156                            {(BlockSizeSHA512-256){1'b0}}} ^ {(BlockSizeSHA512/8){8'h5c}};
157              end
158              Key_384: begin
159                i_pad_256 = {secret_key_i[1023:640],
                   ==>
160                            {(BlockSizeSHA256-384){1'b0}}} ^ {(BlockSizeSHA256/8){8'h36}};
161                i_pad_512 = {secret_key_i[1023:640],
162                            {(BlockSizeSHA512-384){1'b0}}} ^ {(BlockSizeSHA512/8){8'h36}};
163                o_pad_256 = {secret_key_i[1023:640],
164                            {(BlockSizeSHA256-384){1'b0}}} ^ {(BlockSizeSHA256/8){8'h5c}};
165                o_pad_512 = {secret_key_i[1023:640],
166                            {(BlockSizeSHA512-384){1'b0}}} ^ {(BlockSizeSHA512/8){8'h5c}};
167              end
168              Key_512: begin
169                i_pad_256 = secret_key_i[1023:512] ^ {(BlockSizeSHA256/8){8'h36}};
                   ==>
170                i_pad_512 = {secret_key_i[1023:512],
171                            {(BlockSizeSHA512-512){1'b0}}} ^ {(BlockSizeSHA512/8){8'h36}};
172                o_pad_256 = secret_key_i[1023:512] ^ {(BlockSizeSHA256/8){8'h5c}};
173                o_pad_512 = {secret_key_i[1023:512],
174                            {(BlockSizeSHA512-512){1'b0}}} ^ {(BlockSizeSHA512/8){8'h5c}};
175              end
176              Key_1024: begin // not allowed to be configured for SHA-2 256
177                // zero out for SHA-2 256
178                i_pad_256 = '{default: '0};
                   ==>
179                i_pad_512 = secret_key_i[1023:0]   ^ {(BlockSizeSHA512/8){8'h36}};
180                // zero out for SHA-2 256
181                o_pad_256 = '{default: '0};
182                o_pad_512 = secret_key_i[1023:0]   ^ {(BlockSizeSHA512/8){8'h5c}};
183              end
184              default: begin
                 ==>

Branches:

-1-	Status	Tests
Key_128	Covered	T1,T2,T4
Key_256	Covered	T1,T2,T4
Key_384	Covered	T1,T2,T4
Key_512	Covered	T1,T4,T6
Key_1024	Covered	T1,T2,T4
default	Covered	T1,T2,T3

209            if (!hmac_en_i) begin
               -1-  
210              sha_msg_len = message_length_i;
                 ==>
211            // HASH = (o_pad || HASH_INTERMEDIATE (i_pad || msg))
212            // message length for HASH_INTERMEDIATE = block size (i_pad) + message length
213            end else if (sel_msglen == SelIPadMsg) begin
                        -2-  
214              if (digest_size_i == SHA2_256) begin
                 -3-  
215                sha_msg_len = message_length_i + BlockSizeSHA256in64;
                   ==>
216              end else if ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)) begin
                          -4-  
217                sha_msg_len = message_length_i + BlockSizeSHA512in64;
                   ==>
218              end
                 MISSING_ELSE
                 ==>
219            end else if (sel_msglen == SelOPadMsg) begin
                        -5-  
220            // message length for HASH = block size (o_pad) + HASH_INTERMEDIATE digest length
221              if (digest_size_i == SHA2_256) begin
                 -6-  
222                sha_msg_len = BlockSizeSHA256in64 + 64'd256;
                   ==>
223              end else if (digest_size_i == SHA2_384) begin
                          -7-  
224                sha_msg_len = BlockSizeSHA512in64 + 64'd384;
                   ==>
225              end else if (digest_size_i == SHA2_512) begin
                          -8-  
226                sha_msg_len = BlockSizeSHA512in64 + 64'd512;
                   ==>
227              end
                 MISSING_ELSE
                 ==>
228            end else
229              sha_msg_len = '0;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
1	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	-	-	Covered	T2,T4,T6
0	1	0	1	-	-	-	-	Covered	T1,T2,T3
0	1	0	0	-	-	-	-	Covered	T1,T2,T4
0	0	-	-	1	1	-	-	Covered	T4,T6,T19
0	0	-	-	1	0	1	-	Covered	T2,T4,T18
0	0	-	-	1	0	0	1	Covered	T1,T4,T18
0	0	-	-	1	0	0	0	Not Covered
0	0	-	-	0	-	-	-	Excluded		VC_COV_UNR

237            unique case (digest_size_i)
                      -1-  
238              SHA2_256: txcnt_eq_blksz = (txcount[BlockSizeBitsSHA256-1:0] == '0) && (txcount != '0);
                 ==>
239              SHA2_384: txcnt_eq_blksz = (txcount[BlockSizeBitsSHA512-1:0] == '0) && (txcount != '0);
                 ==>
240              SHA2_512: txcnt_eq_blksz = (txcount[BlockSizeBitsSHA512-1:0] == '0) && (txcount != '0);
                 ==>
241              default;
                 ==>

Branches:

-1-	Status	Tests
SHA2_256	Covered	T1,T2,T4
SHA2_384	Covered	T1,T2,T4
SHA2_512	Covered	T1,T2,T3
default	Covered	T1,T2,T3

254            if (clr_txcount) begin
               -1-  
255              txcount_d = '0;
                 ==>
256            end else if (load_txcount) begin
                        -2-  
257              // When loading, add block size to the message length because the SW-visible message length
258              // does not include the block containing the key xor'ed with the inner pad.
259              unique case (digest_size_i)
                        -3-  
260                SHA2_256: txcount_d = message_length_i + BlockSizeSHA256in64;
                   ==>
261                SHA2_384: txcount_d = message_length_i + BlockSizeSHA512in64;
                   ==>
262                SHA2_512: txcount_d = message_length_i + BlockSizeSHA512in64;
                   ==>
263                default : txcount_d = message_length_i + '0;
                   ==> (Excluded)
Exclude Annotation: VC_COV_UNR
264              endcase
265            end else if (inc_txcount) begin
                        -4-  
266              txcount_d[63:5] = txcount[63:5] + 1'b1; // increment by 32 (data word size)
                 ==>
267            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
1	-	-	-	Covered	T1,T2,T4
0	1	SHA2_256	-	Covered	T8,T9,T50
0	1	SHA2_384	-	Covered	T10,T50,T51
0	1	SHA2_512	-	Covered	T7,T9,T20
0	1	default	-	Excluded		VC_COV_UNR
0	0	-	1	Covered	T1,T2,T4
0	0	-	0	Covered	T1,T2,T3

271            if (!rst_ni) txcount <= '0;
               -1-  
               ==>
272            else         txcount <= txcount_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

277            if (!rst_ni) begin
               -1-  
278              reg_hash_process_flag <= 1'b0;
                 ==>
279            end else if (reg_hash_process_i) begin
                        -2-  
280              reg_hash_process_flag <= 1'b1;
                 ==>
281            end else if (hmac_hash_done || reg_hash_start_i || reg_hash_continue_i) begin
                        -3-  
282              reg_hash_process_flag <= 1'b0;
                 ==>
283            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

287            if (!rst_ni) begin
               -1-  
288              round_q <= Inner;
                 ==>
289            end else if (update_round) begin
                        -2-  
290              round_q <= round_d;
                 ==>
291            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T4

295            if (!rst_ni) begin
               -1-  
296              fifo_wdata_sel_o <= 3'h 0;
                 ==>
297            end else if (clr_fifo_wdata_sel) begin
                        -2-         
298              fifo_wdata_sel_o <= 3'h 0;
                 ==>
299            end else if (fifo_wsel_o && fifo_wvalid_o) begin
                        -3-                    
300              fifo_wdata_sel_o <= fifo_wdata_sel_o + 1'b1; // increment by 1
                 ==>
301            end
               MISSING_ELSE
               ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Excluded		VC_COV_UNR

307            if (!rst_ni) st_q <= StIdle;
               -1-  
               ==>
308            else         st_q <= st_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

327            unique case (st_q)
                      -1-  
328              StIdle: begin
329                // reset round to Inner
330                // we always switch context into inner round since outer round computes once over
331                // single block at the end (outer key pad + inner hash)
332                update_round = 1'b1;
333                round_d      = Inner;
334                if (hmac_en_i && reg_hash_start_i) begin
                   -2-  
335                  st_d = StIPad; // start at StIPad if told to start
                     ==>
336        
337                  clr_txcount  = 1'b1;
338                  hash_start   = 1'b1;
339                end else if (hmac_en_i && reg_hash_continue_i) begin
                            -3-  
340                  st_d = StMsg; // skip StIPad if told to continue - assumed it finished StIPad
                     ==>
341        
342                  load_txcount  = 1'b1;
343                  hash_continue = 1'b1;
344                end else begin
345                  st_d = StIdle;
                     ==>
346                end
347              end
348        
349              StIPad: begin
350                sel_rdata = SelIPad;
351        
352                if (txcnt_eq_blksz) begin
                   -4-  
353                  st_d = StMsg;
                     ==>
354        
355                  hmac_sha_rvalid = 1'b0; // block new read request
356                end else begin
357                  st_d = StIPad;
                     ==>
358        
359                  hmac_sha_rvalid = 1'b1;
360                end
361              end
362        
363              StMsg: begin
364                sel_rdata   = SelFifo;
365                fifo_wsel_o = (round_q == Outer);
366        
367                if ( (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
                   -5-  
368                    && (txcount >= sha_message_length_o)) begin
369                  st_d    = StWaitResp;
                     ==>
370        
371                  hmac_sha_rvalid = 1'b0; // block reading words from MSG FIFO
372                  hash_process    = (round_q == Outer);
373                end else if (txcnt_eq_blksz && (txcount >= sha_message_length_o)
                            -6-  
374                             && reg_hash_stop_q && (round_q == Inner)) begin
375                  // wait till all MSG words are pushed out from FIFO (txcount reaches msg length)
376                  // before transitioning to StWaitResp to wait on sha_hash_done_i and disabling
377                  // reading from MSG FIFO
378                  st_d =  StWaitResp;
                     ==>
379        
380                  hmac_sha_rvalid = 1'b0;
381                end else begin
382                  st_d            = StMsg;
                     ==>
383                  hmac_sha_rvalid = fifo_rvalid_i;
384                end
385              end
386        
387              StWaitResp: begin
388                hmac_sha_rvalid = 1'b0;
389        
390                if (sha_hash_done_i) begin
                   -7-  
391                  if (round_q == Outer) begin
                     -8-  
392                    st_d = StDone;
                       ==>
393                  end else begin // round_q == Inner
394                    if (reg_hash_stop_q) begin
                       -9-  
395                      st_d = StDone;
                         ==>
396                    end else begin
397                      st_d = StPushToMsgFifo;
                         ==>
398                    end
399                  end
400                end else begin
401                  st_d = StWaitResp;
                     ==>
402                end
403              end
404        
405              StPushToMsgFifo: begin
406                hmac_sha_rvalid    = 1'b0;
407                fifo_wsel_o        = 1'b1;
408                fifo_wvalid_o      = 1'b1;
409                clr_fifo_wdata_sel = 1'b0;
410        
411                if (fifo_wready_i && (((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) ||
                   -10-                         
412                                     ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) ||
413                                     ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384)))) begin
414        
415                  st_d = StOPad;
                     ==>
416        
417                  clr_txcount  = 1'b1;
418                  update_round = 1'b1;
419                  round_d      = Outer;
420                  hash_start   = 1'b1;
421                end else begin
422                  st_d = StPushToMsgFifo;
                     ==>
423        
424                end
425              end
426        
427              StOPad: begin
428                sel_rdata   = SelOPad;
429                fifo_wsel_o = 1'b1; // Remained HMAC select to indicate HMAC is in second stage
430        
431                if (txcnt_eq_blksz) begin
                   -11-  
432                  st_d = StMsg;
                     ==>
433        
434                  hmac_sha_rvalid = 1'b0; // block new read request
435                end else begin
436                  st_d = StOPad;
                     ==>
437        
438                  hmac_sha_rvalid = 1'b1;
439                end
440              end
441        
442              StDone: begin
443                // raise interrupt (hash_done)
444                st_d = StIdle;
                   ==>
445        
446                hmac_hash_done = 1'b1;
447              end
448        
449              default: begin
450                st_d = StIdle;
                   ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests	Exclude Annotation
StIdle	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StIdle	0	1	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
StIdle	0	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIPad	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
StIPad	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
StMsg	-	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T4
StMsg	-	-	-	0	1	-	-	-	-	-	Covered	T7,T8,T9
StMsg	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
StWaitResp	-	-	-	-	-	1	1	-	-	-	Covered	T1,T2,T4
StWaitResp	-	-	-	-	-	1	0	1	-	-	Covered	T7,T8,T9
StWaitResp	-	-	-	-	-	1	0	0	-	-	Covered	T1,T2,T4
StWaitResp	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T4
StPushToMsgFifo	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T4
StPushToMsgFifo	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T4
StOPad	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
StOPad	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
StDone	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

463            if (!rst_ni) begin
               -1-  
464              reg_hash_stop_q <= 1'b0;
                 ==>
465            end else begin
466              reg_hash_stop_q <= reg_hash_stop_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

485            if (!rst_ni) begin
               -1-  
486              idle_q <= 1'b1;
                 ==>
487            end else begin
488              idle_q <= idle_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3