Line Coverage for Module :
prim_sha2_pad
| Line No. | Total | Covered | Percent |
TOTAL | | 129 | 124 | 96.12 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
ALWAYS | 81 | 5 | 5 | 100.00 |
ALWAYS | 101 | 23 | 22 | 95.65 |
ALWAYS | 190 | 3 | 3 | 100.00 |
ALWAYS | 196 | 74 | 70 | 94.59 |
ALWAYS | 346 | 10 | 10 | 100.00 |
ALWAYS | 364 | 3 | 3 | 100.00 |
CONT_ASSIGN | 368 | 1 | 1 | 100.00 |
ALWAYS | 373 | 3 | 3 | 100.00 |
CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
47 // to hash.
48 1/1 assign hash_go = hash_start_i | hash_continue_i;
Tests: T1 T2 T3
49
50 // tie off unused inport ports and signals
51 if (!MultimodeEn) begin : gen_tie_unused
52 logic unused_signals;
53 assign unused_signals = ^{message_length_i[127:64]};
54 end
55
56 1/1 assign fifo_partial = MultimodeEn ? ~&fifo_rdata_i.mask :
Tests: T1 T2 T3
57 ~&fifo_rdata_i.mask[3:0];
58
59 // tx_count[8:0] == 'h1c0 --> should send LenHi
60 1/1 assign txcnt_eq_1a0 = (digest_mode_flag_q == SHA2_256 || ~MultimodeEn) ?
Tests: T1 T2 T3
61 (tx_count[8:0] == 9'h1a0) :
62 ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
63 (tx_count[9:0] == 10'h340) :
64 '0;
65
66 if (MultimodeEn) begin : gen_txcnt_comp_multimode
67 1/1 assign txcnt_eq_msg_len = (tx_count == message_length_i);
Tests: T1 T2 T3
68 end else begin : gen_txcnt_comp_no_multimode
69 assign txcnt_eq_msg_len = (tx_count[63:0] == message_length_i[63:0]);
70 end
71
72 1/1 assign hash_stop_flag_d = (~sha_en_i || hash_go || hash_done_i) ? 1'b0 :
Tests: T1 T2 T3
73 hash_stop_i ? 1'b1 :
74 hash_stop_flag_q;
75
76 1/1 assign hash_process_flag_d = (~sha_en_i || hash_go || hash_done_i) ? 1'b0 :
Tests: T1 T2 T3
77 hash_process_i ? 1'b1 :
78 hash_process_flag_q;
79
80 always_ff @(posedge clk_i or negedge rst_ni) begin
81 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
82 1/1 hash_stop_flag_q <= 1'b0;
Tests: T1 T2 T3
83 1/1 hash_process_flag_q <= 1'b0;
Tests: T1 T2 T3
84 end else begin
85 1/1 hash_stop_flag_q <= hash_stop_flag_d;
Tests: T1 T2 T3
86 1/1 hash_process_flag_q <= hash_process_flag_d;
Tests: T1 T2 T3
87 end
88 end
89
90 // data path: fout_wdata
91 typedef enum logic [2:0] {
92 FifoIn, // fin_wdata, fin_wstrb
93 Pad80, // {8'h80, 8'h00} , strb (calc based on len[4:3])
94 Pad00, // 32'h0, full strb
95 LenHi, // len[63:32], full strb
96 LenLo // len[31:0], full strb
97 } sel_data_e;
98 sel_data_e sel_data;
99
100 always_comb begin
101 1/1 unique case (sel_data)
Tests: T1 T2 T3
102 FifoIn: begin
103 1/1 shaf_rdata_o = fifo_rdata_i.data;
Tests: T1 T2 T3
104 end
105
106 Pad80: begin
107 // {a[7:0], b[7:0], c[7:0], d[7:0]}
108 // msglen[4:3] == 00 |-> {'h80, 'h00, 'h00, 'h00}
109 // msglen[4:3] == 01 |-> {msg, 'h80, 'h00, 'h00}
110 // msglen[4:3] == 10 |-> {msg[15:0], 'h80, 'h00}
111 // msglen[4:3] == 11 |-> {msg[23:0], 'h80}
112 1/1 if ((digest_mode_flag_q == SHA2_256) || ~MultimodeEn) begin
Tests: T1 T2 T4
113 1/1 unique case (message_length_i[4:3])
Tests: T1 T2 T4
114 1/1 2'b 00: shaf_rdata_o = 64'h 0000_0000_8000_0000;
Tests: T1 T4 T6
115 1/1 2'b 01: shaf_rdata_o = {32'h 0000_0000, fifo_rdata_i.data[31:24], 24'h 8000_00};
Tests: T1 T2 T4
116 1/1 2'b 10: shaf_rdata_o = {32'h 0000_0000, fifo_rdata_i.data[31:16], 16'h 8000};
Tests: T2 T7 T8
117 1/1 2'b 11: shaf_rdata_o = {32'h 0000_0000, fifo_rdata_i.data[31: 8], 8'h 80};
Tests: T1 T4 T6
118 default: shaf_rdata_o = 64'h0;
119 endcase
120 1/1 end else if ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) begin
Tests: T1 T2 T4
121 1/1 unique case (message_length_i[5:3])
Tests: T1 T2 T4
122 1/1 3'b 000: shaf_rdata_o = 64'h 8000_0000_0000_0000;
Tests: T1 T2 T4
123 1/1 3'b 001: shaf_rdata_o = {fifo_rdata_i.data[63:56], 56'h 8000_0000_0000_00};
Tests: T1 T2 T4
124 1/1 3'b 010: shaf_rdata_o = {fifo_rdata_i.data[63:48], 48'h 8000_0000_0000};
Tests: T5 T18 T7
125 1/1 3'b 011: shaf_rdata_o = {fifo_rdata_i.data[63:40], 40'h 8000_0000_00};
Tests: T4 T18 T7
126 1/1 3'b 100: shaf_rdata_o = {fifo_rdata_i.data[63:32], 32'h 8000_0000};
Tests: T7 T8 T20
127 1/1 3'b 101: shaf_rdata_o = {fifo_rdata_i.data[63:24], 24'h 8000_00};
Tests: T2 T4 T6
128 1/1 3'b 110: shaf_rdata_o = {fifo_rdata_i.data[63:16], 16'h 8000};
Tests: T18 T7 T21
129 1/1 3'b 111: shaf_rdata_o = {fifo_rdata_i.data[63:8], 8'h 80};
Tests: T1 T4 T22
130 default: shaf_rdata_o = 64'h0;
131 endcase
132 end else
133 0/1 ==> shaf_rdata_o = '0;
134 end
135
136 Pad00: begin
137 1/1 shaf_rdata_o = '0;
Tests: T1 T2 T4
138 end
139
140 LenHi: begin
141 1/1 shaf_rdata_o = ((digest_mode_flag_q == SHA2_256) || ~MultimodeEn) ?
Tests: T1 T2 T4
142 {32'b0, message_length_i[63:32]}:
143 ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
144 message_length_i[127:64] : '0;
145 end
146
147 LenLo: begin
148 1/1 shaf_rdata_o = ((digest_mode_flag_q == SHA2_256) || ~MultimodeEn) ?
Tests: T1 T2 T4
149 {32'b0, message_length_i[31:0]}:
150 ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
151 message_length_i[63:0]: '0;
152 end
153
154 default: begin
155 shaf_rdata_o = '0;
156 end
157 endcase
158
159 1/1(1 unreachable) if (!MultimodeEn) shaf_rdata_o [63:32] = 32'b0; // assign most sig 32 bits to constant 0
Tests: T1 T2 T3
MISSING_ELSE
160 end
161
162 // Padded length
163 // $ceil(message_length_i + 8 + 64, 512) -> message_length_i [8:0] + 440 and ignore carry
164 //assign length_added = (message_length_i[8:0] + 9'h1b8) ;
165
166 // fifo control
167 // add 8'h 80 , N 8'h00, 64'h message_length_i
168
169 // Steps
170 // 1. `hash_start_i` from CPU (or DMA?)
171 // 2. calculate `padded_length` from `message_length_i`
172 // 3. Check if tx_count == message_length_i, then go to 5
173 // 4. Receiving FIFO input (hand over to fifo output)
174 // 5. Padding bit 1 (8'h80) followed by 8'h00 if needed
175 // 6. Padding with length (high -> low)
176
177 // State Machine
178 typedef enum logic [2:0] {
179 StIdle, // fin_full to prevent unwanted FIFO write
180 StFifoReceive, // Check tx_count == message_length_i
181 StPad80, // 8'h 80 + 8'h 00 X N
182 StPad00,
183 StLenHi,
184 StLenLo
185 } pad_st_e;
186
187 pad_st_e st_q, st_d;
188
189 always_ff @(posedge clk_i or negedge rst_ni) begin
190 2/2 if (!rst_ni) st_q <= StIdle;
Tests: T1 T2 T3 | T1 T2 T3
191 1/1 else st_q <= st_d;
Tests: T1 T2 T3
192 end
193
194 // Next state
195 always_comb begin
196 1/1 shaf_rvalid_o = 1'b0;
Tests: T1 T2 T3
197 1/1 inc_txcount = 1'b0;
Tests: T1 T2 T3
198 1/1 sel_data = FifoIn;
Tests: T1 T2 T3
199 1/1 fifo_rready_o = 1'b0;
Tests: T1 T2 T3
200 1/1 st_d = StIdle;
Tests: T1 T2 T3
201
202 1/1 unique case (st_q)
Tests: T1 T2 T3
203 StIdle: begin
204 1/1 sel_data = FifoIn;
Tests: T1 T2 T3
205 1/1 shaf_rvalid_o = 1'b0;
Tests: T1 T2 T3
206 1/1 if (sha_en_i && hash_go) begin
Tests: T1 T2 T3
207 1/1 inc_txcount = 1'b0;
Tests: T1 T2 T4
208 1/1 st_d = StFifoReceive;
Tests: T1 T2 T4
209 end else begin
210 1/1 st_d = StIdle;
Tests: T1 T2 T3
211 end
212 end
213
214 StFifoReceive: begin
215 1/1 sel_data = FifoIn;
Tests: T1 T2 T4
216 1/1 if (fifo_partial && fifo_rvalid_i) begin
Tests: T1 T2 T4
217 // End of the message (last bit is not word-aligned) , assume hash_process_flag is set
218 1/1 shaf_rvalid_o = 1'b0; // Update entry at StPad80
Tests: T1 T2 T4
219 1/1 inc_txcount = 1'b0;
Tests: T1 T2 T4
220 1/1 fifo_rready_o = 1'b0;
Tests: T1 T2 T4
221 1/1 st_d = StPad80;
Tests: T1 T2 T4
222 1/1 end else if (!hash_process_flag_q) begin
Tests: T1 T2 T4
223 1/1 fifo_rready_o = shaf_rready_i;
Tests: T1 T2 T4
224 1/1 shaf_rvalid_o = fifo_rvalid_i;
Tests: T1 T2 T4
225 1/1 inc_txcount = shaf_rready_i;
Tests: T1 T2 T4
226 1/1 st_d = StFifoReceive;
Tests: T1 T2 T4
227 1/1 end else if (txcnt_eq_msg_len) begin
Tests: T1 T2 T4
228 // already received all msg and was waiting process flag
229 1/1 shaf_rvalid_o = 1'b0;
Tests: T1 T2 T4
230 1/1 inc_txcount = 1'b0;
Tests: T1 T2 T4
231 1/1 fifo_rready_o = 1'b0;
Tests: T1 T2 T4
232 1/1 st_d = StPad80;
Tests: T1 T2 T4
233 end else begin
234 1/1 shaf_rvalid_o = fifo_rvalid_i;
Tests: T1 T5 T6
235 1/1 fifo_rready_o = shaf_rready_i; // 0 always
Tests: T1 T5 T6
236 1/1 inc_txcount = shaf_rready_i; // 0 always
Tests: T1 T5 T6
237 1/1 st_d = StFifoReceive;
Tests: T1 T5 T6
238 end
239
240 1/1 if (txcnt_eq_msg_len && hash_stop_flag_q) begin
Tests: T1 T2 T4
241 1/1 shaf_rvalid_o = 1'b0;
Tests: T2 T4 T5
242 1/1 inc_txcount = 1'b0;
Tests: T2 T4 T5
243 1/1 fifo_rready_o = 1'b0;
Tests: T2 T4 T5
244 1/1 st_d = StIdle;
Tests: T2 T4 T5
245 end
MISSING_ELSE
246 end
247
248 StPad80: begin
249 1/1 sel_data = Pad80;
Tests: T1 T2 T4
250 1/1 shaf_rvalid_o = 1'b1;
Tests: T1 T2 T4
251 1/1 fifo_rready_o = (digest_mode_flag_q == SHA2_256 || ~MultimodeEn) ?
Tests: T1 T2 T4
252 shaf_rready_i && |message_length_i[4:3] :
253 ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
254 shaf_rready_i && |message_length_i[5:3] : '0; // Only when partial
255
256 // exactly 192 bits left, do not need to pad00's
257 1/1 if (shaf_rready_i && txcnt_eq_1a0) begin
Tests: T1 T2 T4
258 1/1 st_d = StLenHi;
Tests: T6 T18 T7
259 1/1 inc_txcount = 1'b1;
Tests: T6 T18 T7
260 // it does not matter if value is < or > than 416 bits. If it's the former, 00 pad until
261 // length field. If >, then the next chunk will contain the length field with appropriate
262 // 0 padding.
263 1/1 end else if (shaf_rready_i && !txcnt_eq_1a0) begin
Tests: T1 T2 T4
264 1/1 st_d = StPad00;
Tests: T1 T2 T4
265 1/1 inc_txcount = 1'b1;
Tests: T1 T2 T4
266 end else begin
267 1/1 st_d = StPad80;
Tests: T1 T4 T19
268 1/1 inc_txcount = 1'b0;
Tests: T1 T4 T19
269 end
270
271 // # Below part is temporal code to speed up the SHA by 16 clocks per chunk
272 // # (80 clk --> 64 clk)
273 // # leaving this as a reference but needs to verify it.
274 //if (shaf_rready_i && !txcnt_eq_1a0) begin
275 // st_d = StPad00;
276 //
277 // inc_txcount = 1'b1;
278 // shaf_rvalid_o = (msg_word_aligned) ? 1'b1 : fifo_rvalid;
279 // fifo_rready = (msg_word_aligned) ? 1'b0 : 1'b1;
280 //end else if (!shaf_rready_i && !txcnt_eq_1a0) begin
281 // st_d = StPad80;
282 //
283 // inc_txcount = 1'b0;
284 // shaf_rvalid_o = (msg_word_aligned) ? 1'b1 : fifo_rvalid;
285 //
286 //end else if (shaf_rready_i && txcnt_eq_1a0) begin
287 // st_d = StLenHi;
288 // inc_txcount = 1'b1;
289 //end else begin
290 // // !shaf_rready_i && txcnt_eq_1a0 , just wait until fifo_rready asserted
291 // st_d = StPad80;
292 // inc_txcount = 1'b0;
293 //end
294 end
295
296 StPad00: begin
297 1/1 sel_data = Pad00;
Tests: T1 T2 T4
298 1/1 shaf_rvalid_o = 1'b1;
Tests: T1 T2 T4
299
300 1/1 if (shaf_rready_i) begin
Tests: T1 T2 T4
301 1/1 inc_txcount = 1'b1;
Tests: T1 T2 T4
302 2/2 if (txcnt_eq_1a0) st_d = StLenHi;
Tests: T1 T2 T4 | T1 T2 T4
303 1/1 else st_d = StPad00;
Tests: T1 T2 T4
304 end else begin
305 1/1 st_d = StPad00;
Tests: T1 T2 T4
306 end
307 end
308
309 StLenHi: begin
310 1/1 sel_data = LenHi;
Tests: T1 T2 T4
311 1/1 shaf_rvalid_o = 1'b1;
Tests: T1 T2 T4
312
313 1/1 if (shaf_rready_i) begin
Tests: T1 T2 T4
314 1/1 st_d = StLenLo;
Tests: T1 T2 T4
315 1/1 inc_txcount = 1'b1;
Tests: T1 T2 T4
316 end else begin
317 0/1 ==> st_d = StLenHi;
318 0/1 ==> inc_txcount = 1'b0;
319 end
320 end
321
322 StLenLo: begin
323 1/1 sel_data = LenLo;
Tests: T1 T2 T4
324 1/1 shaf_rvalid_o = 1'b1;
Tests: T1 T2 T4
325
326 1/1 if (shaf_rready_i) begin
Tests: T1 T2 T4
327 1/1 st_d = StIdle;
Tests: T1 T2 T4
328 1/1 inc_txcount = 1'b1;
Tests: T1 T2 T4
329 end else begin
330 0/1 ==> st_d = StLenLo;
331 0/1 ==> inc_txcount = 1'b0;
332 end
333 end
334
335 default: begin
336 st_d = StIdle;
337 end
338 endcase
339
340 2/2 if (!sha_en_i) st_d = StIdle;
Tests: T1 T2 T3 | T1 T2 T3
341 2/2 else if (hash_go) st_d = StFifoReceive;
Tests: T1 T2 T3 | T1 T2 T4
MISSING_ELSE
342 end
343
344 // tx_count
345 always_comb begin
346 1/1 tx_count_d = tx_count;
Tests: T1 T2 T3
347
348 1/1 if (hash_start_i) begin
Tests: T1 T2 T3
349 // When starting a fresh hash, initialize the data counter to zero.
350 1/1 tx_count_d = '0;
Tests: T1 T2 T4
351 1/1 end else if (hash_continue_i) begin
Tests: T1 T2 T3
352 // When continuing to hash, set the data counter to the current message length.
353 1/1 tx_count_d = message_length_i;
Tests: T2 T4 T5
354 1/1 end else if (inc_txcount) begin
Tests: T1 T2 T3
355 1/1 if ((digest_mode_flag_q == SHA2_256) || !MultimodeEn) begin
Tests: T1 T2 T4
356 1/1 tx_count_d[127:5] = tx_count[127:5] + 1'b1;
Tests: T1 T2 T4
357 1/1 end else if ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) begin
Tests: T1 T2 T4
358 1/1 tx_count_d[127:6] = tx_count[127:6] + 1'b1;
Tests: T1 T2 T4
359 end
==> MISSING_ELSE
360 end
MISSING_ELSE
361 end
362
363 always_ff @(posedge clk_i or negedge rst_ni) begin
364 2/2 if (!rst_ni) tx_count <= '0;
Tests: T1 T2 T3 | T1 T2 T3
365 1/1 else tx_count <= tx_count_d;
Tests: T1 T2 T3
366 end
367
368 1/1 assign digest_mode_flag_d = (hash_start_i || hash_continue_i) ? digest_mode_i : // set config
Tests: T1 T2 T3
369 hash_done_i ? SHA2_None : // clear
370 digest_mode_flag_q; // keep
371
372 always_ff @(posedge clk_i or negedge rst_ni) begin
373 2/2 if (!rst_ni) digest_mode_flag_q <= SHA2_None;
Tests: T1 T2 T3 | T1 T2 T3
374 1/1 else digest_mode_flag_q <= digest_mode_flag_d;
Tests: T1 T2 T3
375 end
376
377 // State machine is in Idle only when it meets tx_count == message length
378 1/1 assign msg_feed_complete_o = (hash_process_flag_q || hash_stop_flag_q) && (st_q == StIdle);
Tests: T1 T2 T3
Cond Coverage for Module :
prim_sha2_pad
| Total | Covered | Percent |
Conditions | 143 | 131 | 91.61 |
Logical | 143 | 131 | 91.61 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 48
EXPRESSION (hash_start_i | hash_continue_i)
------1----- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T5 |
1 | 0 | Covered | T1,T2,T4 |
LINE 60
EXPRESSION
Number Term
1 ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? (tx_count[8:0] == 9'h1a0) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (tx_count[9:0] == 10'h340) : '0))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 60
SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
----------------1--------------- --------2-------
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T3 |
1 | - | Covered | T1,T2,T4 |
LINE 60
SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 60
SUB-EXPRESSION (tx_count[8:0] == 9'h1a0)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 60
SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (tx_count[9:0] == 10'h340) : '0)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 60
SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
----------------1--------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
LINE 60
SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 60
SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 60
SUB-EXPRESSION (tx_count[9:0] == 10'h340)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 67
EXPRESSION (tx_count == message_length_i)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
EXPRESSION ((((~sha_en_i)) || hash_go || hash_done_i) ? 1'b0 : (hash_stop_i ? 1'b1 : hash_stop_flag_q))
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((~sha_en_i)) || hash_go || hash_done_i)
------1------ ---2--- -----3-----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T4 |
0 | 1 | 0 | Covered | T1,T2,T4 |
1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (hash_stop_i ? 1'b1 : hash_stop_flag_q)
-----1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T5 |
LINE 76
EXPRESSION ((((~sha_en_i)) || hash_go || hash_done_i) ? 1'b0 : (hash_process_i ? 1'b1 : hash_process_flag_q))
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 76
SUB-EXPRESSION (((~sha_en_i)) || hash_go || hash_done_i)
------1------ ---2--- -----3-----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T4 |
0 | 1 | 0 | Covered | T1,T2,T4 |
1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 76
SUB-EXPRESSION (hash_process_i ? 1'b1 : hash_process_flag_q)
-------1------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 112
EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
----------------1--------------- --------2-------
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T4 |
1 | - | Covered | T1,T2,T4 |
LINE 112
SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 120
EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
----------------1--------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
LINE 120
SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 120
SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 141
EXPRESSION
Number Term
1 ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? ({32'b0, message_length_i[63:32]}) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[127:64] : '0))
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 141
SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
----------------1--------------- --------2-------
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T4 |
1 | - | Covered | T1,T2,T4 |
LINE 141
SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 141
SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[127:64] : '0)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T4 |
LINE 141
SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
----------------1--------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
LINE 141
SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 141
SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 148
EXPRESSION
Number Term
1 ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? ({32'b0, message_length_i[31:0]}) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[63:0] : '0))
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 148
SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
----------------1--------------- --------2-------
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T4 |
1 | - | Covered | T1,T2,T4 |
LINE 148
SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 148
SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[63:0] : '0)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T4 |
LINE 148
SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
----------------1--------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
LINE 148
SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 148
SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 206
EXPRESSION (sha_en_i && hash_go)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T4 |
LINE 216
EXPRESSION (fifo_partial && fifo_rvalid_i)
------1----- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 240
EXPRESSION (txcnt_eq_msg_len && hash_stop_flag_q)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T8,T23,T24 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T2,T4,T5 |
LINE 251
EXPRESSION
Number Term
1 ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? (shaf_rready_i && ((|message_length_i[4:3]))) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (shaf_rready_i && ((|message_length_i[5:3]))) : '0))
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 251
SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
----------------1--------------- --------2-------
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T4 |
1 | - | Covered | T1,T2,T4 |
LINE 251
SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 251
SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[4:3])))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T9,T21 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T2,T4 |
LINE 251
SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (shaf_rready_i && ((|message_length_i[5:3]))) : '0)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T4 |
LINE 251
SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
----------------1--------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
LINE 251
SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 251
SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 251
SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[5:3])))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 257
EXPRESSION (shaf_rready_i && txcnt_eq_1a0)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T6,T18,T7 |
LINE 263
EXPRESSION (shaf_rready_i && ((!txcnt_eq_1a0)))
------1------ --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T19 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T4 |
LINE 355
EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((!MultimodeEn)))
----------------1--------------- --------2-------
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T4 |
1 | - | Covered | T1,T2,T4 |
LINE 355
SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 357
EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
----------------1--------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
LINE 357
SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 357
SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 368
EXPRESSION ((hash_start_i || hash_continue_i) ? digest_mode_i : (hash_done_i ? SHA2_None : digest_mode_flag_q))
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 368
SUB-EXPRESSION (hash_start_i || hash_continue_i)
------1----- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T5 |
1 | 0 | Covered | T1,T2,T4 |
LINE 368
SUB-EXPRESSION (hash_done_i ? SHA2_None : digest_mode_flag_q)
-----1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 378
EXPRESSION ((hash_process_flag_q || hash_stop_flag_q) && (st_q == StIdle))
--------------------1-------------------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 378
SUB-EXPRESSION (hash_process_flag_q || hash_stop_flag_q)
---------1--------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T5 |
1 | 0 | Covered | T1,T2,T4 |
LINE 378
SUB-EXPRESSION (st_q == StIdle)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
FSM Coverage for Module :
prim_sha2_pad
Summary for FSM :: st_q
| Total | Covered | Percent | |
States |
6 |
6 |
100.00 |
(Not included in score) |
Transitions |
15 |
10 |
66.67 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: st_q
| | | |
StFifoReceive |
208 |
Covered |
T1,T2,T4 |
StIdle |
200 |
Covered |
T1,T2,T3 |
StLenHi |
258 |
Covered |
T1,T2,T4 |
StLenLo |
314 |
Covered |
T1,T2,T4 |
StPad00 |
264 |
Covered |
T1,T2,T4 |
StPad80 |
221 |
Covered |
T1,T2,T4 |
| | | |
StFifoReceive->StIdle |
200 |
Covered |
T2,T4,T5 |
StFifoReceive->StPad80 |
221 |
Covered |
T1,T2,T4 |
StIdle->StFifoReceive |
208 |
Covered |
T1,T2,T4 |
StLenHi->StFifoReceive |
341 |
Not Covered |
|
StLenHi->StIdle |
200 |
Not Covered |
|
StLenHi->StLenLo |
314 |
Covered |
T1,T2,T4 |
StLenLo->StFifoReceive |
341 |
Not Covered |
|
StLenLo->StIdle |
200 |
Covered |
T1,T2,T4 |
StPad00->StFifoReceive |
341 |
Not Covered |
|
StPad00->StIdle |
200 |
Covered |
T10,T25 |
StPad00->StLenHi |
302 |
Covered |
T1,T2,T4 |
StPad80->StFifoReceive |
341 |
Not Covered |
|
StPad80->StIdle |
200 |
Covered |
T11 |
StPad80->StLenHi |
258 |
Covered |
T6,T18,T7 |
StPad80->StPad00 |
264 |
Covered |
T1,T2,T4 |
Branch Coverage for Module :
prim_sha2_pad
| Line No. | Total | Covered | Percent |
Branches |
|
76 |
65 |
85.53 |
TERNARY |
60 |
3 |
3 |
100.00 |
TERNARY |
72 |
3 |
3 |
100.00 |
TERNARY |
76 |
3 |
3 |
100.00 |
TERNARY |
368 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
CASE |
101 |
24 |
18 |
75.00 |
IF |
159 |
1 |
1 |
100.00 |
IF |
190 |
2 |
2 |
100.00 |
CASE |
202 |
22 |
18 |
81.82 |
IF |
340 |
3 |
3 |
100.00 |
IF |
348 |
6 |
5 |
83.33 |
IF |
364 |
2 |
2 |
100.00 |
IF |
373 |
2 |
2 |
100.00 |
60 assign txcnt_eq_1a0 = (digest_mode_flag_q == SHA2_256 || ~MultimodeEn) ?
-1-
==>
61 (tx_count[8:0] == 9'h1a0) :
62 ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
-2-
==>
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
Covered |
T1,T2,T3 |
72 assign hash_stop_flag_d = (~sha_en_i || hash_go || hash_done_i) ? 1'b0 :
-1-
==>
73 hash_stop_i ? 1'b1 :
-2-
==>
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T4,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
76 assign hash_process_flag_d = (~sha_en_i || hash_go || hash_done_i) ? 1'b0 :
-1-
==>
77 hash_process_i ? 1'b1 :
-2-
==>
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
Covered |
T1,T2,T3 |
368 assign digest_mode_flag_d = (hash_start_i || hash_continue_i) ? digest_mode_i : // set config
-1-
==>
369 hash_done_i ? SHA2_None : // clear
-2-
==>
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
Covered |
T1,T2,T3 |
81 if (!rst_ni) begin
-1-
82 hash_stop_flag_q <= 1'b0;
==>
83 hash_process_flag_q <= 1'b0;
84 end else begin
85 hash_stop_flag_q <= hash_stop_flag_d;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
101 unique case (sel_data)
-1-
102 FifoIn: begin
103 shaf_rdata_o = fifo_rdata_i.data;
==>
104 end
105
106 Pad80: begin
107 // {a[7:0], b[7:0], c[7:0], d[7:0]}
108 // msglen[4:3] == 00 |-> {'h80, 'h00, 'h00, 'h00}
109 // msglen[4:3] == 01 |-> {msg, 'h80, 'h00, 'h00}
110 // msglen[4:3] == 10 |-> {msg[15:0], 'h80, 'h00}
111 // msglen[4:3] == 11 |-> {msg[23:0], 'h80}
112 if ((digest_mode_flag_q == SHA2_256) || ~MultimodeEn) begin
-2-
113 unique case (message_length_i[4:3])
-3-
114 2'b 00: shaf_rdata_o = 64'h 0000_0000_8000_0000;
==>
115 2'b 01: shaf_rdata_o = {32'h 0000_0000, fifo_rdata_i.data[31:24], 24'h 8000_00};
==>
116 2'b 10: shaf_rdata_o = {32'h 0000_0000, fifo_rdata_i.data[31:16], 16'h 8000};
==>
117 2'b 11: shaf_rdata_o = {32'h 0000_0000, fifo_rdata_i.data[31: 8], 8'h 80};
==>
118 default: shaf_rdata_o = 64'h0;
==>
119 endcase
120 end else if ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) begin
-4-
121 unique case (message_length_i[5:3])
-5-
122 3'b 000: shaf_rdata_o = 64'h 8000_0000_0000_0000;
==>
123 3'b 001: shaf_rdata_o = {fifo_rdata_i.data[63:56], 56'h 8000_0000_0000_00};
==>
124 3'b 010: shaf_rdata_o = {fifo_rdata_i.data[63:48], 48'h 8000_0000_0000};
==>
125 3'b 011: shaf_rdata_o = {fifo_rdata_i.data[63:40], 40'h 8000_0000_00};
==>
126 3'b 100: shaf_rdata_o = {fifo_rdata_i.data[63:32], 32'h 8000_0000};
==>
127 3'b 101: shaf_rdata_o = {fifo_rdata_i.data[63:24], 24'h 8000_00};
==>
128 3'b 110: shaf_rdata_o = {fifo_rdata_i.data[63:16], 16'h 8000};
==>
129 3'b 111: shaf_rdata_o = {fifo_rdata_i.data[63:8], 8'h 80};
==>
130 default: shaf_rdata_o = 64'h0;
==>
131 endcase
132 end else
133 shaf_rdata_o = '0;
==>
134 end
135
136 Pad00: begin
137 shaf_rdata_o = '0;
==>
138 end
139
140 LenHi: begin
141 shaf_rdata_o = ((digest_mode_flag_q == SHA2_256) || ~MultimodeEn) ?
-6-
==>
142 {32'b0, message_length_i[63:32]}:
143 ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
-7-
==>
==>
144 message_length_i[127:64] : '0;
145 end
146
147 LenLo: begin
148 shaf_rdata_o = ((digest_mode_flag_q == SHA2_256) || ~MultimodeEn) ?
-8-
==>
149 {32'b0, message_length_i[31:0]}:
150 ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
-9-
==>
==>
151 message_length_i[63:0]: '0;
152 end
153
154 default: begin
155 shaf_rdata_o = '0;
==>
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | Status | Tests |
FifoIn |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
Pad80 |
1 |
2'b00 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T4,T6 |
Pad80 |
1 |
2'b01 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
Pad80 |
1 |
2'b10 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T7,T8 |
Pad80 |
1 |
2'b11 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T4,T6 |
Pad80 |
1 |
default |
- |
- |
- |
- |
- |
- |
Not Covered |
|
Pad80 |
0 |
- |
1 |
3'b000 |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
Pad80 |
0 |
- |
1 |
3'b001 |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
Pad80 |
0 |
- |
1 |
3'b010 |
- |
- |
- |
- |
Covered |
T5,T18,T7 |
Pad80 |
0 |
- |
1 |
3'b011 |
- |
- |
- |
- |
Covered |
T4,T18,T7 |
Pad80 |
0 |
- |
1 |
3'b100 |
- |
- |
- |
- |
Covered |
T7,T8,T20 |
Pad80 |
0 |
- |
1 |
3'b101 |
- |
- |
- |
- |
Covered |
T2,T4,T6 |
Pad80 |
0 |
- |
1 |
3'b110 |
- |
- |
- |
- |
Covered |
T18,T7,T21 |
Pad80 |
0 |
- |
1 |
3'b111 |
- |
- |
- |
- |
Covered |
T1,T4,T22 |
Pad80 |
0 |
- |
1 |
default |
- |
- |
- |
- |
Not Covered |
|
Pad80 |
0 |
- |
0 |
- |
- |
- |
- |
- |
Not Covered |
|
Pad00 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
LenHi |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T1,T2,T4 |
LenHi |
- |
- |
- |
- |
0 |
1 |
- |
- |
Covered |
T1,T2,T4 |
LenHi |
- |
- |
- |
- |
0 |
0 |
- |
- |
Not Covered |
|
LenLo |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T1,T2,T4 |
LenLo |
- |
- |
- |
- |
- |
- |
0 |
1 |
Covered |
T1,T2,T4 |
LenLo |
- |
- |
- |
- |
- |
- |
0 |
0 |
Not Covered |
|
default |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
159 if (!MultimodeEn) shaf_rdata_o [63:32] = 32'b0; // assign most sig 32 bits to constant 0
-1-
==> (Unreachable)
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Unreachable |
|
0 |
Covered |
T1,T2,T3 |
190 if (!rst_ni) st_q <= StIdle;
-1-
==>
191 else st_q <= st_d;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
202 unique case (st_q)
-1-
203 StIdle: begin
204 sel_data = FifoIn;
205 shaf_rvalid_o = 1'b0;
206 if (sha_en_i && hash_go) begin
-2-
207 inc_txcount = 1'b0;
==>
208 st_d = StFifoReceive;
209 end else begin
210 st_d = StIdle;
==>
211 end
212 end
213
214 StFifoReceive: begin
215 sel_data = FifoIn;
216 if (fifo_partial && fifo_rvalid_i) begin
-3-
217 // End of the message (last bit is not word-aligned) , assume hash_process_flag is set
218 shaf_rvalid_o = 1'b0; // Update entry at StPad80
==>
219 inc_txcount = 1'b0;
220 fifo_rready_o = 1'b0;
221 st_d = StPad80;
222 end else if (!hash_process_flag_q) begin
-4-
223 fifo_rready_o = shaf_rready_i;
==>
224 shaf_rvalid_o = fifo_rvalid_i;
225 inc_txcount = shaf_rready_i;
226 st_d = StFifoReceive;
227 end else if (txcnt_eq_msg_len) begin
-5-
228 // already received all msg and was waiting process flag
229 shaf_rvalid_o = 1'b0;
==>
230 inc_txcount = 1'b0;
231 fifo_rready_o = 1'b0;
232 st_d = StPad80;
233 end else begin
234 shaf_rvalid_o = fifo_rvalid_i;
==>
235 fifo_rready_o = shaf_rready_i; // 0 always
236 inc_txcount = shaf_rready_i; // 0 always
237 st_d = StFifoReceive;
238 end
239
240 if (txcnt_eq_msg_len && hash_stop_flag_q) begin
-6-
241 shaf_rvalid_o = 1'b0;
==>
242 inc_txcount = 1'b0;
243 fifo_rready_o = 1'b0;
244 st_d = StIdle;
245 end
MISSING_ELSE
==>
246 end
247
248 StPad80: begin
249 sel_data = Pad80;
250 shaf_rvalid_o = 1'b1;
251 fifo_rready_o = (digest_mode_flag_q == SHA2_256 || ~MultimodeEn) ?
-7-
==>
252 shaf_rready_i && |message_length_i[4:3] :
253 ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
-8-
==>
==>
254 shaf_rready_i && |message_length_i[5:3] : '0; // Only when partial
255
256 // exactly 192 bits left, do not need to pad00's
257 if (shaf_rready_i && txcnt_eq_1a0) begin
-9-
258 st_d = StLenHi;
==>
259 inc_txcount = 1'b1;
260 // it does not matter if value is < or > than 416 bits. If it's the former, 00 pad until
261 // length field. If >, then the next chunk will contain the length field with appropriate
262 // 0 padding.
263 end else if (shaf_rready_i && !txcnt_eq_1a0) begin
-10-
264 st_d = StPad00;
==>
265 inc_txcount = 1'b1;
266 end else begin
267 st_d = StPad80;
==>
268 inc_txcount = 1'b0;
269 end
270
271 // # Below part is temporal code to speed up the SHA by 16 clocks per chunk
272 // # (80 clk --> 64 clk)
273 // # leaving this as a reference but needs to verify it.
274 //if (shaf_rready_i && !txcnt_eq_1a0) begin
275 // st_d = StPad00;
276 //
277 // inc_txcount = 1'b1;
278 // shaf_rvalid_o = (msg_word_aligned) ? 1'b1 : fifo_rvalid;
279 // fifo_rready = (msg_word_aligned) ? 1'b0 : 1'b1;
280 //end else if (!shaf_rready_i && !txcnt_eq_1a0) begin
281 // st_d = StPad80;
282 //
283 // inc_txcount = 1'b0;
284 // shaf_rvalid_o = (msg_word_aligned) ? 1'b1 : fifo_rvalid;
285 //
286 //end else if (shaf_rready_i && txcnt_eq_1a0) begin
287 // st_d = StLenHi;
288 // inc_txcount = 1'b1;
289 //end else begin
290 // // !shaf_rready_i && txcnt_eq_1a0 , just wait until fifo_rready asserted
291 // st_d = StPad80;
292 // inc_txcount = 1'b0;
293 //end
294 end
295
296 StPad00: begin
297 sel_data = Pad00;
298 shaf_rvalid_o = 1'b1;
299
300 if (shaf_rready_i) begin
-11-
301 inc_txcount = 1'b1;
302 if (txcnt_eq_1a0) st_d = StLenHi;
-12-
==>
303 else st_d = StPad00;
==>
304 end else begin
305 st_d = StPad00;
==>
306 end
307 end
308
309 StLenHi: begin
310 sel_data = LenHi;
311 shaf_rvalid_o = 1'b1;
312
313 if (shaf_rready_i) begin
-13-
314 st_d = StLenLo;
==>
315 inc_txcount = 1'b1;
316 end else begin
317 st_d = StLenHi;
==>
318 inc_txcount = 1'b0;
319 end
320 end
321
322 StLenLo: begin
323 sel_data = LenLo;
324 shaf_rvalid_o = 1'b1;
325
326 if (shaf_rready_i) begin
-14-
327 st_d = StIdle;
==>
328 inc_txcount = 1'b1;
329 end else begin
330 st_d = StLenLo;
==>
331 inc_txcount = 1'b0;
332 end
333 end
334
335 default: begin
336 st_d = StIdle;
==>
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | Status | Tests |
StIdle |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
StIdle |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StFifoReceive |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
StFifoReceive |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
StFifoReceive |
- |
0 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
StFifoReceive |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T5,T6 |
StFifoReceive |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
StFifoReceive |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
StPad80 |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
StPad80 |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
StPad80 |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
Not Covered |
|
StPad80 |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T6,T18,T7 |
StPad80 |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
StPad80 |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T1,T4,T19 |
StPad00 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
Covered |
T1,T2,T4 |
StPad00 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
Covered |
T1,T2,T4 |
StPad00 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T1,T2,T4 |
StLenHi |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T1,T2,T4 |
StLenHi |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
Not Covered |
|
StLenLo |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T4 |
StLenLo |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Not Covered |
|
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
340 if (!sha_en_i) st_d = StIdle;
-1-
==>
341 else if (hash_go) st_d = StFifoReceive;
-2-
==>
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
Covered |
T1,T2,T3 |
348 if (hash_start_i) begin
-1-
349 // When starting a fresh hash, initialize the data counter to zero.
350 tx_count_d = '0;
==>
351 end else if (hash_continue_i) begin
-2-
352 // When continuing to hash, set the data counter to the current message length.
353 tx_count_d = message_length_i;
==>
354 end else if (inc_txcount) begin
-3-
355 if ((digest_mode_flag_q == SHA2_256) || !MultimodeEn) begin
-4-
356 tx_count_d[127:5] = tx_count[127:5] + 1'b1;
==>
357 end else if ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) begin
-5-
358 tx_count_d[127:6] = tx_count[127:6] + 1'b1;
==>
359 end
MISSING_ELSE
==>
360 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
0 |
1 |
- |
- |
- |
Covered |
T2,T4,T5 |
0 |
0 |
1 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
0 |
0 |
Not Covered |
|
0 |
0 |
0 |
- |
- |
Covered |
T1,T2,T3 |
364 if (!rst_ni) tx_count <= '0;
-1-
==>
365 else tx_count <= tx_count_d;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
373 if (!rst_ni) digest_mode_flag_q <= SHA2_None;
-1-
==>
374 else digest_mode_flag_q <= digest_mode_flag_d;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode.u_pad
| Line No. | Total | Covered | Percent |
TOTAL | | 129 | 124 | 96.12 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
ALWAYS | 81 | 5 | 5 | 100.00 |
ALWAYS | 101 | 23 | 22 | 95.65 |
ALWAYS | 190 | 3 | 3 | 100.00 |
ALWAYS | 196 | 74 | 70 | 94.59 |
ALWAYS | 346 | 10 | 10 | 100.00 |
ALWAYS | 364 | 3 | 3 | 100.00 |
CONT_ASSIGN | 368 | 1 | 1 | 100.00 |
ALWAYS | 373 | 3 | 3 | 100.00 |
CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
47 // to hash.
48 1/1 assign hash_go = hash_start_i | hash_continue_i;
Tests: T1 T2 T3
49
50 // tie off unused inport ports and signals
51 if (!MultimodeEn) begin : gen_tie_unused
52 logic unused_signals;
53 assign unused_signals = ^{message_length_i[127:64]};
54 end
55
56 1/1 assign fifo_partial = MultimodeEn ? ~&fifo_rdata_i.mask :
Tests: T1 T2 T3
57 ~&fifo_rdata_i.mask[3:0];
58
59 // tx_count[8:0] == 'h1c0 --> should send LenHi
60 1/1 assign txcnt_eq_1a0 = (digest_mode_flag_q == SHA2_256 || ~MultimodeEn) ?
Tests: T1 T2 T3
61 (tx_count[8:0] == 9'h1a0) :
62 ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
63 (tx_count[9:0] == 10'h340) :
64 '0;
65
66 if (MultimodeEn) begin : gen_txcnt_comp_multimode
67 1/1 assign txcnt_eq_msg_len = (tx_count == message_length_i);
Tests: T1 T2 T3
68 end else begin : gen_txcnt_comp_no_multimode
69 assign txcnt_eq_msg_len = (tx_count[63:0] == message_length_i[63:0]);
70 end
71
72 1/1 assign hash_stop_flag_d = (~sha_en_i || hash_go || hash_done_i) ? 1'b0 :
Tests: T1 T2 T3
73 hash_stop_i ? 1'b1 :
74 hash_stop_flag_q;
75
76 1/1 assign hash_process_flag_d = (~sha_en_i || hash_go || hash_done_i) ? 1'b0 :
Tests: T1 T2 T3
77 hash_process_i ? 1'b1 :
78 hash_process_flag_q;
79
80 always_ff @(posedge clk_i or negedge rst_ni) begin
81 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
82 1/1 hash_stop_flag_q <= 1'b0;
Tests: T1 T2 T3
83 1/1 hash_process_flag_q <= 1'b0;
Tests: T1 T2 T3
84 end else begin
85 1/1 hash_stop_flag_q <= hash_stop_flag_d;
Tests: T1 T2 T3
86 1/1 hash_process_flag_q <= hash_process_flag_d;
Tests: T1 T2 T3
87 end
88 end
89
90 // data path: fout_wdata
91 typedef enum logic [2:0] {
92 FifoIn, // fin_wdata, fin_wstrb
93 Pad80, // {8'h80, 8'h00} , strb (calc based on len[4:3])
94 Pad00, // 32'h0, full strb
95 LenHi, // len[63:32], full strb
96 LenLo // len[31:0], full strb
97 } sel_data_e;
98 sel_data_e sel_data;
99
100 always_comb begin
101 1/1 unique case (sel_data)
Tests: T1 T2 T3
102 FifoIn: begin
103 1/1 shaf_rdata_o = fifo_rdata_i.data;
Tests: T1 T2 T3
104 end
105
106 Pad80: begin
107 // {a[7:0], b[7:0], c[7:0], d[7:0]}
108 // msglen[4:3] == 00 |-> {'h80, 'h00, 'h00, 'h00}
109 // msglen[4:3] == 01 |-> {msg, 'h80, 'h00, 'h00}
110 // msglen[4:3] == 10 |-> {msg[15:0], 'h80, 'h00}
111 // msglen[4:3] == 11 |-> {msg[23:0], 'h80}
112 1/1 if ((digest_mode_flag_q == SHA2_256) || ~MultimodeEn) begin
Tests: T1 T2 T4
113 1/1 unique case (message_length_i[4:3])
Tests: T1 T2 T4
114 1/1 2'b 00: shaf_rdata_o = 64'h 0000_0000_8000_0000;
Tests: T1 T4 T6
115 1/1 2'b 01: shaf_rdata_o = {32'h 0000_0000, fifo_rdata_i.data[31:24], 24'h 8000_00};
Tests: T1 T2 T4
116 1/1 2'b 10: shaf_rdata_o = {32'h 0000_0000, fifo_rdata_i.data[31:16], 16'h 8000};
Tests: T2 T7 T8
117 1/1 2'b 11: shaf_rdata_o = {32'h 0000_0000, fifo_rdata_i.data[31: 8], 8'h 80};
Tests: T1 T4 T6
118 default: shaf_rdata_o = 64'h0;
Exclude Annotation: VC_COV_UNR
119 endcase
120 1/1 end else if ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) begin
Tests: T1 T2 T4
121 1/1 unique case (message_length_i[5:3])
Tests: T1 T2 T4
122 1/1 3'b 000: shaf_rdata_o = 64'h 8000_0000_0000_0000;
Tests: T1 T2 T4
123 1/1 3'b 001: shaf_rdata_o = {fifo_rdata_i.data[63:56], 56'h 8000_0000_0000_00};
Tests: T1 T2 T4
124 1/1 3'b 010: shaf_rdata_o = {fifo_rdata_i.data[63:48], 48'h 8000_0000_0000};
Tests: T5 T18 T7
125 1/1 3'b 011: shaf_rdata_o = {fifo_rdata_i.data[63:40], 40'h 8000_0000_00};
Tests: T4 T18 T7
126 1/1 3'b 100: shaf_rdata_o = {fifo_rdata_i.data[63:32], 32'h 8000_0000};
Tests: T7 T8 T20
127 1/1 3'b 101: shaf_rdata_o = {fifo_rdata_i.data[63:24], 24'h 8000_00};
Tests: T2 T4 T6
128 1/1 3'b 110: shaf_rdata_o = {fifo_rdata_i.data[63:16], 16'h 8000};
Tests: T18 T7 T21
129 1/1 3'b 111: shaf_rdata_o = {fifo_rdata_i.data[63:8], 8'h 80};
Tests: T1 T4 T22
130 default: shaf_rdata_o = 64'h0;
Exclude Annotation: VC_COV_UNR
131 endcase
132 end else
133 0/1 ==> shaf_rdata_o = '0;
134 end
135
136 Pad00: begin
137 1/1 shaf_rdata_o = '0;
Tests: T1 T2 T4
138 end
139
140 LenHi: begin
141 1/1 shaf_rdata_o = ((digest_mode_flag_q == SHA2_256) || ~MultimodeEn) ?
Tests: T1 T2 T4
142 {32'b0, message_length_i[63:32]}:
143 ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
144 message_length_i[127:64] : '0;
145 end
146
147 LenLo: begin
148 1/1 shaf_rdata_o = ((digest_mode_flag_q == SHA2_256) || ~MultimodeEn) ?
Tests: T1 T2 T4
149 {32'b0, message_length_i[31:0]}:
150 ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
151 message_length_i[63:0]: '0;
152 end
153
154 default: begin
155 shaf_rdata_o = '0;
Exclude Annotation: VC_COV_UNR
156 end
157 endcase
158
159 1/1(1 unreachable) if (!MultimodeEn) shaf_rdata_o [63:32] = 32'b0; // assign most sig 32 bits to constant 0
Tests: T1 T2 T3
MISSING_ELSE
160 end
161
162 // Padded length
163 // $ceil(message_length_i + 8 + 64, 512) -> message_length_i [8:0] + 440 and ignore carry
164 //assign length_added = (message_length_i[8:0] + 9'h1b8) ;
165
166 // fifo control
167 // add 8'h 80 , N 8'h00, 64'h message_length_i
168
169 // Steps
170 // 1. `hash_start_i` from CPU (or DMA?)
171 // 2. calculate `padded_length` from `message_length_i`
172 // 3. Check if tx_count == message_length_i, then go to 5
173 // 4. Receiving FIFO input (hand over to fifo output)
174 // 5. Padding bit 1 (8'h80) followed by 8'h00 if needed
175 // 6. Padding with length (high -> low)
176
177 // State Machine
178 typedef enum logic [2:0] {
179 StIdle, // fin_full to prevent unwanted FIFO write
180 StFifoReceive, // Check tx_count == message_length_i
181 StPad80, // 8'h 80 + 8'h 00 X N
182 StPad00,
183 StLenHi,
184 StLenLo
185 } pad_st_e;
186
187 pad_st_e st_q, st_d;
188
189 always_ff @(posedge clk_i or negedge rst_ni) begin
190 2/2 if (!rst_ni) st_q <= StIdle;
Tests: T1 T2 T3 | T1 T2 T3
191 1/1 else st_q <= st_d;
Tests: T1 T2 T3
192 end
193
194 // Next state
195 always_comb begin
196 1/1 shaf_rvalid_o = 1'b0;
Tests: T1 T2 T3
197 1/1 inc_txcount = 1'b0;
Tests: T1 T2 T3
198 1/1 sel_data = FifoIn;
Tests: T1 T2 T3
199 1/1 fifo_rready_o = 1'b0;
Tests: T1 T2 T3
200 1/1 st_d = StIdle;
Tests: T1 T2 T3
201
202 1/1 unique case (st_q)
Tests: T1 T2 T3
203 StIdle: begin
204 1/1 sel_data = FifoIn;
Tests: T1 T2 T3
205 1/1 shaf_rvalid_o = 1'b0;
Tests: T1 T2 T3
206 1/1 if (sha_en_i && hash_go) begin
Tests: T1 T2 T3
207 1/1 inc_txcount = 1'b0;
Tests: T1 T2 T4
208 1/1 st_d = StFifoReceive;
Tests: T1 T2 T4
209 end else begin
210 1/1 st_d = StIdle;
Tests: T1 T2 T3
211 end
212 end
213
214 StFifoReceive: begin
215 1/1 sel_data = FifoIn;
Tests: T1 T2 T4
216 1/1 if (fifo_partial && fifo_rvalid_i) begin
Tests: T1 T2 T4
217 // End of the message (last bit is not word-aligned) , assume hash_process_flag is set
218 1/1 shaf_rvalid_o = 1'b0; // Update entry at StPad80
Tests: T1 T2 T4
219 1/1 inc_txcount = 1'b0;
Tests: T1 T2 T4
220 1/1 fifo_rready_o = 1'b0;
Tests: T1 T2 T4
221 1/1 st_d = StPad80;
Tests: T1 T2 T4
222 1/1 end else if (!hash_process_flag_q) begin
Tests: T1 T2 T4
223 1/1 fifo_rready_o = shaf_rready_i;
Tests: T1 T2 T4
224 1/1 shaf_rvalid_o = fifo_rvalid_i;
Tests: T1 T2 T4
225 1/1 inc_txcount = shaf_rready_i;
Tests: T1 T2 T4
226 1/1 st_d = StFifoReceive;
Tests: T1 T2 T4
227 1/1 end else if (txcnt_eq_msg_len) begin
Tests: T1 T2 T4
228 // already received all msg and was waiting process flag
229 1/1 shaf_rvalid_o = 1'b0;
Tests: T1 T2 T4
230 1/1 inc_txcount = 1'b0;
Tests: T1 T2 T4
231 1/1 fifo_rready_o = 1'b0;
Tests: T1 T2 T4
232 1/1 st_d = StPad80;
Tests: T1 T2 T4
233 end else begin
234 1/1 shaf_rvalid_o = fifo_rvalid_i;
Tests: T1 T5 T6
235 1/1 fifo_rready_o = shaf_rready_i; // 0 always
Tests: T1 T5 T6
236 1/1 inc_txcount = shaf_rready_i; // 0 always
Tests: T1 T5 T6
237 1/1 st_d = StFifoReceive;
Tests: T1 T5 T6
238 end
239
240 1/1 if (txcnt_eq_msg_len && hash_stop_flag_q) begin
Tests: T1 T2 T4
241 1/1 shaf_rvalid_o = 1'b0;
Tests: T2 T4 T5
242 1/1 inc_txcount = 1'b0;
Tests: T2 T4 T5
243 1/1 fifo_rready_o = 1'b0;
Tests: T2 T4 T5
244 1/1 st_d = StIdle;
Tests: T2 T4 T5
245 end
MISSING_ELSE
246 end
247
248 StPad80: begin
249 1/1 sel_data = Pad80;
Tests: T1 T2 T4
250 1/1 shaf_rvalid_o = 1'b1;
Tests: T1 T2 T4
251 1/1 fifo_rready_o = (digest_mode_flag_q == SHA2_256 || ~MultimodeEn) ?
Tests: T1 T2 T4
252 shaf_rready_i && |message_length_i[4:3] :
253 ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
254 shaf_rready_i && |message_length_i[5:3] : '0; // Only when partial
255
256 // exactly 192 bits left, do not need to pad00's
257 1/1 if (shaf_rready_i && txcnt_eq_1a0) begin
Tests: T1 T2 T4
258 1/1 st_d = StLenHi;
Tests: T6 T18 T7
259 1/1 inc_txcount = 1'b1;
Tests: T6 T18 T7
260 // it does not matter if value is < or > than 416 bits. If it's the former, 00 pad until
261 // length field. If >, then the next chunk will contain the length field with appropriate
262 // 0 padding.
263 1/1 end else if (shaf_rready_i && !txcnt_eq_1a0) begin
Tests: T1 T2 T4
264 1/1 st_d = StPad00;
Tests: T1 T2 T4
265 1/1 inc_txcount = 1'b1;
Tests: T1 T2 T4
266 end else begin
267 1/1 st_d = StPad80;
Tests: T1 T4 T19
268 1/1 inc_txcount = 1'b0;
Tests: T1 T4 T19
269 end
270
271 // # Below part is temporal code to speed up the SHA by 16 clocks per chunk
272 // # (80 clk --> 64 clk)
273 // # leaving this as a reference but needs to verify it.
274 //if (shaf_rready_i && !txcnt_eq_1a0) begin
275 // st_d = StPad00;
276 //
277 // inc_txcount = 1'b1;
278 // shaf_rvalid_o = (msg_word_aligned) ? 1'b1 : fifo_rvalid;
279 // fifo_rready = (msg_word_aligned) ? 1'b0 : 1'b1;
280 //end else if (!shaf_rready_i && !txcnt_eq_1a0) begin
281 // st_d = StPad80;
282 //
283 // inc_txcount = 1'b0;
284 // shaf_rvalid_o = (msg_word_aligned) ? 1'b1 : fifo_rvalid;
285 //
286 //end else if (shaf_rready_i && txcnt_eq_1a0) begin
287 // st_d = StLenHi;
288 // inc_txcount = 1'b1;
289 //end else begin
290 // // !shaf_rready_i && txcnt_eq_1a0 , just wait until fifo_rready asserted
291 // st_d = StPad80;
292 // inc_txcount = 1'b0;
293 //end
294 end
295
296 StPad00: begin
297 1/1 sel_data = Pad00;
Tests: T1 T2 T4
298 1/1 shaf_rvalid_o = 1'b1;
Tests: T1 T2 T4
299
300 1/1 if (shaf_rready_i) begin
Tests: T1 T2 T4
301 1/1 inc_txcount = 1'b1;
Tests: T1 T2 T4
302 2/2 if (txcnt_eq_1a0) st_d = StLenHi;
Tests: T1 T2 T4 | T1 T2 T4
303 1/1 else st_d = StPad00;
Tests: T1 T2 T4
304 end else begin
305 1/1 st_d = StPad00;
Tests: T1 T2 T4
306 end
307 end
308
309 StLenHi: begin
310 1/1 sel_data = LenHi;
Tests: T1 T2 T4
311 1/1 shaf_rvalid_o = 1'b1;
Tests: T1 T2 T4
312
313 1/1 if (shaf_rready_i) begin
Tests: T1 T2 T4
314 1/1 st_d = StLenLo;
Tests: T1 T2 T4
315 1/1 inc_txcount = 1'b1;
Tests: T1 T2 T4
316 end else begin
317 0/1 ==> st_d = StLenHi;
318 0/1 ==> inc_txcount = 1'b0;
319 end
320 end
321
322 StLenLo: begin
323 1/1 sel_data = LenLo;
Tests: T1 T2 T4
324 1/1 shaf_rvalid_o = 1'b1;
Tests: T1 T2 T4
325
326 1/1 if (shaf_rready_i) begin
Tests: T1 T2 T4
327 1/1 st_d = StIdle;
Tests: T1 T2 T4
328 1/1 inc_txcount = 1'b1;
Tests: T1 T2 T4
329 end else begin
330 0/1 ==> st_d = StLenLo;
331 0/1 ==> inc_txcount = 1'b0;
332 end
333 end
334
335 default: begin
336 st_d = StIdle;
Exclude Annotation: VC_COV_UNR
337 end
338 endcase
339
340 2/2 if (!sha_en_i) st_d = StIdle;
Tests: T1 T2 T3 | T1 T2 T3
341 2/2 else if (hash_go) st_d = StFifoReceive;
Tests: T1 T2 T3 | T1 T2 T4
MISSING_ELSE
342 end
343
344 // tx_count
345 always_comb begin
346 1/1 tx_count_d = tx_count;
Tests: T1 T2 T3
347
348 1/1 if (hash_start_i) begin
Tests: T1 T2 T3
349 // When starting a fresh hash, initialize the data counter to zero.
350 1/1 tx_count_d = '0;
Tests: T1 T2 T4
351 1/1 end else if (hash_continue_i) begin
Tests: T1 T2 T3
352 // When continuing to hash, set the data counter to the current message length.
353 1/1 tx_count_d = message_length_i;
Tests: T2 T4 T5
354 1/1 end else if (inc_txcount) begin
Tests: T1 T2 T3
355 1/1 if ((digest_mode_flag_q == SHA2_256) || !MultimodeEn) begin
Tests: T1 T2 T4
356 1/1 tx_count_d[127:5] = tx_count[127:5] + 1'b1;
Tests: T1 T2 T4
357 1/1 end else if ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) begin
Tests: T1 T2 T4
358 1/1 tx_count_d[127:6] = tx_count[127:6] + 1'b1;
Tests: T1 T2 T4
359 end
==> MISSING_ELSE
360 end
MISSING_ELSE
361 end
362
363 always_ff @(posedge clk_i or negedge rst_ni) begin
364 2/2 if (!rst_ni) tx_count <= '0;
Tests: T1 T2 T3 | T1 T2 T3
365 1/1 else tx_count <= tx_count_d;
Tests: T1 T2 T3
366 end
367
368 1/1 assign digest_mode_flag_d = (hash_start_i || hash_continue_i) ? digest_mode_i : // set config
Tests: T1 T2 T3
369 hash_done_i ? SHA2_None : // clear
370 digest_mode_flag_q; // keep
371
372 always_ff @(posedge clk_i or negedge rst_ni) begin
373 2/2 if (!rst_ni) digest_mode_flag_q <= SHA2_None;
Tests: T1 T2 T3 | T1 T2 T3
374 1/1 else digest_mode_flag_q <= digest_mode_flag_d;
Tests: T1 T2 T3
375 end
376
377 // State machine is in Idle only when it meets tx_count == message length
378 1/1 assign msg_feed_complete_o = (hash_process_flag_q || hash_stop_flag_q) && (st_q == StIdle);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode.u_pad
| Total | Covered | Percent |
Conditions | 138 | 131 | 94.93 |
Logical | 138 | 131 | 94.93 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 48
EXPRESSION (hash_start_i | hash_continue_i)
------1----- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T5 |
1 | 0 | Covered | T1,T2,T4 |
LINE 60
EXPRESSION
Number Term
1 ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? (tx_count[8:0] == 9'h1a0) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (tx_count[9:0] == 10'h340) : '0))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 60
SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
----------------1--------------- --------2-------
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T3 |
1 | - | Covered | T1,T2,T4 |
LINE 60
SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 60
SUB-EXPRESSION (tx_count[8:0] == 9'h1a0)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 60
SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (tx_count[9:0] == 10'h340) : '0)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 60
SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
----------------1--------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
LINE 60
SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 60
SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 60
SUB-EXPRESSION (tx_count[9:0] == 10'h340)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 67
EXPRESSION (tx_count == message_length_i)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
EXPRESSION ((((~sha_en_i)) || hash_go || hash_done_i) ? 1'b0 : (hash_stop_i ? 1'b1 : hash_stop_flag_q))
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((~sha_en_i)) || hash_go || hash_done_i)
------1------ ---2--- -----3-----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T4 |
0 | 1 | 0 | Covered | T1,T2,T4 |
1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (hash_stop_i ? 1'b1 : hash_stop_flag_q)
-----1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T5 |
LINE 76
EXPRESSION ((((~sha_en_i)) || hash_go || hash_done_i) ? 1'b0 : (hash_process_i ? 1'b1 : hash_process_flag_q))
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 76
SUB-EXPRESSION (((~sha_en_i)) || hash_go || hash_done_i)
------1------ ---2--- -----3-----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T4 |
0 | 1 | 0 | Covered | T1,T2,T4 |
1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 76
SUB-EXPRESSION (hash_process_i ? 1'b1 : hash_process_flag_q)
-------1------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 112
EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
----------------1--------------- --------2-------
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T4 |
1 | - | Covered | T1,T2,T4 |
LINE 112
SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 120
EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
----------------1--------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
LINE 120
SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 120
SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 141
EXPRESSION
Number Term
1 ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? ({32'b0, message_length_i[63:32]}) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[127:64] : '0))
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 141
SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
----------------1--------------- --------2-------
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T4 |
1 | - | Covered | T1,T2,T4 |
LINE 141
SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 141
SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[127:64] : '0)
-----------------------------------1----------------------------------
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | |
VC_COV_UNR |
1 | Covered | T1,T2,T4 |
LINE 141
SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
----------------1--------------- ----------------2---------------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 0 | Excluded | |
VC_COV_UNR |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
LINE 141
SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 141
SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 148
EXPRESSION
Number Term
1 ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? ({32'b0, message_length_i[31:0]}) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[63:0] : '0))
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 148
SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
----------------1--------------- --------2-------
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T4 |
1 | - | Covered | T1,T2,T4 |
LINE 148
SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 148
SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[63:0] : '0)
-----------------------------------1----------------------------------
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | |
VC_COV_UNR |
1 | Covered | T1,T2,T4 |
LINE 148
SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
----------------1--------------- ----------------2---------------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 0 | Excluded | |
VC_COV_UNR |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
LINE 148
SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 148
SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 206
EXPRESSION (sha_en_i && hash_go)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T4 |
LINE 216
EXPRESSION (fifo_partial && fifo_rvalid_i)
------1----- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 240
EXPRESSION (txcnt_eq_msg_len && hash_stop_flag_q)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T8,T23,T24 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T2,T4,T5 |
LINE 251
EXPRESSION
Number Term
1 ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? (shaf_rready_i && ((|message_length_i[4:3]))) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (shaf_rready_i && ((|message_length_i[5:3]))) : '0))
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 251
SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
----------------1--------------- --------2-------
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T4 |
1 | - | Covered | T1,T2,T4 |
LINE 251
SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 251
SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[4:3])))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T9,T21 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T2,T4 |
LINE 251
SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (shaf_rready_i && ((|message_length_i[5:3]))) : '0)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T4 |
LINE 251
SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
----------------1--------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
LINE 251
SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 251
SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 251
SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[5:3])))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 257
EXPRESSION (shaf_rready_i && txcnt_eq_1a0)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T6,T18,T7 |
LINE 263
EXPRESSION (shaf_rready_i && ((!txcnt_eq_1a0)))
------1------ --------2--------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T1,T4,T19 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T4 |
LINE 355
EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((!MultimodeEn)))
----------------1--------------- --------2-------
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T4 |
1 | - | Covered | T1,T2,T4 |
LINE 355
SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 357
EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
----------------1--------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
LINE 357
SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 357
SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 368
EXPRESSION ((hash_start_i || hash_continue_i) ? digest_mode_i : (hash_done_i ? SHA2_None : digest_mode_flag_q))
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 368
SUB-EXPRESSION (hash_start_i || hash_continue_i)
------1----- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T5 |
1 | 0 | Covered | T1,T2,T4 |
LINE 368
SUB-EXPRESSION (hash_done_i ? SHA2_None : digest_mode_flag_q)
-----1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 378
EXPRESSION ((hash_process_flag_q || hash_stop_flag_q) && (st_q == StIdle))
--------------------1-------------------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 378
SUB-EXPRESSION (hash_process_flag_q || hash_stop_flag_q)
---------1--------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T5 |
1 | 0 | Covered | T1,T2,T4 |
LINE 378
SUB-EXPRESSION (st_q == StIdle)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
FSM Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode.u_pad
Summary for FSM :: st_q
| Total | Covered | Percent | |
States |
6 |
6 |
100.00 |
(Not included in score) |
Transitions |
11 |
10 |
90.91 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: st_q
| | | |
StFifoReceive |
208 |
Covered |
T1,T2,T4 |
StIdle |
200 |
Covered |
T1,T2,T3 |
StLenHi |
258 |
Covered |
T1,T2,T4 |
StLenLo |
314 |
Covered |
T1,T2,T4 |
StPad00 |
264 |
Covered |
T1,T2,T4 |
StPad80 |
221 |
Covered |
T1,T2,T4 |
| | | | |
StFifoReceive->StIdle |
200 |
Covered |
T2,T4,T5 |
|
StFifoReceive->StPad80 |
221 |
Covered |
T1,T2,T4 |
|
StIdle->StFifoReceive |
208 |
Covered |
T1,T2,T4 |
|
StLenHi->StFifoReceive |
341 |
Excluded |
|
[INVALID] Intend to remove transition |
StLenHi->StIdle |
200 |
Not Covered |
|
|
StLenHi->StLenLo |
314 |
Covered |
T1,T2,T4 |
|
StLenLo->StFifoReceive |
341 |
Excluded |
|
[INVALID] Intend to remove transition |
StLenLo->StIdle |
200 |
Covered |
T1,T2,T4 |
|
StPad00->StFifoReceive |
341 |
Excluded |
|
[INVALID] Intend to remove transition |
StPad00->StIdle |
200 |
Covered |
T10,T25 |
|
StPad00->StLenHi |
302 |
Covered |
T1,T2,T4 |
|
StPad80->StFifoReceive |
341 |
Excluded |
|
[INVALID] Intend to remove transition |
StPad80->StIdle |
200 |
Covered |
T11 |
|
StPad80->StLenHi |
258 |
Covered |
T6,T18,T7 |
|
StPad80->StPad00 |
264 |
Covered |
T1,T2,T4 |
|
Branch Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode.u_pad
| Line No. | Total | Covered | Percent |
Branches |
|
70 |
65 |
92.86 |
TERNARY |
60 |
3 |
3 |
100.00 |
TERNARY |
72 |
3 |
3 |
100.00 |
TERNARY |
76 |
3 |
3 |
100.00 |
TERNARY |
368 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
CASE |
101 |
19 |
18 |
94.74 |
IF |
159 |
1 |
1 |
100.00 |
IF |
190 |
2 |
2 |
100.00 |
CASE |
202 |
21 |
18 |
85.71 |
IF |
340 |
3 |
3 |
100.00 |
IF |
348 |
6 |
5 |
83.33 |
IF |
364 |
2 |
2 |
100.00 |
IF |
373 |
2 |
2 |
100.00 |
60 assign txcnt_eq_1a0 = (digest_mode_flag_q == SHA2_256 || ~MultimodeEn) ?
-1-
==>
61 (tx_count[8:0] == 9'h1a0) :
62 ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
-2-
==>
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
Covered |
T1,T2,T3 |
72 assign hash_stop_flag_d = (~sha_en_i || hash_go || hash_done_i) ? 1'b0 :
-1-
==>
73 hash_stop_i ? 1'b1 :
-2-
==>
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T4,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
76 assign hash_process_flag_d = (~sha_en_i || hash_go || hash_done_i) ? 1'b0 :
-1-
==>
77 hash_process_i ? 1'b1 :
-2-
==>
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
Covered |
T1,T2,T3 |
368 assign digest_mode_flag_d = (hash_start_i || hash_continue_i) ? digest_mode_i : // set config
-1-
==>
369 hash_done_i ? SHA2_None : // clear
-2-
==>
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
Covered |
T1,T2,T3 |
81 if (!rst_ni) begin
-1-
82 hash_stop_flag_q <= 1'b0;
==>
83 hash_process_flag_q <= 1'b0;
84 end else begin
85 hash_stop_flag_q <= hash_stop_flag_d;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
101 unique case (sel_data)
-1-
102 FifoIn: begin
103 shaf_rdata_o = fifo_rdata_i.data;
==>
104 end
105
106 Pad80: begin
107 // {a[7:0], b[7:0], c[7:0], d[7:0]}
108 // msglen[4:3] == 00 |-> {'h80, 'h00, 'h00, 'h00}
109 // msglen[4:3] == 01 |-> {msg, 'h80, 'h00, 'h00}
110 // msglen[4:3] == 10 |-> {msg[15:0], 'h80, 'h00}
111 // msglen[4:3] == 11 |-> {msg[23:0], 'h80}
112 if ((digest_mode_flag_q == SHA2_256) || ~MultimodeEn) begin
-2-
113 unique case (message_length_i[4:3])
-3-
114 2'b 00: shaf_rdata_o = 64'h 0000_0000_8000_0000;
==>
115 2'b 01: shaf_rdata_o = {32'h 0000_0000, fifo_rdata_i.data[31:24], 24'h 8000_00};
==>
116 2'b 10: shaf_rdata_o = {32'h 0000_0000, fifo_rdata_i.data[31:16], 16'h 8000};
==>
117 2'b 11: shaf_rdata_o = {32'h 0000_0000, fifo_rdata_i.data[31: 8], 8'h 80};
==>
118 default: shaf_rdata_o = 64'h0;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
119 endcase
120 end else if ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) begin
-4-
121 unique case (message_length_i[5:3])
-5-
122 3'b 000: shaf_rdata_o = 64'h 8000_0000_0000_0000;
==>
123 3'b 001: shaf_rdata_o = {fifo_rdata_i.data[63:56], 56'h 8000_0000_0000_00};
==>
124 3'b 010: shaf_rdata_o = {fifo_rdata_i.data[63:48], 48'h 8000_0000_0000};
==>
125 3'b 011: shaf_rdata_o = {fifo_rdata_i.data[63:40], 40'h 8000_0000_00};
==>
126 3'b 100: shaf_rdata_o = {fifo_rdata_i.data[63:32], 32'h 8000_0000};
==>
127 3'b 101: shaf_rdata_o = {fifo_rdata_i.data[63:24], 24'h 8000_00};
==>
128 3'b 110: shaf_rdata_o = {fifo_rdata_i.data[63:16], 16'h 8000};
==>
129 3'b 111: shaf_rdata_o = {fifo_rdata_i.data[63:8], 8'h 80};
==>
130 default: shaf_rdata_o = 64'h0;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
131 endcase
132 end else
133 shaf_rdata_o = '0;
==>
134 end
135
136 Pad00: begin
137 shaf_rdata_o = '0;
==>
138 end
139
140 LenHi: begin
141 shaf_rdata_o = ((digest_mode_flag_q == SHA2_256) || ~MultimodeEn) ?
-6-
==>
142 {32'b0, message_length_i[63:32]}:
143 ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
-7-
==>
==> (Excluded)
144 message_length_i[127:64] : '0;
145 end
146
147 LenLo: begin
148 shaf_rdata_o = ((digest_mode_flag_q == SHA2_256) || ~MultimodeEn) ?
-8-
==>
149 {32'b0, message_length_i[31:0]}:
150 ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
-9-
==>
==> (Excluded)
151 message_length_i[63:0]: '0;
152 end
153
154 default: begin
155 shaf_rdata_o = '0;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | Status | Tests | Exclude Annotation |
FifoIn |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
Pad80 |
1 |
2'b00 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T4,T6 |
|
Pad80 |
1 |
2'b01 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
|
Pad80 |
1 |
2'b10 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T7,T8 |
|
Pad80 |
1 |
2'b11 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T4,T6 |
|
Pad80 |
1 |
default |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
Pad80 |
0 |
- |
1 |
3'b000 |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
|
Pad80 |
0 |
- |
1 |
3'b001 |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
|
Pad80 |
0 |
- |
1 |
3'b010 |
- |
- |
- |
- |
Covered |
T5,T18,T7 |
|
Pad80 |
0 |
- |
1 |
3'b011 |
- |
- |
- |
- |
Covered |
T4,T18,T7 |
|
Pad80 |
0 |
- |
1 |
3'b100 |
- |
- |
- |
- |
Covered |
T7,T8,T20 |
|
Pad80 |
0 |
- |
1 |
3'b101 |
- |
- |
- |
- |
Covered |
T2,T4,T6 |
|
Pad80 |
0 |
- |
1 |
3'b110 |
- |
- |
- |
- |
Covered |
T18,T7,T21 |
|
Pad80 |
0 |
- |
1 |
3'b111 |
- |
- |
- |
- |
Covered |
T1,T4,T22 |
|
Pad80 |
0 |
- |
1 |
default |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
Pad80 |
0 |
- |
0 |
- |
- |
- |
- |
- |
Not Covered |
|
|
Pad00 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
|
LenHi |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T1,T2,T4 |
|
LenHi |
- |
- |
- |
- |
0 |
1 |
- |
- |
Covered |
T1,T2,T4 |
|
LenHi |
- |
- |
- |
- |
0 |
0 |
- |
- |
Excluded |
|
VC_COV_UNR |
LenLo |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T1,T2,T4 |
|
LenLo |
- |
- |
- |
- |
- |
- |
0 |
1 |
Covered |
T1,T2,T4 |
|
LenLo |
- |
- |
- |
- |
- |
- |
0 |
0 |
Excluded |
|
VC_COV_UNR |
default |
- |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
159 if (!MultimodeEn) shaf_rdata_o [63:32] = 32'b0; // assign most sig 32 bits to constant 0
-1-
==> (Unreachable)
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Unreachable |
|
0 |
Covered |
T1,T2,T3 |
190 if (!rst_ni) st_q <= StIdle;
-1-
==>
191 else st_q <= st_d;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
202 unique case (st_q)
-1-
203 StIdle: begin
204 sel_data = FifoIn;
205 shaf_rvalid_o = 1'b0;
206 if (sha_en_i && hash_go) begin
-2-
207 inc_txcount = 1'b0;
==>
208 st_d = StFifoReceive;
209 end else begin
210 st_d = StIdle;
==>
211 end
212 end
213
214 StFifoReceive: begin
215 sel_data = FifoIn;
216 if (fifo_partial && fifo_rvalid_i) begin
-3-
217 // End of the message (last bit is not word-aligned) , assume hash_process_flag is set
218 shaf_rvalid_o = 1'b0; // Update entry at StPad80
==>
219 inc_txcount = 1'b0;
220 fifo_rready_o = 1'b0;
221 st_d = StPad80;
222 end else if (!hash_process_flag_q) begin
-4-
223 fifo_rready_o = shaf_rready_i;
==>
224 shaf_rvalid_o = fifo_rvalid_i;
225 inc_txcount = shaf_rready_i;
226 st_d = StFifoReceive;
227 end else if (txcnt_eq_msg_len) begin
-5-
228 // already received all msg and was waiting process flag
229 shaf_rvalid_o = 1'b0;
==>
230 inc_txcount = 1'b0;
231 fifo_rready_o = 1'b0;
232 st_d = StPad80;
233 end else begin
234 shaf_rvalid_o = fifo_rvalid_i;
==>
235 fifo_rready_o = shaf_rready_i; // 0 always
236 inc_txcount = shaf_rready_i; // 0 always
237 st_d = StFifoReceive;
238 end
239
240 if (txcnt_eq_msg_len && hash_stop_flag_q) begin
-6-
241 shaf_rvalid_o = 1'b0;
==>
242 inc_txcount = 1'b0;
243 fifo_rready_o = 1'b0;
244 st_d = StIdle;
245 end
MISSING_ELSE
==>
246 end
247
248 StPad80: begin
249 sel_data = Pad80;
250 shaf_rvalid_o = 1'b1;
251 fifo_rready_o = (digest_mode_flag_q == SHA2_256 || ~MultimodeEn) ?
-7-
==>
252 shaf_rready_i && |message_length_i[4:3] :
253 ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
-8-
==>
==>
254 shaf_rready_i && |message_length_i[5:3] : '0; // Only when partial
255
256 // exactly 192 bits left, do not need to pad00's
257 if (shaf_rready_i && txcnt_eq_1a0) begin
-9-
258 st_d = StLenHi;
==>
259 inc_txcount = 1'b1;
260 // it does not matter if value is < or > than 416 bits. If it's the former, 00 pad until
261 // length field. If >, then the next chunk will contain the length field with appropriate
262 // 0 padding.
263 end else if (shaf_rready_i && !txcnt_eq_1a0) begin
-10-
264 st_d = StPad00;
==>
265 inc_txcount = 1'b1;
266 end else begin
267 st_d = StPad80;
==>
268 inc_txcount = 1'b0;
269 end
270
271 // # Below part is temporal code to speed up the SHA by 16 clocks per chunk
272 // # (80 clk --> 64 clk)
273 // # leaving this as a reference but needs to verify it.
274 //if (shaf_rready_i && !txcnt_eq_1a0) begin
275 // st_d = StPad00;
276 //
277 // inc_txcount = 1'b1;
278 // shaf_rvalid_o = (msg_word_aligned) ? 1'b1 : fifo_rvalid;
279 // fifo_rready = (msg_word_aligned) ? 1'b0 : 1'b1;
280 //end else if (!shaf_rready_i && !txcnt_eq_1a0) begin
281 // st_d = StPad80;
282 //
283 // inc_txcount = 1'b0;
284 // shaf_rvalid_o = (msg_word_aligned) ? 1'b1 : fifo_rvalid;
285 //
286 //end else if (shaf_rready_i && txcnt_eq_1a0) begin
287 // st_d = StLenHi;
288 // inc_txcount = 1'b1;
289 //end else begin
290 // // !shaf_rready_i && txcnt_eq_1a0 , just wait until fifo_rready asserted
291 // st_d = StPad80;
292 // inc_txcount = 1'b0;
293 //end
294 end
295
296 StPad00: begin
297 sel_data = Pad00;
298 shaf_rvalid_o = 1'b1;
299
300 if (shaf_rready_i) begin
-11-
301 inc_txcount = 1'b1;
302 if (txcnt_eq_1a0) st_d = StLenHi;
-12-
==>
303 else st_d = StPad00;
==>
304 end else begin
305 st_d = StPad00;
==>
306 end
307 end
308
309 StLenHi: begin
310 sel_data = LenHi;
311 shaf_rvalid_o = 1'b1;
312
313 if (shaf_rready_i) begin
-13-
314 st_d = StLenLo;
==>
315 inc_txcount = 1'b1;
316 end else begin
317 st_d = StLenHi;
==>
318 inc_txcount = 1'b0;
319 end
320 end
321
322 StLenLo: begin
323 sel_data = LenLo;
324 shaf_rvalid_o = 1'b1;
325
326 if (shaf_rready_i) begin
-14-
327 st_d = StIdle;
==>
328 inc_txcount = 1'b1;
329 end else begin
330 st_d = StLenLo;
==>
331 inc_txcount = 1'b0;
332 end
333 end
334
335 default: begin
336 st_d = StIdle;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | Status | Tests | Exclude Annotation |
StIdle |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
|
StIdle |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
StFifoReceive |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
|
StFifoReceive |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
|
StFifoReceive |
- |
0 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
|
StFifoReceive |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T5,T6 |
|
StFifoReceive |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
StFifoReceive |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
|
StPad80 |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
|
StPad80 |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
|
StPad80 |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
Not Covered |
|
|
StPad80 |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T6,T18,T7 |
|
StPad80 |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
|
StPad80 |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T1,T4,T19 |
|
StPad00 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
Covered |
T1,T2,T4 |
|
StPad00 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
Covered |
T1,T2,T4 |
|
StPad00 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T1,T2,T4 |
|
StLenHi |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T1,T2,T4 |
|
StLenHi |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
Not Covered |
|
|
StLenLo |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T4 |
|
StLenLo |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Not Covered |
|
|
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
340 if (!sha_en_i) st_d = StIdle;
-1-
==>
341 else if (hash_go) st_d = StFifoReceive;
-2-
==>
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
Covered |
T1,T2,T3 |
348 if (hash_start_i) begin
-1-
349 // When starting a fresh hash, initialize the data counter to zero.
350 tx_count_d = '0;
==>
351 end else if (hash_continue_i) begin
-2-
352 // When continuing to hash, set the data counter to the current message length.
353 tx_count_d = message_length_i;
==>
354 end else if (inc_txcount) begin
-3-
355 if ((digest_mode_flag_q == SHA2_256) || !MultimodeEn) begin
-4-
356 tx_count_d[127:5] = tx_count[127:5] + 1'b1;
==>
357 end else if ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) begin
-5-
358 tx_count_d[127:6] = tx_count[127:6] + 1'b1;
==>
359 end
MISSING_ELSE
==>
360 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
0 |
1 |
- |
- |
- |
Covered |
T2,T4,T5 |
0 |
0 |
1 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
0 |
0 |
Not Covered |
|
0 |
0 |
0 |
- |
- |
Covered |
T1,T2,T3 |
364 if (!rst_ni) tx_count <= '0;
-1-
==>
365 else tx_count <= tx_count_d;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
373 if (!rst_ni) digest_mode_flag_q <= SHA2_None;
-1-
==>
374 else digest_mode_flag_q <= digest_mode_flag_d;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |