Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38162307	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

35792801

1

T1

22114

T2

3

T14

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35315553	1			T1	24869		T2	1		T3	1
values[0x0]	18111049	1			T1	11322		T2	4		T14	8
values[0x1]	20528506	1			T1	13260		T2	5		T14	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29400285	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

44554823

1

T1

28339

T2

3

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	213411	1			T1	191		T4	6		T6	14
valid_sources[0x01]	214308	1			T1	187		T4	28		T6	11
valid_sources[0x02]	486271	1			T1	207		T4	6		T6	14
valid_sources[0x03]	511561	1			T1	195		T4	23		T6	23
valid_sources[0x04]	210405	1			T1	233		T4	14		T6	30
valid_sources[0x05]	211973	1			T1	173		T4	13		T6	14
valid_sources[0x06]	210752	1			T1	209		T4	16		T6	10
valid_sources[0x07]	1289821	1			T1	197		T4	16		T6	19
valid_sources[0x08]	215061	1			T1	200		T4	26		T6	40
valid_sources[0x09]	213406	1			T1	198		T4	20		T6	31
valid_sources[0x0a]	212207	1			T1	202		T4	5		T6	15
valid_sources[0x0b]	223677	1			T1	235		T4	38		T5	8306
valid_sources[0x0c]	210284	1			T1	185		T4	10		T23	2
valid_sources[0x0d]	451334	1			T1	234		T4	15		T6	37
valid_sources[0x0e]	528163	1			T1	220		T4	17		T6	9
valid_sources[0x0f]	211621	1			T1	184		T4	12		T6	34
valid_sources[0x10]	213484	1			T1	203		T4	2		T6	28
valid_sources[0x11]	331901	1			T1	170		T4	21		T6	16
valid_sources[0x12]	274850	1			T1	164		T4	16		T6	20
valid_sources[0x13]	210941	1			T1	227		T4	18		T6	10
valid_sources[0x14]	213434	1			T1	187		T4	9		T6	15
valid_sources[0x15]	212631	1			T1	209		T4	12		T6	38
valid_sources[0x16]	211787	1			T1	158		T4	19		T6	21
valid_sources[0x17]	270766	1			T1	156		T4	4		T6	36
valid_sources[0x18]	208222	1			T1	165		T4	13		T6	28
valid_sources[0x19]	211986	1			T1	184		T4	25		T6	2
valid_sources[0x1a]	226154	1			T1	201		T4	27		T6	10
valid_sources[0x1b]	211582	1			T1	193		T4	12		T6	17
valid_sources[0x1c]	212788	1			T1	182		T4	6		T6	16
valid_sources[0x1d]	213367	1			T1	197		T4	7		T6	13
valid_sources[0x1e]	211431	1			T1	155		T4	17		T6	30
valid_sources[0x1f]	393865	1			T1	218		T4	27		T6	19
valid_sources[0x20]	223590	1			T1	177		T4	18		T6	31
valid_sources[0x21]	208885	1			T1	217		T4	8		T6	25
valid_sources[0x22]	312902	1			T1	229		T4	10		T6	31
valid_sources[0x23]	212377	1			T1	218		T4	16		T6	19
valid_sources[0x24]	216422	1			T1	209		T4	36		T6	8
valid_sources[0x25]	213318	1			T1	195		T4	17		T6	23
valid_sources[0x26]	269808	1			T1	180		T4	14		T6	26
valid_sources[0x27]	298862	1			T1	183		T4	37		T6	18
valid_sources[0x28]	324683	1			T1	212		T4	25		T6	10
valid_sources[0x29]	212536	1			T1	194		T4	8		T6	15
valid_sources[0x2a]	211828	1			T1	197		T4	9		T6	21
valid_sources[0x2b]	209923	1			T1	203		T4	45		T6	61
valid_sources[0x2c]	377924	1			T1	190		T4	13		T6	33
valid_sources[0x2d]	554213	1			T1	168		T4	16		T6	10
valid_sources[0x2e]	208760	1			T1	221		T3	1		T4	9
valid_sources[0x2f]	212926	1			T1	174		T4	21		T6	22
valid_sources[0x30]	539804	1			T1	143		T4	1		T6	20
valid_sources[0x31]	344447	1			T1	193		T4	11		T6	17
valid_sources[0x32]	210934	1			T1	191		T4	19		T6	20
valid_sources[0x33]	209261	1			T1	212		T4	10		T6	15
valid_sources[0x34]	211381	1			T1	228		T4	9		T6	21
valid_sources[0x35]	292796	1			T1	189		T4	23		T6	19
valid_sources[0x36]	209091	1			T1	193		T4	16		T6	18
valid_sources[0x37]	211540	1			T1	203		T4	26		T6	10
valid_sources[0x38]	596392	1			T1	197		T4	20		T6	21
valid_sources[0x39]	286303	1			T1	169		T4	24		T6	24
valid_sources[0x3a]	211233	1			T1	233		T4	16		T6	11
valid_sources[0x3b]	211091	1			T1	203		T4	24		T6	9
valid_sources[0x3c]	211831	1			T1	236		T4	23		T6	19
valid_sources[0x3d]	213042	1			T1	163		T4	11		T6	47
valid_sources[0x3e]	212675	1			T1	211		T4	29		T6	26
valid_sources[0x3f]	211605	1			T1	178		T4	4		T6	40
valid_sources[0x40]	211318	1			T1	199		T4	23		T6	13
valid_sources[0x41]	210290	1			T1	187		T4	17		T6	36
valid_sources[0x42]	1017828	1			T1	175		T4	34		T6	16
valid_sources[0x43]	210935	1			T1	199		T4	22		T6	18
valid_sources[0x44]	211276	1			T1	201		T4	6		T6	31
valid_sources[0x45]	1092236	1			T1	145		T4	26		T6	31
valid_sources[0x46]	212304	1			T1	147		T4	26		T6	19
valid_sources[0x47]	210951	1			T1	200		T4	17		T6	18
valid_sources[0x48]	211617	1			T1	213		T4	29		T6	24
valid_sources[0x49]	249793	1			T1	185		T4	8		T6	18
valid_sources[0x4a]	210899	1			T1	149		T4	35		T6	17
valid_sources[0x4b]	211013	1			T1	219		T4	4		T6	16
valid_sources[0x4c]	210247	1			T1	253		T4	11		T6	25
valid_sources[0x4d]	210487	1			T1	218		T4	10		T6	20
valid_sources[0x4e]	210279	1			T1	204		T4	8		T6	36
valid_sources[0x4f]	389913	1			T1	178		T4	11		T6	22
valid_sources[0x50]	229719	1			T1	203		T4	11		T6	24
valid_sources[0x51]	235639	1			T1	180		T4	40		T6	31
valid_sources[0x52]	572016	1			T1	168		T4	20		T6	17
valid_sources[0x53]	223080	1			T1	180		T4	31		T6	14
valid_sources[0x54]	211344	1			T1	164		T4	10		T6	38
valid_sources[0x55]	258454	1			T1	156		T14	1		T4	19
valid_sources[0x56]	211144	1			T1	203		T4	13		T6	14
valid_sources[0x57]	212209	1			T1	217		T4	3		T6	18
valid_sources[0x58]	305911	1			T1	188		T4	4		T6	17
valid_sources[0x59]	212439	1			T1	202		T4	8		T6	5
valid_sources[0x5a]	269395	1			T1	183		T4	3		T6	22
valid_sources[0x5b]	212380	1			T1	190		T4	15		T6	23
valid_sources[0x5c]	210985	1			T1	197		T4	9		T6	22
valid_sources[0x5d]	248226	1			T1	173		T4	9		T6	22
valid_sources[0x5e]	214894	1			T1	213		T4	11		T6	24
valid_sources[0x5f]	244375	1			T1	197		T4	18		T6	24
valid_sources[0x60]	212316	1			T1	193		T4	9		T6	18
valid_sources[0x61]	212810	1			T1	234		T4	14		T6	27
valid_sources[0x62]	214103	1			T1	179		T4	26		T6	30
valid_sources[0x63]	232574	1			T1	218		T4	17		T6	45
valid_sources[0x64]	209991	1			T1	207		T4	22		T6	24
valid_sources[0x65]	354363	1			T1	173		T4	40		T6	6
valid_sources[0x66]	209628	1			T1	169		T4	13		T6	30
valid_sources[0x67]	209314	1			T1	172		T4	31		T23	1
valid_sources[0x68]	212091	1			T1	194		T4	14		T6	27
valid_sources[0x69]	212852	1			T1	190		T4	28		T6	25
valid_sources[0x6a]	210290	1			T1	174		T4	12		T6	43
valid_sources[0x6b]	210769	1			T1	181		T4	16		T6	20
valid_sources[0x6c]	210212	1			T1	165		T2	10		T4	6
valid_sources[0x6d]	286221	1			T1	191		T4	23		T6	8
valid_sources[0x6e]	210431	1			T1	227		T4	22		T6	25
valid_sources[0x6f]	208761	1			T1	214		T4	20		T6	22
valid_sources[0x70]	293179	1			T1	199		T6	23		T25	24
valid_sources[0x71]	209823	1			T1	199		T4	44		T6	48
valid_sources[0x72]	211324	1			T1	163		T4	13		T6	11
valid_sources[0x73]	211185	1			T1	169		T4	27		T6	22
valid_sources[0x74]	211199	1			T1	184		T4	12		T6	11
valid_sources[0x75]	342420	1			T1	199		T4	2		T6	8
valid_sources[0x76]	210629	1			T1	192		T4	29		T6	13
valid_sources[0x77]	211549	1			T1	177		T4	18		T6	26
valid_sources[0x78]	274226	1			T1	199		T4	3		T6	30
valid_sources[0x79]	957303	1			T1	164		T4	1		T6	38
valid_sources[0x7a]	209083	1			T1	171		T4	5		T6	22
valid_sources[0x7b]	220881	1			T1	165		T4	21		T6	16
valid_sources[0x7c]	223497	1			T1	169		T4	25		T6	21
valid_sources[0x7d]	211643	1			T1	222		T4	9		T6	22
valid_sources[0x7e]	260454	1			T1	183		T4	1		T21	7
valid_sources[0x7f]	211956	1			T1	175		T4	27		T6	7
valid_sources[0x80]	212073	1			T1	178		T4	9		T6	33

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17452801

1

T1

12480

T2

1

T20

1

values[0x0]

all_enables

biggest_size

9892124

1

T1

5281

T14

2

T4

592

values[0x1]

all_enables

biggest_size

8447876

1

T1

4353

T2

2

T14

1