Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

40027832

1

T1

27337

T2

7

T3

1

full_word

35914824

1

T1

22114

T2

3

T14

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	75942246	1			T1	49451		T2	10		T3	1
auto[TlIntgErrCmd]	141	1			T68	11		T69	3		T70	15
auto[TlIntgErrData]	130	1			T68	8		T69	4		T70	11
auto[TlIntgErrBoth]	139	1			T68	11		T69	3		T70	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35942978

1

T1

24869

T2

1

T3

1

auto[1]

39999678

1

T1

24582

T2

9

T14

17

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18442147	1			T1	12389		T3	1		T14	1
auto[TlIntgErrNone]	partial	auto[1]	21585306	1			T1	14948		T2	7		T14	14
auto[TlIntgErrNone]	full_word	auto[0]	17500655	1			T1	12480		T2	1		T20	1
auto[TlIntgErrNone]	full_word	auto[1]	18414138	1			T1	9634		T2	2		T14	3
auto[TlIntgErrCmd]	partial	auto[0]	57	1			T68	2		T69	1		T70	9
auto[TlIntgErrCmd]	partial	auto[1]	73	1			T68	8		T69	2		T70	4
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T70	2		T140	1		T141	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T68	1		T71	1		T136	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T68	3		T70	4		T138	3
auto[TlIntgErrData]	partial	auto[1]	70	1			T68	5		T69	4		T70	6
auto[TlIntgErrData]	full_word	auto[0]	7	1			T70	1		T138	1		T71	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T71	1		T142	1		T140	1
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T68	3		T69	1		T70	3
auto[TlIntgErrBoth]	partial	auto[1]	77	1			T68	8		T69	2		T70	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T143	1		T141	1		T144	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T145	1		T136	1		T146	1