Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	384889451	1070383	0	0
intr_enable_rd_A	384889451	3502	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384889451	1070383	0	0
T11	288443	1911	0	0
T12	267862	4243	0	0
T13	0	7972	0	0
T18	0	6629	0	0
T19	0	16705	0	0
T27	79776	0	0	0
T28	101348	0	0	0
T31	0	10572	0	0
T32	0	3810	0	0
T33	36362	0	0	0
T54	351928	0	0	0
T56	71907	0	0	0
T67	3674	0	0	0
T72	0	9	0	0
T73	0	264	0	0
T74	0	5	0	0
T75	1874	0	0	0
T76	85947	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384889451	3502	0	0
T11	288443	25	0	0
T12	267862	0	0	0
T18	0	75	0	0
T19	0	45	0	0
T27	79776	0	0	0
T28	101348	0	0	0
T33	36362	0	0	0
T54	351928	0	0	0
T56	71907	0	0	0
T67	3674	0	0	0
T75	1874	0	0	0
T76	85947	0	0	0
T77	0	30	0	0
T78	0	43	0	0
T79	0	26	0	0
T80	0	44	0	0
T81	0	26	0	0
T82	0	13	0	0
T83	0	11	0	0