Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42507497	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

39593029

1

T1

3786

T2

6

T12

893

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	39372443	1			T1	2701		T2	1		T3	1
values[0x0]	20051347	1			T1	1672		T2	7		T12	445
values[0x1]	22676736	1			T1	1720		T2	6		T12	534

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32790403	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

49310123

1

T1

4453

T2

7

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	524859	1			T12	17		T4	5		T6	50
valid_sources[0x01]	228540	1			T4	1		T6	37		T7	39
valid_sources[0x02]	228935	1			T12	16		T4	1		T6	28
valid_sources[0x03]	231338	1			T6	44		T7	50		T11	29
valid_sources[0x04]	226207	1			T4	2		T6	46		T7	35
valid_sources[0x05]	354064	1			T12	2		T6	46		T7	26
valid_sources[0x06]	228835	1			T12	20		T6	41		T7	39
valid_sources[0x07]	292000	1			T12	26		T4	1		T6	36
valid_sources[0x08]	674043	1			T12	2		T4	2		T6	43
valid_sources[0x09]	229048	1			T4	1		T6	29		T7	32
valid_sources[0x0a]	231448	1			T12	3		T6	35		T7	39
valid_sources[0x0b]	249419	1			T12	4		T6	47		T7	39
valid_sources[0x0c]	227948	1			T12	17		T6	35		T7	46
valid_sources[0x0d]	427587	1			T12	7		T4	1		T6	37
valid_sources[0x0e]	225687	1			T12	1		T4	1		T6	34
valid_sources[0x0f]	226898	1			T4	3		T6	37		T7	23
valid_sources[0x10]	227773	1			T12	4		T4	1		T6	36
valid_sources[0x11]	226716	1			T3	1		T6	34		T7	11
valid_sources[0x12]	224719	1			T12	3		T6	51		T7	29
valid_sources[0x13]	226533	1			T12	9		T6	45		T7	49
valid_sources[0x14]	225764	1			T4	2		T6	31		T7	25
valid_sources[0x15]	2306734	1			T12	6		T4	1		T6	43
valid_sources[0x16]	235232	1			T6	33		T7	42		T11	19
valid_sources[0x17]	227394	1			T12	2		T4	3		T6	47
valid_sources[0x18]	259786	1			T12	4		T6	42		T7	38
valid_sources[0x19]	230127	1			T12	19		T20	1		T4	2
valid_sources[0x1a]	291564	1			T4	4		T6	40		T7	35
valid_sources[0x1b]	229706	1			T6	50		T7	33		T11	27
valid_sources[0x1c]	227993	1			T12	9		T6	49		T7	13
valid_sources[0x1d]	232175	1			T12	1		T4	2		T6	49
valid_sources[0x1e]	231348	1			T4	1		T6	23		T7	35
valid_sources[0x1f]	226974	1			T4	2		T6	37		T7	63
valid_sources[0x20]	238408	1			T4	1		T6	38		T7	34
valid_sources[0x21]	229615	1			T12	18		T4	2		T6	34
valid_sources[0x22]	376031	1			T12	45		T4	1		T6	52
valid_sources[0x23]	227733	1			T12	2		T6	32		T7	47
valid_sources[0x24]	812295	1			T6	37		T7	46		T11	36
valid_sources[0x25]	226643	1			T12	4		T4	1		T6	47
valid_sources[0x26]	288996	1			T12	2		T6	33		T7	46
valid_sources[0x27]	253175	1			T12	12		T4	1		T6	43
valid_sources[0x28]	228661	1			T12	6		T4	2		T6	49
valid_sources[0x29]	343320	1			T12	12		T4	1		T6	47
valid_sources[0x2a]	228775	1			T12	19		T4	2		T6	52
valid_sources[0x2b]	255730	1			T12	2		T20	1		T4	2
valid_sources[0x2c]	227604	1			T4	1		T6	43		T7	15
valid_sources[0x2d]	228485	1			T6	46		T7	49		T11	37
valid_sources[0x2e]	238364	1			T12	8		T4	3		T6	35
valid_sources[0x2f]	229575	1			T12	16		T6	35		T7	37
valid_sources[0x30]	372085	1			T12	15		T4	1		T6	35
valid_sources[0x31]	226912	1			T12	33		T6	36		T7	46
valid_sources[0x32]	226570	1			T12	3		T4	2		T6	46
valid_sources[0x33]	227248	1			T12	1		T4	1		T6	37
valid_sources[0x34]	228705	1			T4	2		T6	34		T7	35
valid_sources[0x35]	854066	1			T12	47		T6	45		T7	34
valid_sources[0x36]	1270695	1			T12	1		T6	35		T7	39
valid_sources[0x37]	224847	1			T12	3		T6	38		T7	31
valid_sources[0x38]	1342077	1			T4	3		T6	21		T7	10
valid_sources[0x39]	334969	1			T12	18		T4	1		T6	47
valid_sources[0x3a]	1141871	1			T12	3		T4	2		T6	41
valid_sources[0x3b]	385185	1			T4	1		T6	38		T7	55
valid_sources[0x3c]	239219	1			T12	4		T4	2		T6	41
valid_sources[0x3d]	237393	1			T12	5		T4	1		T6	40
valid_sources[0x3e]	286309	1			T12	8		T4	1		T6	38
valid_sources[0x3f]	228889	1			T4	1		T6	32		T7	24
valid_sources[0x40]	228477	1			T4	1		T6	35		T7	21
valid_sources[0x41]	227105	1			T12	4		T4	1		T6	38
valid_sources[0x42]	258874	1			T12	16		T6	49		T7	28
valid_sources[0x43]	232572	1			T12	10		T4	1		T6	47
valid_sources[0x44]	228204	1			T12	3		T4	1		T6	50
valid_sources[0x45]	231133	1			T12	10		T4	1		T6	40
valid_sources[0x46]	224772	1			T12	14		T4	1		T6	44
valid_sources[0x47]	232446	1			T4	2		T6	39		T7	16
valid_sources[0x48]	233750	1			T12	12		T6	54		T7	26
valid_sources[0x49]	407250	1			T12	1		T6	45		T7	33
valid_sources[0x4a]	228294	1			T4	1		T6	33		T7	36
valid_sources[0x4b]	232082	1			T12	26		T4	1		T6	34
valid_sources[0x4c]	225532	1			T12	13		T6	44		T7	51
valid_sources[0x4d]	241136	1			T12	1		T6	30		T7	32
valid_sources[0x4e]	244451	1			T12	32		T4	2		T6	37
valid_sources[0x4f]	344419	1			T4	1		T6	32		T7	19
valid_sources[0x50]	228769	1			T12	1		T4	1		T6	38
valid_sources[0x51]	227244	1			T12	12		T6	41		T7	34
valid_sources[0x52]	226814	1			T4	1		T6	42		T7	27
valid_sources[0x53]	246695	1			T12	23		T6	51		T7	46
valid_sources[0x54]	239056	1			T12	3		T4	1		T6	44
valid_sources[0x55]	259497	1			T12	37		T4	1		T6	38
valid_sources[0x56]	249570	1			T12	6		T6	29		T7	43
valid_sources[0x57]	2187857	1			T6	33		T7	31		T11	36
valid_sources[0x58]	230756	1			T4	1		T6	36		T7	44
valid_sources[0x59]	229424	1			T12	1		T4	4		T6	46
valid_sources[0x5a]	623819	1			T4	1		T6	52		T7	28
valid_sources[0x5b]	316243	1			T12	12		T4	3		T6	37
valid_sources[0x5c]	229134	1			T12	2		T6	33		T7	46
valid_sources[0x5d]	231850	1			T12	8		T4	2		T6	51
valid_sources[0x5e]	226689	1			T12	19		T4	2		T6	46
valid_sources[0x5f]	228184	1			T12	20		T6	27		T7	39
valid_sources[0x60]	227403	1			T12	6		T6	43		T7	62
valid_sources[0x61]	227214	1			T4	1		T6	46		T7	33
valid_sources[0x62]	759250	1			T12	3		T6	45		T7	33
valid_sources[0x63]	233933	1			T12	3		T20	1		T4	3
valid_sources[0x64]	2832008	1			T12	7		T4	1		T6	39
valid_sources[0x65]	226103	1			T12	1		T4	1		T6	34
valid_sources[0x66]	223363	1			T12	7		T20	1		T4	1
valid_sources[0x67]	226786	1			T12	2		T20	2		T4	1
valid_sources[0x68]	242437	1			T6	27		T7	27		T11	34
valid_sources[0x69]	229787	1			T12	5		T6	39		T7	37
valid_sources[0x6a]	228680	1			T12	16		T4	3		T6	35
valid_sources[0x6b]	222356	1			T12	5		T6	30		T7	45
valid_sources[0x6c]	524646	1			T12	5		T6	54		T7	13
valid_sources[0x6d]	226986	1			T12	19		T4	2		T6	43
valid_sources[0x6e]	236613	1			T6	46		T7	23		T11	26
valid_sources[0x6f]	227824	1			T4	1		T6	50		T7	33
valid_sources[0x70]	238375	1			T4	2		T6	27		T7	47
valid_sources[0x71]	253873	1			T12	1		T4	2		T6	45
valid_sources[0x72]	369048	1			T12	1		T6	30		T7	42
valid_sources[0x73]	226677	1			T12	2		T20	1		T4	1
valid_sources[0x74]	229776	1			T12	2		T4	2		T6	48
valid_sources[0x75]	229615	1			T12	8		T4	4		T6	38
valid_sources[0x76]	229899	1			T12	4		T6	39		T7	56
valid_sources[0x77]	236967	1			T12	13		T6	35		T7	26
valid_sources[0x78]	228011	1			T12	1		T4	3		T6	39
valid_sources[0x79]	225048	1			T12	3		T4	1		T6	33
valid_sources[0x7a]	225824	1			T12	4		T4	1		T6	48
valid_sources[0x7b]	228975	1			T4	1		T6	22		T7	46
valid_sources[0x7c]	224969	1			T4	2		T6	42		T7	26
valid_sources[0x7d]	226678	1			T12	34		T20	1		T6	59
valid_sources[0x7e]	1162057	1			T12	22		T4	3		T6	43
valid_sources[0x7f]	226016	1			T6	50		T7	33		T11	44
valid_sources[0x80]	234271	1			T12	19		T4	2		T6	44

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19428559

1

T1

898

T2

1

T12

497

values[0x0]

all_enables

biggest_size

10882983

1

T1

1472

T2

3

T12

209

values[0x1]

all_enables

biggest_size

9281487

1

T1

1416

T2

2

T12

187