Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

43235596

1

T1

2307

T2

8

T3

1

full_word

39640580

1

T1

3786

T2

6

T12

893

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	82875756	1			T1	6093		T2	14		T3	1
auto[TlIntgErrCmd]	137	1			T69	5		T70	4		T71	6
auto[TlIntgErrData]	142	1			T69	1		T70	7		T71	10
auto[TlIntgErrBoth]	141	1			T69	4		T70	9		T71	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39622204

1

T1

2701

T2

1

T3

1

auto[1]

43253972

1

T1

3392

T2

13

T12

979

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	20174481	1			T1	1803		T3	1		T12	484
auto[TlIntgErrNone]	partial	auto[1]	23060734	1			T1	504		T2	8		T12	583
auto[TlIntgErrNone]	full_word	auto[0]	19447513	1			T1	898		T2	1		T12	497
auto[TlIntgErrNone]	full_word	auto[1]	20193028	1			T1	2888		T2	5		T12	396
auto[TlIntgErrCmd]	partial	auto[0]	61	1			T69	2		T70	2		T71	2
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T69	3		T70	2		T71	4
auto[TlIntgErrCmd]	full_word	auto[0]	10	1			T134	1		T136	1		T137	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T135	1		T136	1		T137	1
auto[TlIntgErrData]	partial	auto[0]	67	1			T70	1		T71	6		T135	3
auto[TlIntgErrData]	partial	auto[1]	63	1			T69	1		T70	6		T71	4
auto[TlIntgErrData]	full_word	auto[0]	7	1			T133	1		T138	1		T75	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T135	1		T132	1		T136	1
auto[TlIntgErrBoth]	partial	auto[0]	61	1			T69	1		T70	6		T71	1
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T69	2		T70	3		T71	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T75	1		T139	2		T140	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T69	1		T71	1		T132	1