Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	445881600	410670	0	0
intr_enable_rd_A	445881600	2651	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445881600	410670	0	0
T13	324171	3145	0	0
T14	0	8049	0	0
T15	0	2656	0	0
T19	0	13159	0	0
T27	542885	0	0	0
T29	0	7839	0	0
T30	0	17167	0	0
T34	0	3769	0	0
T59	168219	0	0	0
T60	225221	0	0	0
T61	165997	0	0	0
T64	425304	0	0	0
T68	7502	0	0	0
T69	0	2	0	0
T74	0	8406	0	0
T76	0	14155	0	0
T77	1386	0	0	0
T78	223139	0	0	0
T79	600060	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445881600	2651	0	0
T13	324171	33	0	0
T15	0	30	0	0
T19	0	26	0	0
T27	542885	0	0	0
T59	168219	0	0	0
T60	225221	0	0	0
T61	165997	0	0	0
T64	425304	0	0	0
T68	7502	0	0	0
T77	1386	0	0	0
T78	223139	0	0	0
T79	600060	0	0	0
T80	0	35	0	0
T81	0	3	0	0
T82	0	11	0	0
T83	0	13	0	0
T84	0	17	0	0
T85	0	34	0	0
T86	0	85	0	0