Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39607553	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37210804

1

T1

1

T2

1

T3

2803

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36676041	1			T1	1		T2	1		T3	2940
values[0x0]	18844280	1			T1	2		T3	1228		T4	462
values[0x1]	21298036	1			T1	2		T3	1352		T4	494

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30535328	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

46283029

1

T1

1

T2

1

T3

3431

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	218530	1			T3	23		T5	8		T6	19
valid_sources[0x01]	302858	1			T3	25		T4	21		T5	32
valid_sources[0x02]	218628	1			T3	23		T5	10		T6	21
valid_sources[0x03]	218503	1			T3	17		T4	4		T5	12
valid_sources[0x04]	307332	1			T3	20		T4	3		T5	4
valid_sources[0x05]	218315	1			T3	20		T4	71		T5	17
valid_sources[0x06]	217859	1			T3	28		T4	13		T6	25
valid_sources[0x07]	341545	1			T3	25		T5	35		T6	14
valid_sources[0x08]	218986	1			T3	29		T4	13		T5	12
valid_sources[0x09]	221136	1			T3	16		T5	27		T6	20
valid_sources[0x0a]	345221	1			T3	23		T5	9		T6	10
valid_sources[0x0b]	218092	1			T3	16		T5	14		T6	21
valid_sources[0x0c]	286707	1			T3	16		T4	12		T5	27
valid_sources[0x0d]	220204	1			T3	26		T5	13		T6	22
valid_sources[0x0e]	217216	1			T3	23		T4	4		T5	28
valid_sources[0x0f]	574230	1			T3	26		T4	23		T5	9
valid_sources[0x10]	218837	1			T3	26		T5	24		T6	12
valid_sources[0x11]	219886	1			T1	1		T3	20		T4	13
valid_sources[0x12]	218406	1			T3	19		T5	22		T6	17
valid_sources[0x13]	219005	1			T1	1		T3	18		T4	10
valid_sources[0x14]	216611	1			T3	24		T5	9		T6	25
valid_sources[0x15]	982230	1			T3	26		T4	4		T5	26
valid_sources[0x16]	220982	1			T3	22		T5	18		T6	17
valid_sources[0x17]	221849	1			T3	17		T4	3		T5	8
valid_sources[0x18]	220470	1			T3	21		T4	1		T5	9
valid_sources[0x19]	580725	1			T3	28		T4	11		T5	12
valid_sources[0x1a]	220609	1			T3	25		T5	5		T6	15
valid_sources[0x1b]	219376	1			T3	14		T4	9		T5	6
valid_sources[0x1c]	218937	1			T3	24		T5	41		T6	27
valid_sources[0x1d]	218418	1			T3	21		T4	9		T5	20
valid_sources[0x1e]	235447	1			T3	17		T5	6		T6	14
valid_sources[0x1f]	266604	1			T3	24		T4	5		T5	5
valid_sources[0x20]	263857	1			T3	26		T4	8		T5	8
valid_sources[0x21]	315312	1			T3	16		T4	4		T5	8
valid_sources[0x22]	218167	1			T3	22		T4	6		T5	12
valid_sources[0x23]	220750	1			T3	25		T5	24		T6	16
valid_sources[0x24]	218620	1			T3	34		T5	2		T6	25
valid_sources[0x25]	233290	1			T3	33		T5	21		T6	17
valid_sources[0x26]	721856	1			T3	34		T4	5		T5	10
valid_sources[0x27]	217002	1			T3	28		T4	21		T5	29
valid_sources[0x28]	223839	1			T3	19		T5	7		T6	18
valid_sources[0x29]	217661	1			T3	26		T4	16		T5	8
valid_sources[0x2a]	220388	1			T3	23		T4	43		T5	1
valid_sources[0x2b]	218097	1			T3	16		T5	19		T6	11
valid_sources[0x2c]	218614	1			T3	21		T4	3		T5	13
valid_sources[0x2d]	218856	1			T3	20		T5	10		T6	31
valid_sources[0x2e]	219923	1			T3	18		T4	21		T5	11
valid_sources[0x2f]	278044	1			T3	17		T5	23		T6	14
valid_sources[0x30]	218800	1			T3	19		T4	93		T5	2
valid_sources[0x31]	251257	1			T3	18		T4	9		T5	11
valid_sources[0x32]	216634	1			T3	19		T4	4		T5	22
valid_sources[0x33]	301283	1			T3	10		T4	19		T5	28
valid_sources[0x34]	219862	1			T3	13		T4	32		T5	19
valid_sources[0x35]	220489	1			T3	26		T4	5		T5	21
valid_sources[0x36]	270488	1			T3	20		T4	21		T5	8
valid_sources[0x37]	218828	1			T3	21		T5	32		T6	18
valid_sources[0x38]	219676	1			T3	27		T4	14		T5	13
valid_sources[0x39]	672708	1			T3	21		T4	4		T5	8
valid_sources[0x3a]	339988	1			T3	31		T5	17		T6	20
valid_sources[0x3b]	345122	1			T3	14		T5	10		T6	23
valid_sources[0x3c]	220047	1			T3	22		T4	16		T5	10
valid_sources[0x3d]	768327	1			T3	30		T4	2		T5	19
valid_sources[0x3e]	290084	1			T3	27		T5	1		T6	10
valid_sources[0x3f]	217798	1			T3	23		T4	16		T5	16
valid_sources[0x40]	221074	1			T3	20		T5	26		T6	15
valid_sources[0x41]	329702	1			T3	33		T4	3		T5	7
valid_sources[0x42]	360418	1			T3	19		T5	21		T6	14
valid_sources[0x43]	219438	1			T3	22		T4	4		T5	4
valid_sources[0x44]	247263	1			T3	15		T5	4		T6	14
valid_sources[0x45]	219323	1			T3	14		T4	3		T5	47
valid_sources[0x46]	218536	1			T3	18		T4	1		T5	9
valid_sources[0x47]	217502	1			T3	25		T4	4		T5	35
valid_sources[0x48]	220497	1			T3	17		T4	7		T5	4
valid_sources[0x49]	221247	1			T3	24		T5	13		T6	24
valid_sources[0x4a]	1317193	1			T3	23		T4	11		T5	6
valid_sources[0x4b]	311199	1			T3	21		T4	2		T5	16
valid_sources[0x4c]	222353	1			T3	26		T5	28		T6	24
valid_sources[0x4d]	318394	1			T3	18		T4	18		T5	9
valid_sources[0x4e]	219053	1			T3	19		T4	19		T5	10
valid_sources[0x4f]	355430	1			T3	16		T5	4		T6	11
valid_sources[0x50]	240637	1			T3	25		T5	11		T6	15
valid_sources[0x51]	218712	1			T3	15		T4	5		T5	32
valid_sources[0x52]	249709	1			T3	22		T4	13		T5	18
valid_sources[0x53]	512668	1			T3	20		T4	11		T5	15
valid_sources[0x54]	247103	1			T3	20		T4	3		T5	2
valid_sources[0x55]	219231	1			T3	27		T4	23		T5	10
valid_sources[0x56]	218351	1			T3	19		T4	8		T5	27
valid_sources[0x57]	220530	1			T3	17		T5	19		T6	17
valid_sources[0x58]	364927	1			T3	16		T5	32		T6	20
valid_sources[0x59]	266487	1			T3	14		T4	13		T5	21
valid_sources[0x5a]	218564	1			T3	28		T5	4		T6	21
valid_sources[0x5b]	222718	1			T3	30		T5	7		T6	17
valid_sources[0x5c]	286223	1			T3	21		T4	30		T5	2
valid_sources[0x5d]	272502	1			T3	23		T4	12		T5	29
valid_sources[0x5e]	219013	1			T3	26		T4	5		T5	21
valid_sources[0x5f]	218850	1			T3	12		T4	6		T5	7
valid_sources[0x60]	220203	1			T3	26		T5	23		T6	12
valid_sources[0x61]	2158711	1			T3	25		T4	10		T5	8
valid_sources[0x62]	217778	1			T3	19		T5	29		T6	13
valid_sources[0x63]	217736	1			T3	23		T5	7		T6	24
valid_sources[0x64]	216946	1			T3	29		T4	4		T5	10
valid_sources[0x65]	218438	1			T1	2		T3	22		T4	3
valid_sources[0x66]	220502	1			T3	21		T4	1		T5	27
valid_sources[0x67]	221101	1			T3	24		T4	17		T5	1
valid_sources[0x68]	219407	1			T3	26		T4	2		T5	3
valid_sources[0x69]	272873	1			T3	10		T4	97		T5	12
valid_sources[0x6a]	219208	1			T3	26		T4	2		T5	8
valid_sources[0x6b]	218711	1			T3	25		T4	7		T5	30
valid_sources[0x6c]	220066	1			T3	20		T5	9		T6	17
valid_sources[0x6d]	216933	1			T3	16		T4	15		T5	29
valid_sources[0x6e]	218506	1			T3	21		T4	9		T6	13
valid_sources[0x6f]	217666	1			T3	22		T5	38		T6	19
valid_sources[0x70]	220456	1			T3	19		T5	1		T6	26
valid_sources[0x71]	226564	1			T3	27		T4	13		T5	18
valid_sources[0x72]	220337	1			T3	25		T4	2		T5	5
valid_sources[0x73]	217669	1			T3	29		T4	8		T5	16
valid_sources[0x74]	356533	1			T3	18		T4	1		T5	12
valid_sources[0x75]	407536	1			T3	21		T5	10		T6	15
valid_sources[0x76]	217178	1			T3	25		T5	3		T6	18
valid_sources[0x77]	219792	1			T3	21		T5	14		T6	25
valid_sources[0x78]	852530	1			T3	21		T4	5		T5	15
valid_sources[0x79]	219298	1			T3	12		T4	7		T5	4
valid_sources[0x7a]	218448	1			T3	25		T5	1		T6	15
valid_sources[0x7b]	219776	1			T3	24		T5	35		T6	9
valid_sources[0x7c]	219716	1			T3	23		T4	6		T5	21
valid_sources[0x7d]	221149	1			T3	21		T5	17		T6	16
valid_sources[0x7e]	220607	1			T3	16		T4	9		T5	7
valid_sources[0x7f]	219359	1			T3	12		T5	22		T6	17
valid_sources[0x80]	250390	1			T3	19		T5	11		T6	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18124508

1

T1

1

T2

1

T3

1392

values[0x0]

all_enables

biggest_size

10299035

1

T3

745

T4

311

T5

445

values[0x1]

all_enables

biggest_size

8787261

1

T3

666

T4

260

T5

333