Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

41157953

1

T1

4

T3

2717

T4

902

full_word

37311246

1

T1

1

T2

1

T3

2803

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	78468789	1			T1	5		T2	1		T3	5520
auto[TlIntgErrCmd]	134	1			T54	9		T55	6		T56	6
auto[TlIntgErrData]	137	1			T54	12		T55	4		T56	3
auto[TlIntgErrBoth]	139	1			T54	9		T55	10		T56	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37195458

1

T1

1

T2

1

T3

2940

auto[1]

41273741

1

T1

4

T3

2580

T4

956

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	19031245	1			T3	1548		T4	517		T5	968
auto[TlIntgErrNone]	partial	auto[1]	22126332	1			T1	4		T3	1169		T4	385
auto[TlIntgErrNone]	full_word	auto[0]	18164035	1			T1	1		T2	1		T3	1392
auto[TlIntgErrNone]	full_word	auto[1]	19147177	1			T3	1411		T4	571		T5	778
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T54	6		T55	3		T56	2
auto[TlIntgErrCmd]	partial	auto[1]	75	1			T54	3		T55	2		T56	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T133	1		T137	1		T138	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T55	1		T56	3		T133	1
auto[TlIntgErrData]	partial	auto[0]	68	1			T54	6		T55	3		T56	1
auto[TlIntgErrData]	partial	auto[1]	62	1			T54	5		T55	1		T135	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T54	1		T56	1		T139	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T56	1		T140	1		T134	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T54	2		T55	2		T135	1
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T54	6		T55	7		T135	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T54	1		T141	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	12	1			T55	1		T56	1		T142	1