Unified Coverage Report :: Module :: hmac_reg_top

Module : hmac_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.31	100.00	97.23			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.31	100.00	97.23			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.31	100.00	97.23			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.18	93.17	97.71	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_cfg_digest_size	100.00	100.00
u_cfg_digest_swap	100.00	100.00
u_cfg_endian_swap	100.00	100.00
u_cfg_hmac_en	100.00	100.00
u_cfg_key_length	100.00	100.00
u_cfg_key_swap	100.00	100.00
u_cfg_sha_en	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_cmd_hash_continue	100.00	100.00
u_cmd_hash_process	100.00	100.00
u_cmd_hash_start	100.00	100.00
u_cmd_hash_stop	100.00	100.00
u_digest_0	100.00	100.00
u_digest_1	100.00	100.00
u_digest_10	100.00	100.00
u_digest_11	100.00	100.00
u_digest_12	100.00	100.00
u_digest_13	100.00	100.00
u_digest_14	100.00	100.00
u_digest_15	100.00	100.00
u_digest_2	100.00	100.00
u_digest_3	100.00	100.00
u_digest_4	100.00	100.00
u_digest_5	100.00	100.00
u_digest_6	100.00	100.00
u_digest_7	100.00	100.00
u_digest_8	100.00	100.00
u_digest_9	100.00	100.00
u_err_code	100.00	100.00	100.00			100.00
u_intr_enable_fifo_empty	100.00	100.00	100.00			100.00
u_intr_enable_hmac_done	100.00	100.00	100.00			100.00
u_intr_enable_hmac_err	100.00	100.00	100.00			100.00
u_intr_state_fifo_empty	92.59	77.78	100.00			100.00
u_intr_state_hmac_done	100.00	100.00	100.00			100.00
u_intr_state_hmac_err	100.00	100.00	100.00			100.00
u_intr_test_fifo_empty	100.00	100.00
u_intr_test_hmac_done	100.00	100.00
u_intr_test_hmac_err	100.00	100.00
u_key_0	50.00	50.00
u_key_1	50.00	50.00
u_key_10	50.00	50.00
u_key_11	50.00	50.00
u_key_12	50.00	50.00
u_key_13	50.00	50.00
u_key_14	50.00	50.00
u_key_15	50.00	50.00
u_key_16	50.00	50.00
u_key_17	50.00	50.00
u_key_18	50.00	50.00
u_key_19	50.00	50.00
u_key_2	50.00	50.00
u_key_20	50.00	50.00
u_key_21	50.00	50.00
u_key_22	50.00	50.00
u_key_23	50.00	50.00
u_key_24	50.00	50.00
u_key_25	50.00	50.00
u_key_26	50.00	50.00
u_key_27	50.00	50.00
u_key_28	50.00	50.00
u_key_29	50.00	50.00
u_key_3	50.00	50.00
u_key_30	50.00	50.00
u_key_31	50.00	50.00
u_key_4	50.00	50.00
u_key_5	50.00	50.00
u_key_6	50.00	50.00
u_key_7	50.00	50.00
u_key_8	50.00	50.00
u_key_9	50.00	50.00
u_msg_length_lower	100.00	100.00
u_msg_length_upper	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.97	97.14	98.75			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_socket	99.69	98.75	100.00			100.00	100.00
u_status_fifo_depth	100.00	100.00
u_status_fifo_empty	100.00	100.00
u_status_fifo_full	100.00	100.00
u_status_hmac_idle	100.00	100.00
u_wipe_secret	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : hmac_reg_top

	Line No.	Total	Covered	Percent
TOTAL		486	486	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	528	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
CONT_ASSIGN	581	1	1	100.00
CONT_ASSIGN	595	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	616	1	1	100.00
CONT_ASSIGN	632	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	680	1	1	100.00
CONT_ASSIGN	696	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	733	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	765	1	1	100.00
CONT_ASSIGN	781	1	1	100.00
CONT_ASSIGN	877	1	1	100.00
CONT_ASSIGN	891	1	1	100.00
CONT_ASSIGN	898	1	1	100.00
CONT_ASSIGN	912	1	1	100.00
CONT_ASSIGN	919	1	1	100.00
CONT_ASSIGN	933	1	1	100.00
CONT_ASSIGN	940	1	1	100.00
CONT_ASSIGN	954	1	1	100.00
CONT_ASSIGN	961	1	1	100.00
CONT_ASSIGN	975	1	1	100.00
CONT_ASSIGN	982	1	1	100.00
CONT_ASSIGN	996	1	1	100.00
CONT_ASSIGN	1003	1	1	100.00
CONT_ASSIGN	1017	1	1	100.00
CONT_ASSIGN	1024	1	1	100.00
CONT_ASSIGN	1038	1	1	100.00
CONT_ASSIGN	1045	1	1	100.00
CONT_ASSIGN	1059	1	1	100.00
CONT_ASSIGN	1066	1	1	100.00
CONT_ASSIGN	1080	1	1	100.00
CONT_ASSIGN	1087	1	1	100.00
CONT_ASSIGN	1101	1	1	100.00
CONT_ASSIGN	1108	1	1	100.00
CONT_ASSIGN	1122	1	1	100.00
CONT_ASSIGN	1129	1	1	100.00
CONT_ASSIGN	1143	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1164	1	1	100.00
CONT_ASSIGN	1171	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1192	1	1	100.00
CONT_ASSIGN	1206	1	1	100.00
CONT_ASSIGN	1213	1	1	100.00
CONT_ASSIGN	1227	1	1	100.00
CONT_ASSIGN	1234	1	1	100.00
CONT_ASSIGN	1248	1	1	100.00
CONT_ASSIGN	1255	1	1	100.00
CONT_ASSIGN	1269	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1290	1	1	100.00
CONT_ASSIGN	1297	1	1	100.00
CONT_ASSIGN	1311	1	1	100.00
CONT_ASSIGN	1318	1	1	100.00
CONT_ASSIGN	1332	1	1	100.00
CONT_ASSIGN	1339	1	1	100.00
CONT_ASSIGN	1353	1	1	100.00
CONT_ASSIGN	1360	1	1	100.00
CONT_ASSIGN	1374	1	1	100.00
CONT_ASSIGN	1381	1	1	100.00
CONT_ASSIGN	1395	1	1	100.00
CONT_ASSIGN	1402	1	1	100.00
CONT_ASSIGN	1416	1	1	100.00
CONT_ASSIGN	1423	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1444	1	1	100.00
CONT_ASSIGN	1458	1	1	100.00
CONT_ASSIGN	1465	1	1	100.00
CONT_ASSIGN	1479	1	1	100.00
CONT_ASSIGN	1486	1	1	100.00
CONT_ASSIGN	1500	1	1	100.00
CONT_ASSIGN	1507	1	1	100.00
CONT_ASSIGN	1521	1	1	100.00
CONT_ASSIGN	1528	1	1	100.00
CONT_ASSIGN	1542	1	1	100.00
CONT_ASSIGN	1549	1	1	100.00
CONT_ASSIGN	1563	1	1	100.00
CONT_ASSIGN	1570	1	1	100.00
CONT_ASSIGN	1584	1	1	100.00
CONT_ASSIGN	1591	1	1	100.00
CONT_ASSIGN	1605	1	1	100.00
CONT_ASSIGN	1612	1	1	100.00
CONT_ASSIGN	1626	1	1	100.00
CONT_ASSIGN	1633	1	1	100.00
CONT_ASSIGN	1647	1	1	100.00
CONT_ASSIGN	1654	1	1	100.00
CONT_ASSIGN	1668	1	1	100.00
CONT_ASSIGN	1675	1	1	100.00
CONT_ASSIGN	1689	1	1	100.00
CONT_ASSIGN	1696	1	1	100.00
CONT_ASSIGN	1710	1	1	100.00
CONT_ASSIGN	1717	1	1	100.00
CONT_ASSIGN	1731	1	1	100.00
CONT_ASSIGN	1738	1	1	100.00
CONT_ASSIGN	1752	1	1	100.00
CONT_ASSIGN	1759	1	1	100.00
CONT_ASSIGN	1773	1	1	100.00
CONT_ASSIGN	1780	1	1	100.00
CONT_ASSIGN	1794	1	1	100.00
CONT_ASSIGN	1801	1	1	100.00
CONT_ASSIGN	1815	1	1	100.00
CONT_ASSIGN	1822	1	1	100.00
CONT_ASSIGN	1836	1	1	100.00
CONT_ASSIGN	1843	1	1	100.00
CONT_ASSIGN	1857	1	1	100.00
CONT_ASSIGN	1864	1	1	100.00
CONT_ASSIGN	1878	1	1	100.00
CONT_ASSIGN	1885	1	1	100.00
CONT_ASSIGN	1899	1	1	100.00
CONT_ASSIGN	1905	1	1	100.00
CONT_ASSIGN	1919	1	1	100.00
CONT_ASSIGN	1925	1	1	100.00
CONT_ASSIGN	1939	1	1	100.00
ALWAYS	1945	60	60	100.00
CONT_ASSIGN	2007	1	1	100.00
ALWAYS	2011	1	1	100.00
CONT_ASSIGN	2074	1	1	100.00
CONT_ASSIGN	2076	1	1	100.00
CONT_ASSIGN	2078	1	1	100.00
CONT_ASSIGN	2079	1	1	100.00
CONT_ASSIGN	2081	1	1	100.00
CONT_ASSIGN	2083	1	1	100.00
CONT_ASSIGN	2085	1	1	100.00
CONT_ASSIGN	2086	1	1	100.00
CONT_ASSIGN	2088	1	1	100.00
CONT_ASSIGN	2090	1	1	100.00
CONT_ASSIGN	2092	1	1	100.00
CONT_ASSIGN	2093	1	1	100.00
CONT_ASSIGN	2095	1	1	100.00
CONT_ASSIGN	2096	1	1	100.00
CONT_ASSIGN	2097	1	1	100.00
CONT_ASSIGN	2099	1	1	100.00
CONT_ASSIGN	2101	1	1	100.00
CONT_ASSIGN	2103	1	1	100.00
CONT_ASSIGN	2105	1	1	100.00
CONT_ASSIGN	2107	1	1	100.00
CONT_ASSIGN	2109	1	1	100.00
CONT_ASSIGN	2111	1	1	100.00
CONT_ASSIGN	2112	1	1	100.00
CONT_ASSIGN	2114	1	1	100.00
CONT_ASSIGN	2116	1	1	100.00
CONT_ASSIGN	2118	1	1	100.00
CONT_ASSIGN	2120	1	1	100.00
CONT_ASSIGN	2121	1	1	100.00
CONT_ASSIGN	2122	1	1	100.00
CONT_ASSIGN	2124	1	1	100.00
CONT_ASSIGN	2125	1	1	100.00
CONT_ASSIGN	2127	1	1	100.00
CONT_ASSIGN	2128	1	1	100.00
CONT_ASSIGN	2130	1	1	100.00
CONT_ASSIGN	2131	1	1	100.00
CONT_ASSIGN	2133	1	1	100.00
CONT_ASSIGN	2134	1	1	100.00
CONT_ASSIGN	2136	1	1	100.00
CONT_ASSIGN	2137	1	1	100.00
CONT_ASSIGN	2139	1	1	100.00
CONT_ASSIGN	2140	1	1	100.00
CONT_ASSIGN	2142	1	1	100.00
CONT_ASSIGN	2143	1	1	100.00
CONT_ASSIGN	2145	1	1	100.00
CONT_ASSIGN	2146	1	1	100.00
CONT_ASSIGN	2148	1	1	100.00
CONT_ASSIGN	2149	1	1	100.00
CONT_ASSIGN	2151	1	1	100.00
CONT_ASSIGN	2152	1	1	100.00
CONT_ASSIGN	2154	1	1	100.00
CONT_ASSIGN	2155	1	1	100.00
CONT_ASSIGN	2157	1	1	100.00
CONT_ASSIGN	2158	1	1	100.00
CONT_ASSIGN	2160	1	1	100.00
CONT_ASSIGN	2161	1	1	100.00
CONT_ASSIGN	2163	1	1	100.00
CONT_ASSIGN	2164	1	1	100.00
CONT_ASSIGN	2166	1	1	100.00
CONT_ASSIGN	2167	1	1	100.00
CONT_ASSIGN	2169	1	1	100.00
CONT_ASSIGN	2170	1	1	100.00
CONT_ASSIGN	2172	1	1	100.00
CONT_ASSIGN	2173	1	1	100.00
CONT_ASSIGN	2175	1	1	100.00
CONT_ASSIGN	2176	1	1	100.00
CONT_ASSIGN	2178	1	1	100.00
CONT_ASSIGN	2179	1	1	100.00
CONT_ASSIGN	2181	1	1	100.00
CONT_ASSIGN	2182	1	1	100.00
CONT_ASSIGN	2184	1	1	100.00
CONT_ASSIGN	2185	1	1	100.00
CONT_ASSIGN	2187	1	1	100.00
CONT_ASSIGN	2188	1	1	100.00
CONT_ASSIGN	2190	1	1	100.00
CONT_ASSIGN	2191	1	1	100.00
CONT_ASSIGN	2193	1	1	100.00
CONT_ASSIGN	2194	1	1	100.00
CONT_ASSIGN	2196	1	1	100.00
CONT_ASSIGN	2197	1	1	100.00
CONT_ASSIGN	2199	1	1	100.00
CONT_ASSIGN	2200	1	1	100.00
CONT_ASSIGN	2202	1	1	100.00
CONT_ASSIGN	2203	1	1	100.00
CONT_ASSIGN	2205	1	1	100.00
CONT_ASSIGN	2206	1	1	100.00
CONT_ASSIGN	2208	1	1	100.00
CONT_ASSIGN	2209	1	1	100.00
CONT_ASSIGN	2211	1	1	100.00
CONT_ASSIGN	2212	1	1	100.00
CONT_ASSIGN	2214	1	1	100.00
CONT_ASSIGN	2215	1	1	100.00
CONT_ASSIGN	2217	1	1	100.00
CONT_ASSIGN	2218	1	1	100.00
CONT_ASSIGN	2220	1	1	100.00
CONT_ASSIGN	2221	1	1	100.00
CONT_ASSIGN	2222	1	1	100.00
CONT_ASSIGN	2224	1	1	100.00
CONT_ASSIGN	2225	1	1	100.00
CONT_ASSIGN	2226	1	1	100.00
CONT_ASSIGN	2228	1	1	100.00
CONT_ASSIGN	2229	1	1	100.00
CONT_ASSIGN	2230	1	1	100.00
CONT_ASSIGN	2232	1	1	100.00
CONT_ASSIGN	2233	1	1	100.00
CONT_ASSIGN	2234	1	1	100.00
CONT_ASSIGN	2236	1	1	100.00
CONT_ASSIGN	2237	1	1	100.00
CONT_ASSIGN	2238	1	1	100.00
CONT_ASSIGN	2240	1	1	100.00
CONT_ASSIGN	2241	1	1	100.00
CONT_ASSIGN	2242	1	1	100.00
CONT_ASSIGN	2244	1	1	100.00
CONT_ASSIGN	2245	1	1	100.00
CONT_ASSIGN	2246	1	1	100.00
CONT_ASSIGN	2248	1	1	100.00
CONT_ASSIGN	2249	1	1	100.00
CONT_ASSIGN	2250	1	1	100.00
CONT_ASSIGN	2252	1	1	100.00
CONT_ASSIGN	2253	1	1	100.00
CONT_ASSIGN	2254	1	1	100.00
CONT_ASSIGN	2256	1	1	100.00
CONT_ASSIGN	2257	1	1	100.00
CONT_ASSIGN	2258	1	1	100.00
CONT_ASSIGN	2260	1	1	100.00
CONT_ASSIGN	2261	1	1	100.00
CONT_ASSIGN	2262	1	1	100.00
CONT_ASSIGN	2264	1	1	100.00
CONT_ASSIGN	2265	1	1	100.00
CONT_ASSIGN	2266	1	1	100.00
CONT_ASSIGN	2268	1	1	100.00
CONT_ASSIGN	2269	1	1	100.00
CONT_ASSIGN	2270	1	1	100.00
CONT_ASSIGN	2272	1	1	100.00
CONT_ASSIGN	2273	1	1	100.00
CONT_ASSIGN	2274	1	1	100.00
CONT_ASSIGN	2276	1	1	100.00
CONT_ASSIGN	2277	1	1	100.00
CONT_ASSIGN	2278	1	1	100.00
CONT_ASSIGN	2280	1	1	100.00
CONT_ASSIGN	2281	1	1	100.00
CONT_ASSIGN	2282	1	1	100.00
CONT_ASSIGN	2284	1	1	100.00
CONT_ASSIGN	2285	1	1	100.00
CONT_ASSIGN	2286	1	1	100.00
CONT_ASSIGN	2288	1	1	100.00
CONT_ASSIGN	2289	1	1	100.00
CONT_ASSIGN	2290	1	1	100.00
CONT_ASSIGN	2292	1	1	100.00
ALWAYS	2296	60	60	100.00
ALWAYS	2360	79	79	100.00
CONT_ASSIGN	2627	0	0
CONT_ASSIGN	2635	1	1	100.00
CONT_ASSIGN	2636	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Module : hmac_reg_top

	Total	Covered	Percent
Conditions	687	668	97.23
Logical	687	668	97.23
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
63-2011	100.00
2011-2282	95.13
2285-2290	87.50

---

Branch Coverage for Module : hmac_reg_top

	Line No.	Total	Covered	Percent
Branches		69	69	100.00
TERNARY	2007	2	2	100.00
IF	73	3	3	100.00
TERNARY	130	2	2	100.00
IF	136	2	2	100.00
CASE	2361	60	60	100.00

2007         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

73             if (!rst_ni) begin
               -1-  
74               err_q <= '0;
                 ==>
75             end else if (intg_err || reg_we_err) begin
                        -2-  
76               err_q <= 1'b1;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T28,T51
0	0	Covered	T1,T2,T3

130            reg_steer =
                          
131                tl_i.a_address[AW-1:0] inside {[4096:8191]} ? 1'd0 :
                                                               -1-  
                                                               ==>  
                                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

136            if (intg_err) begin
               -1-  
137              reg_steer = 1'd1;
                 ==>
138            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T54,T55,T56
0	Covered	T1,T2,T3

2361           unique case (1'b1)
                      -1-  
2362             addr_hit[0]: begin
2363               reg_rdata_next[0] = intr_state_hmac_done_qs;
                   ==>
2364               reg_rdata_next[1] = intr_state_fifo_empty_qs;
2365               reg_rdata_next[2] = intr_state_hmac_err_qs;
2366             end
2367       
2368             addr_hit[1]: begin
2369               reg_rdata_next[0] = intr_enable_hmac_done_qs;
                   ==>
2370               reg_rdata_next[1] = intr_enable_fifo_empty_qs;
2371               reg_rdata_next[2] = intr_enable_hmac_err_qs;
2372             end
2373       
2374             addr_hit[2]: begin
2375               reg_rdata_next[0] = '0;
                   ==>
2376               reg_rdata_next[1] = '0;
2377               reg_rdata_next[2] = '0;
2378             end
2379       
2380             addr_hit[3]: begin
2381               reg_rdata_next[0] = '0;
                   ==>
2382             end
2383       
2384             addr_hit[4]: begin
2385               reg_rdata_next[0] = cfg_hmac_en_qs;
                   ==>
2386               reg_rdata_next[1] = cfg_sha_en_qs;
2387               reg_rdata_next[2] = cfg_endian_swap_qs;
2388               reg_rdata_next[3] = cfg_digest_swap_qs;
2389               reg_rdata_next[4] = cfg_key_swap_qs;
2390               reg_rdata_next[8:5] = cfg_digest_size_qs;
2391               reg_rdata_next[14:9] = cfg_key_length_qs;
2392             end
2393       
2394             addr_hit[5]: begin
2395               reg_rdata_next[0] = '0;
                   ==>
2396               reg_rdata_next[1] = '0;
2397               reg_rdata_next[2] = '0;
2398               reg_rdata_next[3] = '0;
2399             end
2400       
2401             addr_hit[6]: begin
2402               reg_rdata_next[0] = status_hmac_idle_qs;
                   ==>
2403               reg_rdata_next[1] = status_fifo_empty_qs;
2404               reg_rdata_next[2] = status_fifo_full_qs;
2405               reg_rdata_next[9:4] = status_fifo_depth_qs;
2406             end
2407       
2408             addr_hit[7]: begin
2409               reg_rdata_next[31:0] = err_code_qs;
                   ==>
2410             end
2411       
2412             addr_hit[8]: begin
2413               reg_rdata_next[31:0] = '0;
                   ==>
2414             end
2415       
2416             addr_hit[9]: begin
2417               reg_rdata_next[31:0] = '0;
                   ==>
2418             end
2419       
2420             addr_hit[10]: begin
2421               reg_rdata_next[31:0] = '0;
                   ==>
2422             end
2423       
2424             addr_hit[11]: begin
2425               reg_rdata_next[31:0] = '0;
                   ==>
2426             end
2427       
2428             addr_hit[12]: begin
2429               reg_rdata_next[31:0] = '0;
                   ==>
2430             end
2431       
2432             addr_hit[13]: begin
2433               reg_rdata_next[31:0] = '0;
                   ==>
2434             end
2435       
2436             addr_hit[14]: begin
2437               reg_rdata_next[31:0] = '0;
                   ==>
2438             end
2439       
2440             addr_hit[15]: begin
2441               reg_rdata_next[31:0] = '0;
                   ==>
2442             end
2443       
2444             addr_hit[16]: begin
2445               reg_rdata_next[31:0] = '0;
                   ==>
2446             end
2447       
2448             addr_hit[17]: begin
2449               reg_rdata_next[31:0] = '0;
                   ==>
2450             end
2451       
2452             addr_hit[18]: begin
2453               reg_rdata_next[31:0] = '0;
                   ==>
2454             end
2455       
2456             addr_hit[19]: begin
2457               reg_rdata_next[31:0] = '0;
                   ==>
2458             end
2459       
2460             addr_hit[20]: begin
2461               reg_rdata_next[31:0] = '0;
                   ==>
2462             end
2463       
2464             addr_hit[21]: begin
2465               reg_rdata_next[31:0] = '0;
                   ==>
2466             end
2467       
2468             addr_hit[22]: begin
2469               reg_rdata_next[31:0] = '0;
                   ==>
2470             end
2471       
2472             addr_hit[23]: begin
2473               reg_rdata_next[31:0] = '0;
                   ==>
2474             end
2475       
2476             addr_hit[24]: begin
2477               reg_rdata_next[31:0] = '0;
                   ==>
2478             end
2479       
2480             addr_hit[25]: begin
2481               reg_rdata_next[31:0] = '0;
                   ==>
2482             end
2483       
2484             addr_hit[26]: begin
2485               reg_rdata_next[31:0] = '0;
                   ==>
2486             end
2487       
2488             addr_hit[27]: begin
2489               reg_rdata_next[31:0] = '0;
                   ==>
2490             end
2491       
2492             addr_hit[28]: begin
2493               reg_rdata_next[31:0] = '0;
                   ==>
2494             end
2495       
2496             addr_hit[29]: begin
2497               reg_rdata_next[31:0] = '0;
                   ==>
2498             end
2499       
2500             addr_hit[30]: begin
2501               reg_rdata_next[31:0] = '0;
                   ==>
2502             end
2503       
2504             addr_hit[31]: begin
2505               reg_rdata_next[31:0] = '0;
                   ==>
2506             end
2507       
2508             addr_hit[32]: begin
2509               reg_rdata_next[31:0] = '0;
                   ==>
2510             end
2511       
2512             addr_hit[33]: begin
2513               reg_rdata_next[31:0] = '0;
                   ==>
2514             end
2515       
2516             addr_hit[34]: begin
2517               reg_rdata_next[31:0] = '0;
                   ==>
2518             end
2519       
2520             addr_hit[35]: begin
2521               reg_rdata_next[31:0] = '0;
                   ==>
2522             end
2523       
2524             addr_hit[36]: begin
2525               reg_rdata_next[31:0] = '0;
                   ==>
2526             end
2527       
2528             addr_hit[37]: begin
2529               reg_rdata_next[31:0] = '0;
                   ==>
2530             end
2531       
2532             addr_hit[38]: begin
2533               reg_rdata_next[31:0] = '0;
                   ==>
2534             end
2535       
2536             addr_hit[39]: begin
2537               reg_rdata_next[31:0] = '0;
                   ==>
2538             end
2539       
2540             addr_hit[40]: begin
2541               reg_rdata_next[31:0] = '0;
                   ==>
2542             end
2543       
2544             addr_hit[41]: begin
2545               reg_rdata_next[31:0] = digest_0_qs;
                   ==>
2546             end
2547       
2548             addr_hit[42]: begin
2549               reg_rdata_next[31:0] = digest_1_qs;
                   ==>
2550             end
2551       
2552             addr_hit[43]: begin
2553               reg_rdata_next[31:0] = digest_2_qs;
                   ==>
2554             end
2555       
2556             addr_hit[44]: begin
2557               reg_rdata_next[31:0] = digest_3_qs;
                   ==>
2558             end
2559       
2560             addr_hit[45]: begin
2561               reg_rdata_next[31:0] = digest_4_qs;
                   ==>
2562             end
2563       
2564             addr_hit[46]: begin
2565               reg_rdata_next[31:0] = digest_5_qs;
                   ==>
2566             end
2567       
2568             addr_hit[47]: begin
2569               reg_rdata_next[31:0] = digest_6_qs;
                   ==>
2570             end
2571       
2572             addr_hit[48]: begin
2573               reg_rdata_next[31:0] = digest_7_qs;
                   ==>
2574             end
2575       
2576             addr_hit[49]: begin
2577               reg_rdata_next[31:0] = digest_8_qs;
                   ==>
2578             end
2579       
2580             addr_hit[50]: begin
2581               reg_rdata_next[31:0] = digest_9_qs;
                   ==>
2582             end
2583       
2584             addr_hit[51]: begin
2585               reg_rdata_next[31:0] = digest_10_qs;
                   ==>
2586             end
2587       
2588             addr_hit[52]: begin
2589               reg_rdata_next[31:0] = digest_11_qs;
                   ==>
2590             end
2591       
2592             addr_hit[53]: begin
2593               reg_rdata_next[31:0] = digest_12_qs;
                   ==>
2594             end
2595       
2596             addr_hit[54]: begin
2597               reg_rdata_next[31:0] = digest_13_qs;
                   ==>
2598             end
2599       
2600             addr_hit[55]: begin
2601               reg_rdata_next[31:0] = digest_14_qs;
                   ==>
2602             end
2603       
2604             addr_hit[56]: begin
2605               reg_rdata_next[31:0] = digest_15_qs;
                   ==>
2606             end
2607       
2608             addr_hit[57]: begin
2609               reg_rdata_next[31:0] = msg_length_lower_qs;
                   ==>
2610             end
2611       
2612             addr_hit[58]: begin
2613               reg_rdata_next[31:0] = msg_length_upper_qs;
                   ==>
2614             end
2615       
2616             default: begin
2617               reg_rdata_next = '1;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
addr_hit[38]	Covered	T1,T2,T3
addr_hit[39]	Covered	T1,T2,T3
addr_hit[40]	Covered	T1,T2,T3
addr_hit[41]	Covered	T1,T2,T3
addr_hit[42]	Covered	T1,T2,T3
addr_hit[43]	Covered	T1,T2,T3
addr_hit[44]	Covered	T1,T2,T3
addr_hit[45]	Covered	T1,T2,T3
addr_hit[46]	Covered	T1,T2,T3
addr_hit[47]	Covered	T1,T2,T3
addr_hit[48]	Covered	T1,T2,T3
addr_hit[49]	Covered	T1,T2,T3
addr_hit[50]	Covered	T1,T2,T3
addr_hit[51]	Covered	T1,T2,T3
addr_hit[52]	Covered	T1,T2,T3
addr_hit[53]	Covered	T1,T2,T3
addr_hit[54]	Covered	T1,T2,T3
addr_hit[55]	Covered	T1,T2,T3
addr_hit[56]	Covered	T1,T2,T3
addr_hit[57]	Covered	T1,T2,T3
addr_hit[58]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : hmac_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	445546444	59127673	0	0
reAfterRv	445546444	59127673	0	0
rePulse	445546444	36504111	0	0
wePulse	445546444	22623562	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	445546444	59127673	0	0
T1	654	5	0	0
T2	6740	1	0	0
T3	14831	4588	0	0
T4	5546	1743	0	0
T5	28573	2991	0	0
T6	18176	3661	0	0
T7	67039	7137	0	0
T8	38369	1626	0	0
T27	1543	19	0	0
T28	7772	1	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	445546444	59127673	0	0
T1	654	5	0	0
T2	6740	1	0	0
T3	14831	4588	0	0
T4	5546	1743	0	0
T5	28573	2991	0	0
T6	18176	3661	0	0
T7	67039	7137	0	0
T8	38369	1626	0	0
T27	1543	19	0	0
T28	7772	1	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	445546444	36504111	0	0
T1	654	1	0	0
T2	6740	1	0	0
T3	14831	2940	0	0
T4	5546	1079	0	0
T5	28573	1960	0	0
T6	18176	2423	0	0
T7	67039	4714	0	0
T8	38369	1165	0	0
T27	1543	1	0	0
T28	7772	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	445546444	22623562	0	0
T1	654	4	0	0
T2	6740	0	0	0
T3	14831	1648	0	0
T4	5546	664	0	0
T5	28573	1031	0	0
T6	18176	1238	0	0
T7	67039	2423	0	0
T8	38369	461	0	0
T9	0	944	0	0
T10	0	2171	0	0
T27	1543	18	0	0
T28	7772	0	0	0