Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	445546444	888467	0	0
intr_enable_rd_A	445546444	2537	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445546444	888467	0	0
T19	538614	3012	0	0
T20	0	7685	0	0
T21	0	17082	0	0
T22	0	8037	0	0
T26	0	5989	0	0
T48	645198	0	0	0
T54	0	5	0	0
T55	0	2	0	0
T58	0	1005	0	0
T59	0	923	0	0
T60	0	232	0	0
T61	284404	0	0	0
T62	751	0	0	0
T63	371145	0	0	0
T64	93321	0	0	0
T65	311994	0	0	0
T66	10495	0	0	0
T67	223733	0	0	0
T68	739	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445546444	2537	0	0
T26	133984	47	0	0
T54	0	122	0	0
T57	0	13	0	0
T69	0	10	0	0
T70	0	56	0	0
T71	0	106	0	0
T72	0	102	0	0
T73	0	50	0	0
T74	0	3	0	0
T75	0	21	0	0
T76	32247	0	0	0
T77	39807	0	0	0
T78	140324	0	0	0
T79	115106	0	0	0
T80	416275	0	0	0
T81	32755	0	0	0
T82	109384	0	0	0
T83	792	0	0	0
T84	81705	0	0	0