Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39530866	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36994926

1

T3

1975

T4

2558

T5

6609

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36549633	1			T1	1		T2	1		T3	1942
values[0x0]	18757956	1			T2	1		T3	853		T4	1221
values[0x1]	21218203	1			T2	1		T3	887		T4	1211

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30480218	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

46045574

1

T1

1

T2

1

T3

2383

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	320402	1			T3	6		T4	19		T5	57
valid_sources[0x01]	240570	1			T3	3		T5	68		T9	227
valid_sources[0x02]	237952	1			T3	16		T4	20		T5	52
valid_sources[0x03]	231072	1			T3	4		T5	60		T9	80
valid_sources[0x04]	234662	1			T3	10		T4	11		T5	64
valid_sources[0x05]	230869	1			T3	11		T4	30		T5	55
valid_sources[0x06]	532510	1			T3	17		T5	37		T9	69
valid_sources[0x07]	235820	1			T3	14		T4	19		T5	36
valid_sources[0x08]	235308	1			T3	28		T4	3		T5	69
valid_sources[0x09]	477462	1			T3	12		T4	1		T5	38
valid_sources[0x0a]	229145	1			T3	9		T5	40		T9	113
valid_sources[0x0b]	232966	1			T3	8		T4	7		T5	57
valid_sources[0x0c]	232376	1			T3	26		T4	14		T5	44
valid_sources[0x0d]	304685	1			T3	9		T5	60		T9	164
valid_sources[0x0e]	244570	1			T3	9		T4	9		T5	54
valid_sources[0x0f]	235702	1			T3	6		T5	49		T9	39
valid_sources[0x10]	232866	1			T3	19		T4	26		T5	42
valid_sources[0x11]	282628	1			T3	8		T4	60		T5	52
valid_sources[0x12]	233986	1			T3	20		T4	22		T5	49
valid_sources[0x13]	269684	1			T3	8		T4	20		T5	48
valid_sources[0x14]	231024	1			T3	9		T4	19		T5	58
valid_sources[0x15]	233446	1			T3	12		T4	2		T5	66
valid_sources[0x16]	233154	1			T3	15		T4	14		T5	32
valid_sources[0x17]	233790	1			T3	1		T5	46		T9	116
valid_sources[0x18]	231278	1			T3	15		T5	36		T9	66
valid_sources[0x19]	239883	1			T3	14		T4	73		T5	54
valid_sources[0x1a]	233359	1			T3	9		T4	10		T5	41
valid_sources[0x1b]	233076	1			T3	9		T4	13		T5	50
valid_sources[0x1c]	242996	1			T3	14		T4	61		T5	67
valid_sources[0x1d]	935551	1			T3	11		T4	23		T5	53
valid_sources[0x1e]	316860	1			T3	10		T4	13		T5	70
valid_sources[0x1f]	229871	1			T3	12		T5	47		T28	1
valid_sources[0x20]	231446	1			T3	21		T4	3		T5	44
valid_sources[0x21]	265752	1			T3	13		T4	5		T5	48
valid_sources[0x22]	281765	1			T3	13		T5	71		T9	66
valid_sources[0x23]	255209	1			T3	9		T4	14		T5	50
valid_sources[0x24]	399126	1			T3	23		T4	25		T5	54
valid_sources[0x25]	273549	1			T3	17		T5	55		T9	69
valid_sources[0x26]	232652	1			T3	16		T5	47		T9	87
valid_sources[0x27]	233217	1			T3	22		T4	6		T5	49
valid_sources[0x28]	231731	1			T3	10		T5	41		T9	83
valid_sources[0x29]	279648	1			T3	10		T4	12		T5	50
valid_sources[0x2a]	233067	1			T3	11		T5	44		T9	215
valid_sources[0x2b]	229905	1			T3	13		T4	10		T5	53
valid_sources[0x2c]	235568	1			T3	11		T5	39		T9	137
valid_sources[0x2d]	235489	1			T3	11		T4	16		T5	52
valid_sources[0x2e]	258977	1			T3	18		T4	29		T5	37
valid_sources[0x2f]	297759	1			T3	13		T4	1		T5	53
valid_sources[0x30]	2073480	1			T3	12		T4	28		T5	56
valid_sources[0x31]	237534	1			T4	33		T5	60		T9	127
valid_sources[0x32]	235026	1			T3	19		T4	1		T5	30
valid_sources[0x33]	1262505	1			T3	4		T4	1		T5	52
valid_sources[0x34]	327725	1			T3	18		T4	12		T5	48
valid_sources[0x35]	233477	1			T3	21		T4	24		T5	60
valid_sources[0x36]	231997	1			T3	7		T4	2		T5	49
valid_sources[0x37]	234903	1			T3	16		T4	10		T5	50
valid_sources[0x38]	233518	1			T3	11		T5	44		T9	166
valid_sources[0x39]	232680	1			T3	17		T4	17		T5	43
valid_sources[0x3a]	237400	1			T3	15		T4	15		T5	55
valid_sources[0x3b]	233438	1			T3	26		T4	10		T5	52
valid_sources[0x3c]	238365	1			T3	7		T5	43		T9	118
valid_sources[0x3d]	237068	1			T3	8		T4	13		T5	30
valid_sources[0x3e]	273391	1			T3	13		T4	5		T5	42
valid_sources[0x3f]	438630	1			T3	31		T4	4		T5	36
valid_sources[0x40]	257794	1			T3	24		T5	69		T28	1
valid_sources[0x41]	292550	1			T3	4		T5	60		T9	125
valid_sources[0x42]	377224	1			T3	4		T4	5		T5	36
valid_sources[0x43]	257315	1			T3	8		T5	44		T9	113
valid_sources[0x44]	231071	1			T3	23		T4	6		T5	58
valid_sources[0x45]	234994	1			T3	10		T4	11		T5	60
valid_sources[0x46]	233891	1			T3	13		T5	42		T9	132
valid_sources[0x47]	232697	1			T3	22		T4	31		T5	40
valid_sources[0x48]	247561	1			T3	12		T4	9		T5	54
valid_sources[0x49]	232791	1			T3	17		T4	40		T5	42
valid_sources[0x4a]	232939	1			T3	20		T4	7		T5	46
valid_sources[0x4b]	234442	1			T3	8		T4	5		T5	42
valid_sources[0x4c]	233118	1			T3	6		T5	55		T28	1
valid_sources[0x4d]	232732	1			T3	19		T4	12		T5	59
valid_sources[0x4e]	251620	1			T3	24		T4	33		T5	43
valid_sources[0x4f]	293341	1			T3	16		T4	31		T5	54
valid_sources[0x50]	232257	1			T3	24		T4	40		T5	62
valid_sources[0x51]	233023	1			T3	12		T4	2		T5	47
valid_sources[0x52]	234755	1			T3	18		T4	22		T5	43
valid_sources[0x53]	308825	1			T3	15		T4	8		T5	38
valid_sources[0x54]	235063	1			T3	13		T4	32		T5	62
valid_sources[0x55]	234618	1			T3	11		T4	9		T5	49
valid_sources[0x56]	235966	1			T3	7		T5	54		T9	177
valid_sources[0x57]	1131826	1			T3	17		T5	34		T9	96
valid_sources[0x58]	238421	1			T3	19		T4	13		T5	47
valid_sources[0x59]	235751	1			T3	15		T4	11		T5	43
valid_sources[0x5a]	242640	1			T3	11		T4	10		T5	51
valid_sources[0x5b]	232415	1			T3	20		T4	12		T5	39
valid_sources[0x5c]	232016	1			T3	15		T4	7		T5	49
valid_sources[0x5d]	239797	1			T3	14		T4	30		T5	40
valid_sources[0x5e]	232203	1			T3	22		T5	44		T9	133
valid_sources[0x5f]	233090	1			T3	8		T4	26		T5	61
valid_sources[0x60]	264521	1			T3	4		T5	51		T9	67
valid_sources[0x61]	234393	1			T3	14		T4	8		T5	51
valid_sources[0x62]	233585	1			T3	16		T4	18		T5	57
valid_sources[0x63]	234218	1			T3	17		T4	36		T5	60
valid_sources[0x64]	316329	1			T3	5		T5	42		T9	117
valid_sources[0x65]	232310	1			T3	23		T4	16		T5	59
valid_sources[0x66]	231561	1			T3	9		T4	18		T5	62
valid_sources[0x67]	231793	1			T3	24		T4	5		T5	41
valid_sources[0x68]	232747	1			T3	12		T4	23		T5	49
valid_sources[0x69]	279557	1			T3	13		T4	4		T5	62
valid_sources[0x6a]	232929	1			T3	11		T5	40		T9	121
valid_sources[0x6b]	231738	1			T3	26		T4	2		T5	73
valid_sources[0x6c]	236866	1			T3	5		T5	60		T9	58
valid_sources[0x6d]	233651	1			T3	7		T4	4		T5	64
valid_sources[0x6e]	232858	1			T3	20		T5	37		T9	84
valid_sources[0x6f]	307322	1			T3	6		T4	18		T5	53
valid_sources[0x70]	317308	1			T3	12		T5	51		T9	118
valid_sources[0x71]	235893	1			T3	12		T4	4		T5	60
valid_sources[0x72]	236660	1			T3	3		T4	21		T5	55
valid_sources[0x73]	232934	1			T3	12		T4	6		T5	47
valid_sources[0x74]	265158	1			T3	15		T4	15		T5	56
valid_sources[0x75]	284866	1			T3	11		T4	1		T5	45
valid_sources[0x76]	239947	1			T3	15		T4	31		T5	61
valid_sources[0x77]	275216	1			T3	22		T5	50		T9	126
valid_sources[0x78]	232846	1			T3	31		T4	22		T5	57
valid_sources[0x79]	233141	1			T3	18		T4	6		T5	47
valid_sources[0x7a]	452147	1			T3	2		T4	36		T5	48
valid_sources[0x7b]	237290	1			T1	1		T3	16		T4	17
valid_sources[0x7c]	303011	1			T3	10		T4	10		T5	39
valid_sources[0x7d]	233636	1			T3	1		T5	71		T9	169
valid_sources[0x7e]	230996	1			T3	23		T5	54		T9	147
valid_sources[0x7f]	231946	1			T3	39		T4	35		T5	39
valid_sources[0x80]	236284	1			T3	7		T4	47		T5	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18061345

1

T3

909

T4

217

T5

3207

values[0x0]

all_enables

biggest_size

10220742

1

T3

565

T4

1181

T5

1838

values[0x1]

all_enables

biggest_size

8712839

1

T3

501

T4

1160

T5

1564