Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

40958113

1

T1

1

T2

3

T3

1707

full_word

37087582

1

T3

1975

T4

2558

T5

6609

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	78045315	1			T1	1		T2	3		T3	3682
auto[TlIntgErrCmd]	115	1			T56	1		T57	3		T58	5
auto[TlIntgErrData]	141	1			T56	4		T57	6		T58	3
auto[TlIntgErrBoth]	124	1			T56	5		T57	1		T58	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37026316

1

T1

1

T2

1

T3

1942

auto[1]

41019379

1

T2

2

T3

1740

T4

2432

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18928297	1			T1	1		T2	1		T3	1033
auto[TlIntgErrNone]	partial	auto[1]	22029463	1			T2	2		T3	674		T4	91
auto[TlIntgErrNone]	full_word	auto[0]	18097848	1			T3	909		T4	217		T5	3207
auto[TlIntgErrNone]	full_word	auto[1]	18989707	1			T3	1066		T4	2341		T5	3402
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T56	1		T57	1		T58	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T57	1		T58	4		T128	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T128	1		T126	1		T131	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T57	1		T132	1		T130	1
auto[TlIntgErrData]	partial	auto[0]	65	1			T56	3		T57	2		T58	1
auto[TlIntgErrData]	partial	auto[1]	65	1			T56	1		T57	2		T58	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T57	1		T132	1		T131	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T57	1		T58	1		T129	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T56	1		T58	1		T128	2
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T56	4		T57	1		T58	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T129	1		T133	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T133	1		T134	1		T135	2