Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	435480889	810519	0	0
intr_enable_rd_A	435480889	2921	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435480889	810519	0	0
T20	129015	0	0	0
T21	62368	0	0	0
T23	393717	4611	0	0
T24	0	5963	0	0
T25	0	10860	0	0
T29	42567	0	0	0
T53	89697	0	0	0
T63	0	21765	0	0
T64	0	11138	0	0
T65	0	20548	0	0
T66	0	947	0	0
T67	0	6	0	0
T68	0	186	0	0
T69	0	233	0	0
T70	582045	0	0	0
T71	309855	0	0	0
T72	1669	0	0	0
T73	166228	0	0	0
T74	432879	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435480889	2921	0	0
T20	129015	0	0	0
T21	62368	0	0	0
T23	393717	30	0	0
T25	0	51	0	0
T29	42567	0	0	0
T53	89697	0	0	0
T61	0	19	0	0
T70	582045	0	0	0
T71	309855	0	0	0
T72	1669	0	0	0
T73	166228	0	0	0
T74	432879	0	0	0
T75	0	9	0	0
T76	0	19	0	0
T77	0	74	0	0
T78	0	20	0	0
T79	0	84	0	0
T80	0	43	0	0
T81	0	22	0	0