Unified Coverage Report :: Module :: prim_sha2_32

Module : prim_sha2_32

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.87	87.25	73.97			81.40

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_sha2_512	99.39	100.00	98.18			100.00

---

Module Instance : tb.dut.u_prim_sha2_512

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.39	100.00	98.18			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.47	98.60	96.71		90.00	96.59

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_multimode_logic.u_prim_sha2_multimode	95.07	98.13	96.42		90.00	95.74

Line Coverage for Module : prim_sha2_32

	Line No.	Total	Covered	Percent
TOTAL		102	89	87.25
CONT_ASSIGN	44	1	1	100.00
ALWAYS	65	89	76	85.39
ALWAYS	222	3	3	100.00
ALWAYS	227	3	3	100.00
ALWAYS	232	3	3	100.00
ALWAYS	237	3	3	100.00

43                        // to hash.
44         1/1            assign hash_go = hash_start_i | hash_continue_i;
           Tests:       T1 T2 T3 
45                      
46                        fifoctl_state_e fifo_st;
47                      
48                        // tie off unused ports/port slices
49                        if (!MultimodeEn) begin : gen_tie_unused
50                          logic unused_signals;
51                          assign unused_signals = ^{digest_mode_i, hash_go};
52                        end
53                      
54                        // logic and prim_sha2 instantiation for MultimodeEn = 1
55                        if (MultimodeEn) begin : gen_multimode_logic
56                          // signal definitions for multi-mode
57                          sha_fifo64_t  word_buffer_d, word_buffer_q;
58                          logic [1:0]   word_part_count_d, word_part_count_q;
59                          logic         sha_process, process_flag_d, process_flag_q;
60                          logic         word_valid;
61                          logic         word_part_inc, word_part_reset;
62                          digest_mode_e digest_mode_flag_d, digest_mode_flag_q;
63                      
64                          always_comb begin : multimode_combinational
65         1/1                word_part_inc    = 1'b0;
           Tests:       T1 T2 T3 
66         1/1                word_part_reset  = 1'b0;
           Tests:       T1 T2 T3 
67         1/1                full_word.mask   = 8'hFF; // to keep the padding buffer ready to receive
           Tests:       T1 T2 T3 
68         1/1                full_word.data   = 64'h0;
           Tests:       T1 T2 T3 
69         1/1                sha_process      = 1'b0;
           Tests:       T1 T2 T3 
70         1/1                word_valid       = 1'b0;
           Tests:       T1 T2 T3 
71         1/1                fifo_rready_o    = 1'b0;
           Tests:       T1 T2 T3 
72                      
73                            // assign word_buffer
74         2/2                if (!sha_en_i || hash_go) word_buffer_d = 0;
           Tests:       T1 T2 T3  | T1 T2 T3 
75         1/1                else                      word_buffer_d = word_buffer_q;
           Tests:       T3 T4 T5 
76                      
77         1/1                if (sha_en_i && fifo_rvalid_i) begin // valid incoming word part and SHA engine is enabled
           Tests:       T1 T2 T3 
78         1/1                  if (word_part_count_q == 2'b00) begin
           Tests:       T3 T5 T6 
79         1/1                    if (digest_mode_flag_q != SHA2_256) begin
           Tests:       T3 T5 T6 
80                                  // accumulate most significant 32 bits of word and mask bits
81         1/1                      word_buffer_d.data[63:32] = fifo_rdata_i.data;
           Tests:       T3 T5 T6 
82         1/1                      word_buffer_d.mask[7:4]   = fifo_rdata_i.mask;
           Tests:       T3 T5 T6 
83         1/1                      if (fifo_st == FifoLoadFromFifo) begin
           Tests:       T3 T5 T6 
84         1/1                        fifo_rready_o = 1'b1; // load word from FIFO
           Tests:       T3 T5 T6 
85         1/1                        word_part_inc = 1'b1;
           Tests:       T3 T5 T6 
86                                  end else begin
87         1/1                        fifo_rready_o = 1'b0; // do not load from FIFO
           Tests:       T3 T5 T6 
88         1/1                        word_part_inc = 1'b0;
           Tests:       T3 T5 T6 
89                                  end
90                                end else begin   // SHA2_256 so pad and push out the word
91         1/1                      word_valid = 1'b1;
           Tests:       T3 T5 T7 
92                                  // store the word with most significant padding
93         1/1                      word_buffer_d.data = {32'b0, fifo_rdata_i.data};
           Tests:       T3 T5 T7 
94         1/1                      word_buffer_d.mask = {4'hF, fifo_rdata_i.mask}; // pad with all-1 byte mask
           Tests:       T3 T5 T7 
95                                  // pad with all-zero data and all-one byte masking and push word out already for 256
96         1/1                      full_word.data =  {32'b0, fifo_rdata_i.data};
           Tests:       T3 T5 T7 
97         1/1                      full_word.mask =  {4'hF, fifo_rdata_i.mask};
           Tests:       T3 T5 T7 
98         1/1                      if (hash_process_i || process_flag_q) begin
           Tests:       T3 T5 T7 
99         1/1                          sha_process = 1'b1;
           Tests:       T3 T5 T7 
100                                 end
                        MISSING_ELSE
101        1/1                      if (sha_ready == 1'b1) begin
           Tests:       T3 T5 T7 
102                                   // if word has been absorbed into hash engine
103        1/1                        fifo_rready_o = 1'b1; // word pushed out to SHA engine so word buffer ready
           Tests:       T3 T5 T7 
104                                 end else begin
105        1/1                        fifo_rready_o = 1'b0;
           Tests:       T3 T5 T7 
106                                 end
107                               end
108                     
109        1/1                  end else if (word_part_count_q == 2'b01) begin
           Tests:       T3 T5 T6 
110                               // accumulate least significant 32 bits and mask
111        1/1                    word_buffer_d.data [31:0] = fifo_rdata_i.data;
           Tests:       T3 T5 T6 
112        1/1                    word_buffer_d.mask [3:0]  = fifo_rdata_i.mask;
           Tests:       T3 T5 T6 
113                     
114                               // now ready to pass full word through
115        1/1                    word_valid              = 1'b1;
           Tests:       T3 T5 T6 
116        1/1                    full_word.data [63:32]  = word_buffer_q.data[63:32];
           Tests:       T3 T5 T6 
117        1/1                    full_word.mask [7:4]    = word_buffer_q.mask[7:4];
           Tests:       T3 T5 T6 
118        1/1                    full_word.data [31:0]   = fifo_rdata_i.data;
           Tests:       T3 T5 T6 
119        1/1                    full_word.mask  [3:0]   = fifo_rdata_i.mask;
           Tests:       T3 T5 T6 
120                     
121        1/1                    if (hash_process_i || process_flag_q) begin
           Tests:       T3 T5 T6 
122        1/1                        sha_process = 1'b1;
           Tests:       T3 T5 T6 
123                               end
                        MISSING_ELSE
124        1/1                    if (sha_ready == 1'b1) begin
           Tests:       T3 T5 T6 
125                                 // word has been consumed
126        1/1                      fifo_rready_o     = 1'b1; // word pushed out to SHA engine so word buffer ready
           Tests:       T3 T5 T6 
127        1/1                      word_part_reset   = 1'b1;
           Tests:       T3 T5 T6 
128        1/1                      word_part_inc     = 1'b0;
           Tests:       T3 T5 T6 
129                               end else begin
130        1/1                      fifo_rready_o     = 1'b0;
           Tests:       T3 T5 T6 
131        1/1                      word_part_inc     = 1'b0;
           Tests:       T3 T5 T6 
132                               end
133        0/1     ==>          end else if (word_part_count_q == 2'b10) begin // word buffer is full and not loaded out yet
134                               // fifo_rready_o is now deasserted: accumulated word is waiting to be pushed out
135        0/1     ==>            fifo_rready_o     = 1'b0;
136        0/1     ==>            word_valid        = 1'b1; // word buffer is ready to shift word out to SHA engine
137        0/1     ==>            full_word         = word_buffer_q;
138        0/1     ==>            if (hash_process_i || process_flag_q) begin
139        0/1     ==>                sha_process   = 1'b1;
140                               end
                   ==>  MISSING_ELSE
141        0/1     ==>            if (sha_ready == 1'b1) begin // waiting on sha_ready to turn 1
142                                 // do not assert fifo_rready_o yet
143        0/1     ==>              word_part_reset = 1'b1;
144                               end
                   ==>  MISSING_ELSE
145                             end
                   ==>  MISSING_ELSE
146        1/1                end else if (sha_en_i) begin // hash engine still enabled but no new valid input
           Tests:       T1 T2 T3 
147                             // provide the last latched input so long as hash is enabled
148        1/1                  full_word = word_buffer_q;
           Tests:       T3 T4 T5 
149        1/1                  if (word_part_count_q == 2'b00 && (hash_process_i || process_flag_q)) begin
           Tests:       T3 T4 T5 
150        1/1                    sha_process = 1'b1; // wait on hash_process_i
           Tests:       T3 T4 T5 
151        1/1                  end else if (word_part_count_q == 2'b01 && (hash_process_i || process_flag_q)) begin
           Tests:       T3 T4 T5 
152                               // 384/512: msg ended: apply 32-bit word packing and push last word
153        1/1                    full_word.data [31:0] = 32'b0;
           Tests:       T5 T8 T9 
154        1/1                    full_word.mask [3:0]  = 4'h0;
           Tests:       T5 T8 T9 
155        1/1                    word_valid            = 1'b1;
           Tests:       T5 T8 T9 
156        1/1                    sha_process           = 1'b1;
           Tests:       T5 T8 T9 
157        1/1                    if (sha_ready == 1'b1) begin // word has been consumed
           Tests:       T5 T8 T9 
158        1/1                      word_part_reset = 1'b1; // which will also reset word_valid in the next cycle
           Tests:       T5 T8 T9 
159                               end
                        MISSING_ELSE
160        1/1                  end else if (word_part_count_q == 2'b01) begin // word feeding stalled but msg not ended
           Tests:       T3 T4 T5 
161        1/1                    word_valid = 1'b0;
           Tests:       T3 T5 T6 
162        1/1                  end else if (word_part_count_q == 2'b10 && (hash_process_i || process_flag_q)) begin
           Tests:       T3 T4 T5 
163                               // 384/512: msg ended but last word still waiting to be fed in
164        0/1     ==>            word_valid  = 1'b1;
165        0/1     ==>            sha_process = 1'b1;
166        0/1     ==>            if (sha_ready == 1'b1) begin // word has been consumed
167        0/1     ==>              word_part_reset = 1'b1; // which will also reset word_valid in the next cycle
168                               end
                   ==>  MISSING_ELSE
169        1/1                  end else if (word_part_count_q == 2'b10) begin // word feeding stalled
           Tests:       T3 T4 T5 
170        0/1     ==>            word_valid = 1'b0;
171                             end
                        MISSING_ELSE
172                           end
                        MISSING_ELSE
173                     
174                           // assign word_part_count_d
175        1/1                if ((word_part_reset || hash_go || !sha_en_i)) begin
           Tests:       T1 T2 T3 
176        1/1                  word_part_count_d = '0;
           Tests:       T1 T2 T3 
177        1/1                end else if (word_part_inc) begin
           Tests:       T3 T4 T5 
178        1/1                  word_part_count_d = word_part_count_q + 1'b1;
           Tests:       T3 T5 T6 
179                           end else begin
180        1/1                  word_part_count_d = word_part_count_q;
           Tests:       T3 T4 T5 
181                           end
182                     
183                           // assign digest_mode_flag_d
184        2/2                if (hash_go)          digest_mode_flag_d = digest_mode_i;      // latch in configured mode
           Tests:       T1 T2 T3  | T3 T4 T5 
185        2/2                else if (hash_done_o) digest_mode_flag_d = SHA2_None;          // clear
           Tests:       T1 T2 T3  | T3 T4 T5 
186        1/1                else                  digest_mode_flag_d = digest_mode_flag_q; // keep
           Tests:       T1 T2 T3 
187                     
188                           // assign process_flag
189        2/2                if (!sha_en_i || hash_go) process_flag_d = 1'b0;
           Tests:       T1 T2 T3  | T1 T2 T3 
190        2/2                else if (hash_process_i)  process_flag_d = 1'b1;
           Tests:       T3 T4 T5  | T3 T4 T5 
191        1/1                else                      process_flag_d = process_flag_q;
           Tests:       T3 T4 T5 
192                         end : multimode_combinational
193                     
194                         prim_sha2 #(
195                           .MultimodeEn(1)
196                         ) u_prim_sha2_multimode (
197                           .clk_i (clk_i),
198                           .rst_ni (rst_ni),
199                           .wipe_secret_i      (wipe_secret_i),
200                           .wipe_v_i           (wipe_v_i),
201                           .fifo_rvalid_i      (word_valid),
202                           .fifo_rdata_i       (full_word),
203                           .fifo_rready_o      (sha_ready),
204                           .sha_en_i           (sha_en_i),
205                           .hash_start_i       (hash_start_i),
206                           .hash_stop_i        (hash_stop_i),
207                           .hash_continue_i    (hash_continue_i),
208                           .digest_mode_i      (digest_mode_i),
209                           .hash_process_i     (sha_process),
210                           .hash_done_o        (hash_done_o),
211                           .message_length_i   (message_length_i),
212                           .digest_i           (digest_i),
213                           .digest_we_i        (digest_we_i),
214                           .digest_o           (digest_o),
215                           .digest_on_blk_o    (digest_on_blk_o),
216                           .fifo_st_o          (fifo_st),
217                           .hash_running_o     (hash_running_o),
218                           .idle_o             (idle_o)
219                         );
220                     
221                         always_ff @(posedge clk_i or negedge rst_ni) begin
222        2/2                if (!rst_ni)  word_part_count_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
223        1/1                else          word_part_count_q <= word_part_count_d;
           Tests:       T1 T2 T3 
224                         end
225                     
226                         always_ff @(posedge clk_i or negedge rst_ni) begin
227        2/2                if (!rst_ni)  word_buffer_q <= 0;
           Tests:       T1 T2 T3  | T1 T2 T3 
228        1/1                else          word_buffer_q <= word_buffer_d;
           Tests:       T1 T2 T3 
229                         end
230                     
231                         always_ff @(posedge clk_i or negedge rst_ni) begin
232        2/2               if (!rst_ni)          process_flag_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
233        1/1                else  process_flag_q <= process_flag_d;
           Tests:       T1 T2 T3 
234                         end
235                     
236                         always_ff @(posedge clk_i or negedge rst_ni) begin
237        2/2                if (!rst_ni) digest_mode_flag_q <= SHA2_None;
           Tests:       T1 T2 T3  | T1 T2 T3 
238        1/1                else         digest_mode_flag_q <= digest_mode_flag_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_sha2_32

	Total	Covered	Percent
Conditions	73	54	73.97
Logical	73	54	73.97
Non-Logical	0	0
Event	0	0

 LINE       44
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T4,T5

 LINE       74
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3

 LINE       77
 EXPRESSION (sha_en_i && fifo_rvalid_i)
             ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T5,T6

 LINE       78
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b0)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T3,T5,T6

 LINE       79
 EXPRESSION (gen_multimode_logic.digest_mode_flag_q != SHA2_256)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T5,T7
1	Covered	T3,T5,T6

 LINE       83
 EXPRESSION (fifo_st == FifoLoadFromFifo)
            --------------1--------------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T3,T5,T6

 LINE       98
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T7
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T5,T7

 LINE       101
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T5,T7
1	Covered	T3,T5,T7

 LINE       109
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
            -----------------------1-----------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T5,T6

 LINE       121
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T6
0	1	Covered	T6,T9,T10
1	0	Covered	T3,T5,T6

 LINE       124
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T3,T5,T6

 LINE       133
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
            ------------------------1-----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       138
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       141
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       149
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b0) && (hash_process_i || gen_multimode_logic.process_flag_q))
             -----------------------1-----------------------    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       149
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b0)
                -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T3,T4,T5

 LINE       149
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       151
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b1) && (hash_process_i || gen_multimode_logic.process_flag_q))
             -----------------------1-----------------------    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T5,T6
1	1	Covered	T5,T8,T9

 LINE       151
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
                -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T5,T6

 LINE       151
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9

 LINE       157
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T8,T9
1	Covered	T5,T8,T9

 LINE       160
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T5,T6

 LINE       162
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b10) && (hash_process_i || gen_multimode_logic.process_flag_q))
             ------------------------1-----------------------    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       162
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
                ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Not Covered

 LINE       162
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Not Covered
1	0	Not Covered

 LINE       166
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       169
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Not Covered

 LINE       175
 EXPRESSION (gen_multimode_logic.word_part_reset || hash_go || ((!sha_en_i)))
             -----------------1-----------------    ---2---    ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T3,T4,T5
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T3,T4,T5
1	0	0	Covered	T3,T5,T6

 LINE       189
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_sha2_32

	Line No.	Total	Covered	Percent
Branches		43	35	81.40
IF	74	2	2	100.00
IF	77	24	16	66.67
IF	175	3	3	100.00
IF	184	3	3	100.00
IF	189	3	3	100.00
IF	222	2	2	100.00
IF	227	2	2	100.00
IF	232	2	2	100.00
IF	237	2	2	100.00

74               if (!sha_en_i || hash_go) word_buffer_d = 0;
                 -1-  
                 ==>
75               else                      word_buffer_d = word_buffer_q;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

77               if (sha_en_i && fifo_rvalid_i) begin // valid incoming word part and SHA engine is enabled
                 -1-                 
78                 if (word_part_count_q == 2'b00) begin
                   -2-  
79                   if (digest_mode_flag_q != SHA2_256) begin
                     -3-  
80                     // accumulate most significant 32 bits of word and mask bits
81                     word_buffer_d.data[63:32] = fifo_rdata_i.data;
82                     word_buffer_d.mask[7:4]   = fifo_rdata_i.mask;
83                     if (fifo_st == FifoLoadFromFifo) begin
                       -4-                            
84                       fifo_rready_o = 1'b1; // load word from FIFO
                         ==>
85                       word_part_inc = 1'b1;
86                     end else begin
87                       fifo_rready_o = 1'b0; // do not load from FIFO
                         ==>
88                       word_part_inc = 1'b0;
89                     end
90                   end else begin   // SHA2_256 so pad and push out the word
91                     word_valid = 1'b1;
92                     // store the word with most significant padding
93                     word_buffer_d.data = {32'b0, fifo_rdata_i.data};
94                     word_buffer_d.mask = {4'hF, fifo_rdata_i.mask}; // pad with all-1 byte mask
95                     // pad with all-zero data and all-one byte masking and push word out already for 256
96                     full_word.data =  {32'b0, fifo_rdata_i.data};
97                     full_word.mask =  {4'hF, fifo_rdata_i.mask};
98                     if (hash_process_i || process_flag_q) begin
                       -5-  
99                         sha_process = 1'b1;
                           ==>
100                    end
                       MISSING_ELSE
                       ==>
101                    if (sha_ready == 1'b1) begin
                       -6-  
102                      // if word has been absorbed into hash engine
103                      fifo_rready_o = 1'b1; // word pushed out to SHA engine so word buffer ready
                         ==>
104                    end else begin
105                      fifo_rready_o = 1'b0;
                         ==>
106                    end
107                  end
108        
109                end else if (word_part_count_q == 2'b01) begin
                            -7-  
110                  // accumulate least significant 32 bits and mask
111                  word_buffer_d.data [31:0] = fifo_rdata_i.data;
112                  word_buffer_d.mask [3:0]  = fifo_rdata_i.mask;
113        
114                  // now ready to pass full word through
115                  word_valid              = 1'b1;
116                  full_word.data [63:32]  = word_buffer_q.data[63:32];
117                  full_word.mask [7:4]    = word_buffer_q.mask[7:4];
118                  full_word.data [31:0]   = fifo_rdata_i.data;
119                  full_word.mask  [3:0]   = fifo_rdata_i.mask;
120        
121                  if (hash_process_i || process_flag_q) begin
                     -8-  
122                      sha_process = 1'b1;
                         ==>
123                  end
                     MISSING_ELSE
                     ==>
124                  if (sha_ready == 1'b1) begin
                     -9-  
125                    // word has been consumed
126                    fifo_rready_o     = 1'b1; // word pushed out to SHA engine so word buffer ready
                       ==>
127                    word_part_reset   = 1'b1;
128                    word_part_inc     = 1'b0;
129                  end else begin
130                    fifo_rready_o     = 1'b0;
                       ==>
131                    word_part_inc     = 1'b0;
132                  end
133                end else if (word_part_count_q == 2'b10) begin // word buffer is full and not loaded out yet
                            -10-  
134                  // fifo_rready_o is now deasserted: accumulated word is waiting to be pushed out
135                  fifo_rready_o     = 1'b0;
136                  word_valid        = 1'b1; // word buffer is ready to shift word out to SHA engine
137                  full_word         = word_buffer_q;
138                  if (hash_process_i || process_flag_q) begin
                     -11-  
139                      sha_process   = 1'b1;
                         ==>
140                  end
                     MISSING_ELSE
                     ==>
141                  if (sha_ready == 1'b1) begin // waiting on sha_ready to turn 1
                     -12-  
142                    // do not assert fifo_rready_o yet
143                    word_part_reset = 1'b1;
                       ==>
144                  end
                     MISSING_ELSE
                     ==>
145                end
                   MISSING_ELSE
                   ==>
146              end else if (sha_en_i) begin // hash engine still enabled but no new valid input
                          -13-  
147                // provide the last latched input so long as hash is enabled
148                full_word = word_buffer_q;
149                if (word_part_count_q == 2'b00 && (hash_process_i || process_flag_q)) begin
                   -14-  
150                  sha_process = 1'b1; // wait on hash_process_i
                     ==>
151                end else if (word_part_count_q == 2'b01 && (hash_process_i || process_flag_q)) begin
                            -15-  
152                  // 384/512: msg ended: apply 32-bit word packing and push last word
153                  full_word.data [31:0] = 32'b0;
154                  full_word.mask [3:0]  = 4'h0;
155                  word_valid            = 1'b1;
156                  sha_process           = 1'b1;
157                  if (sha_ready == 1'b1) begin // word has been consumed
                     -16-  
158                    word_part_reset = 1'b1; // which will also reset word_valid in the next cycle
                       ==>
159                  end
                     MISSING_ELSE
                     ==>
160                end else if (word_part_count_q == 2'b01) begin // word feeding stalled but msg not ended
                            -17-  
161                  word_valid = 1'b0;
                     ==>
162                end else if (word_part_count_q == 2'b10 && (hash_process_i || process_flag_q)) begin
                            -18-  
163                  // 384/512: msg ended but last word still waiting to be fed in
164                  word_valid  = 1'b1;
165                  sha_process = 1'b1;
166                  if (sha_ready == 1'b1) begin // word has been consumed
                     -19-  
167                    word_part_reset = 1'b1; // which will also reset word_valid in the next cycle
                       ==>
168                  end
                     MISSING_ELSE
                     ==>
169                end else if (word_part_count_q == 2'b10) begin // word feeding stalled
                            -20-  
170                  word_valid = 1'b0;
                     ==>
171                end
                   MISSING_ELSE
                   ==>
172              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	Status	Tests
1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T6
1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T6
1	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T7
1	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T7
1	1	0	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T7
1	1	0	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T7
1	0	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T6
1	0	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T6
1	0	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T6
1	0	-	-	-	-	1	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T6
1	0	-	-	-	-	0	-	-	1	1	-	-	-	-	-	-	-	-	-	Not Covered
1	0	-	-	-	-	0	-	-	1	0	-	-	-	-	-	-	-	-	-	Not Covered
1	0	-	-	-	-	0	-	-	1	-	1	-	-	-	-	-	-	-	-	Not Covered
1	0	-	-	-	-	0	-	-	1	-	0	-	-	-	-	-	-	-	-	Not Covered
1	0	-	-	-	-	0	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
0	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T3,T4,T5
0	-	-	-	-	-	-	-	-	-	-	-	1	0	1	1	-	-	-	-	Covered	T5,T8,T9
0	-	-	-	-	-	-	-	-	-	-	-	1	0	1	0	-	-	-	-	Covered	T5,T8,T9
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	1	-	-	-	Covered	T3,T5,T6
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	1	1	-	Not Covered
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	1	0	-	Not Covered
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	0	-	1	Not Covered
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	0	-	0	Covered	T3,T4,T5
0	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3

175              if ((word_part_reset || hash_go || !sha_en_i)) begin
                 -1-  
176                word_part_count_d = '0;
                   ==>
177              end else if (word_part_inc) begin
                          -2-  
178                word_part_count_d = word_part_count_q + 1'b1;
                   ==>
179              end else begin
180                word_part_count_d = word_part_count_q;
                   ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
0	0	Covered	T3,T4,T5

184              if (hash_go)          digest_mode_flag_d = digest_mode_i;      // latch in configured mode
                 -1-  
                 ==>
185              else if (hash_done_o) digest_mode_flag_d = SHA2_None;          // clear
                      -2-  
                 ==>
186              else                  digest_mode_flag_d = digest_mode_flag_q; // keep
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
0	0	Covered	T1,T2,T3

189              if (!sha_en_i || hash_go) process_flag_d = 1'b0;
                 -1-  
                 ==>
190              else if (hash_process_i)  process_flag_d = 1'b1;
                      -2-  
                 ==>
191              else                      process_flag_d = process_flag_q;
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
0	0	Covered	T3,T4,T5

222              if (!rst_ni)  word_part_count_q <= '0;
                 -1-  
                 ==>
223              else          word_part_count_q <= word_part_count_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

227              if (!rst_ni)  word_buffer_q <= 0;
                 -1-  
                 ==>
228              else          word_buffer_q <= word_buffer_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

232             if (!rst_ni)          process_flag_q <= '0;
                -1-  
                ==>
233              else  process_flag_q <= process_flag_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

237              if (!rst_ni) digest_mode_flag_q <= SHA2_None;
                 -1-  
                 ==>
238              else         digest_mode_flag_q <= digest_mode_flag_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_sha2_512

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	65	76	76	100.00
ALWAYS	222	3	3	100.00
ALWAYS	227	3	3	100.00
ALWAYS	232	3	3	100.00
ALWAYS	237	3	3	100.00

43                        // to hash.
44         1/1            assign hash_go = hash_start_i | hash_continue_i;
           Tests:       T1 T2 T3 
45                      
46                        fifoctl_state_e fifo_st;
47                      
48                        // tie off unused ports/port slices
49                        if (!MultimodeEn) begin : gen_tie_unused
50                          logic unused_signals;
51                          assign unused_signals = ^{digest_mode_i, hash_go};
52                        end
53                      
54                        // logic and prim_sha2 instantiation for MultimodeEn = 1
55                        if (MultimodeEn) begin : gen_multimode_logic
56                          // signal definitions for multi-mode
57                          sha_fifo64_t  word_buffer_d, word_buffer_q;
58                          logic [1:0]   word_part_count_d, word_part_count_q;
59                          logic         sha_process, process_flag_d, process_flag_q;
60                          logic         word_valid;
61                          logic         word_part_inc, word_part_reset;
62                          digest_mode_e digest_mode_flag_d, digest_mode_flag_q;
63                      
64                          always_comb begin : multimode_combinational
65         1/1                word_part_inc    = 1'b0;
           Tests:       T1 T2 T3 
66         1/1                word_part_reset  = 1'b0;
           Tests:       T1 T2 T3 
67         1/1                full_word.mask   = 8'hFF; // to keep the padding buffer ready to receive
           Tests:       T1 T2 T3 
68         1/1                full_word.data   = 64'h0;
           Tests:       T1 T2 T3 
69         1/1                sha_process      = 1'b0;
           Tests:       T1 T2 T3 
70         1/1                word_valid       = 1'b0;
           Tests:       T1 T2 T3 
71         1/1                fifo_rready_o    = 1'b0;
           Tests:       T1 T2 T3 
72                      
73                            // assign word_buffer
74         2/2                if (!sha_en_i || hash_go) word_buffer_d = 0;
           Tests:       T1 T2 T3  | T1 T2 T3 
75         1/1                else                      word_buffer_d = word_buffer_q;
           Tests:       T3 T4 T5 
76                      
77         1/1                if (sha_en_i && fifo_rvalid_i) begin // valid incoming word part and SHA engine is enabled
           Tests:       T1 T2 T3 
78         1/1                  if (word_part_count_q == 2'b00) begin
           Tests:       T3 T5 T6 
79         1/1                    if (digest_mode_flag_q != SHA2_256) begin
           Tests:       T3 T5 T6 
80                                  // accumulate most significant 32 bits of word and mask bits
81         1/1                      word_buffer_d.data[63:32] = fifo_rdata_i.data;
           Tests:       T3 T5 T6 
82         1/1                      word_buffer_d.mask[7:4]   = fifo_rdata_i.mask;
           Tests:       T3 T5 T6 
83         1/1                      if (fifo_st == FifoLoadFromFifo) begin
           Tests:       T3 T5 T6 
84         1/1                        fifo_rready_o = 1'b1; // load word from FIFO
           Tests:       T3 T5 T6 
85         1/1                        word_part_inc = 1'b1;
           Tests:       T3 T5 T6 
86                                  end else begin
87         1/1                        fifo_rready_o = 1'b0; // do not load from FIFO
           Tests:       T3 T5 T6 
88         1/1                        word_part_inc = 1'b0;
           Tests:       T3 T5 T6 
89                                  end
90                                end else begin   // SHA2_256 so pad and push out the word
91         1/1                      word_valid = 1'b1;
           Tests:       T3 T5 T7 
92                                  // store the word with most significant padding
93         1/1                      word_buffer_d.data = {32'b0, fifo_rdata_i.data};
           Tests:       T3 T5 T7 
94         1/1                      word_buffer_d.mask = {4'hF, fifo_rdata_i.mask}; // pad with all-1 byte mask
           Tests:       T3 T5 T7 
95                                  // pad with all-zero data and all-one byte masking and push word out already for 256
96         1/1                      full_word.data =  {32'b0, fifo_rdata_i.data};
           Tests:       T3 T5 T7 
97         1/1                      full_word.mask =  {4'hF, fifo_rdata_i.mask};
           Tests:       T3 T5 T7 
98         1/1                      if (hash_process_i || process_flag_q) begin
           Tests:       T3 T5 T7 
99         1/1                          sha_process = 1'b1;
           Tests:       T3 T5 T7 
100                                 end
                        MISSING_ELSE
101        1/1                      if (sha_ready == 1'b1) begin
           Tests:       T3 T5 T7 
102                                   // if word has been absorbed into hash engine
103        1/1                        fifo_rready_o = 1'b1; // word pushed out to SHA engine so word buffer ready
           Tests:       T3 T5 T7 
104                                 end else begin
105        1/1                        fifo_rready_o = 1'b0;
           Tests:       T3 T5 T7 
106                                 end
107                               end
108                     
109        1/1                  end else if (word_part_count_q == 2'b01) begin
           Tests:       T3 T5 T6 
110                               // accumulate least significant 32 bits and mask
111        1/1                    word_buffer_d.data [31:0] = fifo_rdata_i.data;
           Tests:       T3 T5 T6 
112        1/1                    word_buffer_d.mask [3:0]  = fifo_rdata_i.mask;
           Tests:       T3 T5 T6 
113                     
114                               // now ready to pass full word through
115        1/1                    word_valid              = 1'b1;
           Tests:       T3 T5 T6 
116        1/1                    full_word.data [63:32]  = word_buffer_q.data[63:32];
           Tests:       T3 T5 T6 
117        1/1                    full_word.mask [7:4]    = word_buffer_q.mask[7:4];
           Tests:       T3 T5 T6 
118        1/1                    full_word.data [31:0]   = fifo_rdata_i.data;
           Tests:       T3 T5 T6 
119        1/1                    full_word.mask  [3:0]   = fifo_rdata_i.mask;
           Tests:       T3 T5 T6 
120                     
121        1/1                    if (hash_process_i || process_flag_q) begin
           Tests:       T3 T5 T6 
122        1/1                        sha_process = 1'b1;
           Tests:       T3 T5 T6 
123                               end
                        MISSING_ELSE
124        1/1                    if (sha_ready == 1'b1) begin
           Tests:       T3 T5 T6 
125                                 // word has been consumed
126        1/1                      fifo_rready_o     = 1'b1; // word pushed out to SHA engine so word buffer ready
           Tests:       T3 T5 T6 
127        1/1                      word_part_reset   = 1'b1;
           Tests:       T3 T5 T6 
128        1/1                      word_part_inc     = 1'b0;
           Tests:       T3 T5 T6 
129                               end else begin
130        1/1                      fifo_rready_o     = 1'b0;
           Tests:       T3 T5 T6 
131        1/1                      word_part_inc     = 1'b0;
           Tests:       T3 T5 T6 
132                               end
133        excluded             end else if (word_part_count_q == 2'b10) begin // word buffer is full and not loaded out yet
Exclude Annotation: VC_COV_UNR
134                               // fifo_rready_o is now deasserted: accumulated word is waiting to be pushed out
135        excluded               fifo_rready_o     = 1'b0;
Exclude Annotation: VC_COV_UNR
136        excluded               word_valid        = 1'b1; // word buffer is ready to shift word out to SHA engine
Exclude Annotation: VC_COV_UNR
137        excluded               full_word         = word_buffer_q;
Exclude Annotation: VC_COV_UNR
138        excluded               if (hash_process_i || process_flag_q) begin
Exclude Annotation: VC_COV_UNR
139        excluded                   sha_process   = 1'b1;
Exclude Annotation: VC_COV_UNR
140                               end
                   ==>  MISSING_ELSE
141        excluded               if (sha_ready == 1'b1) begin // waiting on sha_ready to turn 1
Exclude Annotation: VC_COV_UNR
142                                 // do not assert fifo_rready_o yet
143        excluded                 word_part_reset = 1'b1;
Exclude Annotation: VC_COV_UNR
144                               end
                   ==>  MISSING_ELSE
145                             end
                   ==>  MISSING_ELSE
146        1/1                end else if (sha_en_i) begin // hash engine still enabled but no new valid input
           Tests:       T1 T2 T3 
147                             // provide the last latched input so long as hash is enabled
148        1/1                  full_word = word_buffer_q;
           Tests:       T3 T4 T5 
149        1/1                  if (word_part_count_q == 2'b00 && (hash_process_i || process_flag_q)) begin
           Tests:       T3 T4 T5 
150        1/1                    sha_process = 1'b1; // wait on hash_process_i
           Tests:       T3 T4 T5 
151        1/1                  end else if (word_part_count_q == 2'b01 && (hash_process_i || process_flag_q)) begin
           Tests:       T3 T4 T5 
152                               // 384/512: msg ended: apply 32-bit word packing and push last word
153        1/1                    full_word.data [31:0] = 32'b0;
           Tests:       T5 T8 T9 
154        1/1                    full_word.mask [3:0]  = 4'h0;
           Tests:       T5 T8 T9 
155        1/1                    word_valid            = 1'b1;
           Tests:       T5 T8 T9 
156        1/1                    sha_process           = 1'b1;
           Tests:       T5 T8 T9 
157        1/1                    if (sha_ready == 1'b1) begin // word has been consumed
           Tests:       T5 T8 T9 
158        1/1                      word_part_reset = 1'b1; // which will also reset word_valid in the next cycle
           Tests:       T5 T8 T9 
159                               end
                        MISSING_ELSE
160        1/1                  end else if (word_part_count_q == 2'b01) begin // word feeding stalled but msg not ended
           Tests:       T3 T4 T5 
161        1/1                    word_valid = 1'b0;
           Tests:       T3 T5 T6 
162        1/1                  end else if (word_part_count_q == 2'b10 && (hash_process_i || process_flag_q)) begin
           Tests:       T3 T4 T5 
163                               // 384/512: msg ended but last word still waiting to be fed in
164        excluded               word_valid  = 1'b1;
Exclude Annotation: VC_COV_UNR
165        excluded               sha_process = 1'b1;
Exclude Annotation: VC_COV_UNR
166        excluded               if (sha_ready == 1'b1) begin // word has been consumed
Exclude Annotation: VC_COV_UNR
167        excluded                 word_part_reset = 1'b1; // which will also reset word_valid in the next cycle
Exclude Annotation: VC_COV_UNR
168                               end
                   ==>  MISSING_ELSE
169        1/1                  end else if (word_part_count_q == 2'b10) begin // word feeding stalled
           Tests:       T3 T4 T5 
170        excluded               word_valid = 1'b0;
Exclude Annotation: VC_COV_UNR
171                             end
                        MISSING_ELSE
172                           end
                        MISSING_ELSE
173                     
174                           // assign word_part_count_d
175        1/1                if ((word_part_reset || hash_go || !sha_en_i)) begin
           Tests:       T1 T2 T3 
176        1/1                  word_part_count_d = '0;
           Tests:       T1 T2 T3 
177        1/1                end else if (word_part_inc) begin
           Tests:       T3 T4 T5 
178        1/1                  word_part_count_d = word_part_count_q + 1'b1;
           Tests:       T3 T5 T6 
179                           end else begin
180        1/1                  word_part_count_d = word_part_count_q;
           Tests:       T3 T4 T5 
181                           end
182                     
183                           // assign digest_mode_flag_d
184        2/2                if (hash_go)          digest_mode_flag_d = digest_mode_i;      // latch in configured mode
           Tests:       T1 T2 T3  | T3 T4 T5 
185        2/2                else if (hash_done_o) digest_mode_flag_d = SHA2_None;          // clear
           Tests:       T1 T2 T3  | T3 T4 T5 
186        1/1                else                  digest_mode_flag_d = digest_mode_flag_q; // keep
           Tests:       T1 T2 T3 
187                     
188                           // assign process_flag
189        2/2                if (!sha_en_i || hash_go) process_flag_d = 1'b0;
           Tests:       T1 T2 T3  | T1 T2 T3 
190        2/2                else if (hash_process_i)  process_flag_d = 1'b1;
           Tests:       T3 T4 T5  | T3 T4 T5 
191        1/1                else                      process_flag_d = process_flag_q;
           Tests:       T3 T4 T5 
192                         end : multimode_combinational
193                     
194                         prim_sha2 #(
195                           .MultimodeEn(1)
196                         ) u_prim_sha2_multimode (
197                           .clk_i (clk_i),
198                           .rst_ni (rst_ni),
199                           .wipe_secret_i      (wipe_secret_i),
200                           .wipe_v_i           (wipe_v_i),
201                           .fifo_rvalid_i      (word_valid),
202                           .fifo_rdata_i       (full_word),
203                           .fifo_rready_o      (sha_ready),
204                           .sha_en_i           (sha_en_i),
205                           .hash_start_i       (hash_start_i),
206                           .hash_stop_i        (hash_stop_i),
207                           .hash_continue_i    (hash_continue_i),
208                           .digest_mode_i      (digest_mode_i),
209                           .hash_process_i     (sha_process),
210                           .hash_done_o        (hash_done_o),
211                           .message_length_i   (message_length_i),
212                           .digest_i           (digest_i),
213                           .digest_we_i        (digest_we_i),
214                           .digest_o           (digest_o),
215                           .digest_on_blk_o    (digest_on_blk_o),
216                           .fifo_st_o          (fifo_st),
217                           .hash_running_o     (hash_running_o),
218                           .idle_o             (idle_o)
219                         );
220                     
221                         always_ff @(posedge clk_i or negedge rst_ni) begin
222        2/2                if (!rst_ni)  word_part_count_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
223        1/1                else          word_part_count_q <= word_part_count_d;
           Tests:       T1 T2 T3 
224                         end
225                     
226                         always_ff @(posedge clk_i or negedge rst_ni) begin
227        2/2                if (!rst_ni)  word_buffer_q <= 0;
           Tests:       T1 T2 T3  | T1 T2 T3 
228        1/1                else          word_buffer_q <= word_buffer_d;
           Tests:       T1 T2 T3 
229                         end
230                     
231                         always_ff @(posedge clk_i or negedge rst_ni) begin
232        2/2               if (!rst_ni)          process_flag_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
233        1/1                else  process_flag_q <= process_flag_d;
           Tests:       T1 T2 T3 
234                         end
235                     
236                         always_ff @(posedge clk_i or negedge rst_ni) begin
237        2/2                if (!rst_ni) digest_mode_flag_q <= SHA2_None;
           Tests:       T1 T2 T3  | T1 T2 T3 
238        1/1                else         digest_mode_flag_q <= digest_mode_flag_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_sha2_512

	Total	Covered	Percent
Conditions	55	54	98.18
Logical	55	54	98.18
Non-Logical	0	0
Event	0	0

 LINE       44
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T4,T5

 LINE       74
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3

 LINE       77
 EXPRESSION (sha_en_i && fifo_rvalid_i)
             ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T5,T6

 LINE       78
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b0)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T3,T5,T6

 LINE       79
 EXPRESSION (gen_multimode_logic.digest_mode_flag_q != SHA2_256)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T5,T7
1	Covered	T3,T5,T6

 LINE       83
 EXPRESSION (fifo_st == FifoLoadFromFifo)
            --------------1--------------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T3,T5,T6

 LINE       98
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T7
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T5,T7

 LINE       101
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T5,T7
1	Covered	T3,T5,T7

 LINE       109
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
            -----------------------1-----------------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T3,T5,T6

 LINE       121
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T6
0	1	Covered	T6,T9,T10
1	0	Covered	T3,T5,T6

 LINE       124
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T3,T5,T6

 LINE       133
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
            ------------------------1-----------------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Excluded		VC_COV_UNR

 LINE       138
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Excluded		VC_COV_UNR
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR

 LINE       141
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Excluded		VC_COV_UNR

 LINE       149
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b0) && (hash_process_i || gen_multimode_logic.process_flag_q))
             -----------------------1-----------------------    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       149
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b0)
                -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T3,T4,T5

 LINE       149
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       151
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b1) && (hash_process_i || gen_multimode_logic.process_flag_q))
             -----------------------1-----------------------    ---------------------------2--------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T5,T6
1	1	Covered	T5,T8,T9

 LINE       151
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
                -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T5,T6

 LINE       151
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9

 LINE       157
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T8,T9
1	Covered	T5,T8,T9

 LINE       160
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T5,T6

 LINE       162
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b10) && (hash_process_i || gen_multimode_logic.process_flag_q))
             ------------------------1-----------------------    ---------------------------2--------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       162
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
                ------------------------1-----------------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T3,T4,T5
1	Excluded		VC_COV_UNR

 LINE       162
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T3,T4,T5
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR

 LINE       166
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Excluded		VC_COV_UNR

 LINE       169
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
            ------------------------1-----------------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T3,T4,T5
1	Excluded		VC_COV_UNR

 LINE       175
 EXPRESSION (gen_multimode_logic.word_part_reset || hash_go || ((!sha_en_i)))
             -----------------1-----------------    ---2---    ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T3,T4,T5
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T3,T4,T5
1	0	0	Covered	T3,T5,T6

 LINE       189
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_prim_sha2_512

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
IF	74	2	2	100.00
IF	77	16	16	100.00
IF	175	3	3	100.00
IF	184	3	3	100.00
IF	189	3	3	100.00
IF	222	2	2	100.00
IF	227	2	2	100.00
IF	232	2	2	100.00
IF	237	2	2	100.00

74               if (!sha_en_i || hash_go) word_buffer_d = 0;
                 -1-  
                 ==>
75               else                      word_buffer_d = word_buffer_q;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

77               if (sha_en_i && fifo_rvalid_i) begin // valid incoming word part and SHA engine is enabled
                 -1-                 
78                 if (word_part_count_q == 2'b00) begin
                   -2-  
79                   if (digest_mode_flag_q != SHA2_256) begin
                     -3-  
80                     // accumulate most significant 32 bits of word and mask bits
81                     word_buffer_d.data[63:32] = fifo_rdata_i.data;
82                     word_buffer_d.mask[7:4]   = fifo_rdata_i.mask;
83                     if (fifo_st == FifoLoadFromFifo) begin
                       -4-                            
84                       fifo_rready_o = 1'b1; // load word from FIFO
                         ==>
85                       word_part_inc = 1'b1;
86                     end else begin
87                       fifo_rready_o = 1'b0; // do not load from FIFO
                         ==>
88                       word_part_inc = 1'b0;
89                     end
90                   end else begin   // SHA2_256 so pad and push out the word
91                     word_valid = 1'b1;
92                     // store the word with most significant padding
93                     word_buffer_d.data = {32'b0, fifo_rdata_i.data};
94                     word_buffer_d.mask = {4'hF, fifo_rdata_i.mask}; // pad with all-1 byte mask
95                     // pad with all-zero data and all-one byte masking and push word out already for 256
96                     full_word.data =  {32'b0, fifo_rdata_i.data};
97                     full_word.mask =  {4'hF, fifo_rdata_i.mask};
98                     if (hash_process_i || process_flag_q) begin
                       -5-  
99                         sha_process = 1'b1;
                           ==>
100                    end
                       MISSING_ELSE
                       ==>
101                    if (sha_ready == 1'b1) begin
                       -6-  
102                      // if word has been absorbed into hash engine
103                      fifo_rready_o = 1'b1; // word pushed out to SHA engine so word buffer ready
                         ==>
104                    end else begin
105                      fifo_rready_o = 1'b0;
                         ==>
106                    end
107                  end
108        
109                end else if (word_part_count_q == 2'b01) begin
                            -7-  
110                  // accumulate least significant 32 bits and mask
111                  word_buffer_d.data [31:0] = fifo_rdata_i.data;
112                  word_buffer_d.mask [3:0]  = fifo_rdata_i.mask;
113        
114                  // now ready to pass full word through
115                  word_valid              = 1'b1;
116                  full_word.data [63:32]  = word_buffer_q.data[63:32];
117                  full_word.mask [7:4]    = word_buffer_q.mask[7:4];
118                  full_word.data [31:0]   = fifo_rdata_i.data;
119                  full_word.mask  [3:0]   = fifo_rdata_i.mask;
120        
121                  if (hash_process_i || process_flag_q) begin
                     -8-  
122                      sha_process = 1'b1;
                         ==>
123                  end
                     MISSING_ELSE
                     ==>
124                  if (sha_ready == 1'b1) begin
                     -9-  
125                    // word has been consumed
126                    fifo_rready_o     = 1'b1; // word pushed out to SHA engine so word buffer ready
                       ==>
127                    word_part_reset   = 1'b1;
128                    word_part_inc     = 1'b0;
129                  end else begin
130                    fifo_rready_o     = 1'b0;
                       ==>
131                    word_part_inc     = 1'b0;
132                  end
133                end else if (word_part_count_q == 2'b10) begin // word buffer is full and not loaded out yet
                            -10-  
134                  // fifo_rready_o is now deasserted: accumulated word is waiting to be pushed out
135                  fifo_rready_o     = 1'b0;
136                  word_valid        = 1'b1; // word buffer is ready to shift word out to SHA engine
137                  full_word         = word_buffer_q;
138                  if (hash_process_i || process_flag_q) begin
                     -11-  
139                      sha_process   = 1'b1;
                         ==> (Excluded)
Exclude Annotation: VC_COV_UNR
140                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
141                  if (sha_ready == 1'b1) begin // waiting on sha_ready to turn 1
                     -12-  
142                    // do not assert fifo_rready_o yet
143                    word_part_reset = 1'b1;
                       ==> (Excluded)
Exclude Annotation: VC_COV_UNR
144                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
145                end
                   MISSING_ELSE
                   ==> (Excluded)
Exclude Annotation: VC_COV_UNR
146              end else if (sha_en_i) begin // hash engine still enabled but no new valid input
                          -13-  
147                // provide the last latched input so long as hash is enabled
148                full_word = word_buffer_q;
149                if (word_part_count_q == 2'b00 && (hash_process_i || process_flag_q)) begin
                   -14-  
150                  sha_process = 1'b1; // wait on hash_process_i
                     ==>
151                end else if (word_part_count_q == 2'b01 && (hash_process_i || process_flag_q)) begin
                            -15-  
152                  // 384/512: msg ended: apply 32-bit word packing and push last word
153                  full_word.data [31:0] = 32'b0;
154                  full_word.mask [3:0]  = 4'h0;
155                  word_valid            = 1'b1;
156                  sha_process           = 1'b1;
157                  if (sha_ready == 1'b1) begin // word has been consumed
                     -16-  
158                    word_part_reset = 1'b1; // which will also reset word_valid in the next cycle
                       ==>
159                  end
                     MISSING_ELSE
                     ==>
160                end else if (word_part_count_q == 2'b01) begin // word feeding stalled but msg not ended
                            -17-  
161                  word_valid = 1'b0;
                     ==>
162                end else if (word_part_count_q == 2'b10 && (hash_process_i || process_flag_q)) begin
                            -18-  
163                  // 384/512: msg ended but last word still waiting to be fed in
164                  word_valid  = 1'b1;
165                  sha_process = 1'b1;
166                  if (sha_ready == 1'b1) begin // word has been consumed
                     -19-  
167                    word_part_reset = 1'b1; // which will also reset word_valid in the next cycle
                       ==> (Excluded)
Exclude Annotation: VC_COV_UNR
168                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
169                end else if (word_part_count_q == 2'b10) begin // word feeding stalled
                            -20-  
170                  word_valid = 1'b0;
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
171                end
                   MISSING_ELSE
                   ==>
172              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	Status	Tests	Exclude Annotation
1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T6
1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T6
1	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T7
1	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T7
1	1	0	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T7
1	1	0	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T7
1	0	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T6
1	0	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T6
1	0	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T6
1	0	-	-	-	-	1	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T6
1	0	-	-	-	-	0	-	-	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
1	0	-	-	-	-	0	-	-	1	0	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
1	0	-	-	-	-	0	-	-	1	-	1	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
1	0	-	-	-	-	0	-	-	1	-	0	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
1	0	-	-	-	-	0	-	-	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
0	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T3,T4,T5
0	-	-	-	-	-	-	-	-	-	-	-	1	0	1	1	-	-	-	-	Covered	T5,T8,T9
0	-	-	-	-	-	-	-	-	-	-	-	1	0	1	0	-	-	-	-	Covered	T5,T8,T9
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	1	-	-	-	Covered	T3,T5,T6
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	1	1	-	Excluded		VC_COV_UNR
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	1	0	-	Excluded		VC_COV_UNR
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	0	-	1	Excluded		VC_COV_UNR
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	0	-	0	Covered	T3,T4,T5
0	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3

175              if ((word_part_reset || hash_go || !sha_en_i)) begin
                 -1-  
176                word_part_count_d = '0;
                   ==>
177              end else if (word_part_inc) begin
                          -2-  
178                word_part_count_d = word_part_count_q + 1'b1;
                   ==>
179              end else begin
180                word_part_count_d = word_part_count_q;
                   ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
0	0	Covered	T3,T4,T5

184              if (hash_go)          digest_mode_flag_d = digest_mode_i;      // latch in configured mode
                 -1-  
                 ==>
185              else if (hash_done_o) digest_mode_flag_d = SHA2_None;          // clear
                      -2-  
                 ==>
186              else                  digest_mode_flag_d = digest_mode_flag_q; // keep
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
0	0	Covered	T1,T2,T3

189              if (!sha_en_i || hash_go) process_flag_d = 1'b0;
                 -1-  
                 ==>
190              else if (hash_process_i)  process_flag_d = 1'b1;
                      -2-  
                 ==>
191              else                      process_flag_d = process_flag_q;
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
0	0	Covered	T3,T4,T5

222              if (!rst_ni)  word_part_count_q <= '0;
                 -1-  
                 ==>
223              else          word_part_count_q <= word_part_count_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

227              if (!rst_ni)  word_buffer_q <= 0;
                 -1-  
                 ==>
228              else          word_buffer_q <= word_buffer_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

232             if (!rst_ni)          process_flag_q <= '0;
                -1-  
                ==>
233              else  process_flag_q <= process_flag_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

237              if (!rst_ni) digest_mode_flag_q <= SHA2_None;
                 -1-  
                 ==>
238              else         digest_mode_flag_q <= digest_mode_flag_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3