Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

41037634

1

T1

6823

T2

6731

T3

10622

full_word

37401380

1

T1

5414

T2

6930

T3

16676

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	78438634	1			T1	12237		T2	13661		T3	27298
auto[TlIntgErrCmd]	141	1			T59	4		T60	7		T61	11
auto[TlIntgErrData]	128	1			T59	4		T60	6		T61	15
auto[TlIntgErrBoth]	111	1			T59	2		T60	7		T61	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37281925

1

T1

6253

T2

7141

T3

11272

auto[1]

41157089

1

T1

5984

T2

6520

T3

16026

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	19007567	1			T1	3244		T2	3733		T3	5665
auto[TlIntgErrNone]	partial	auto[1]	22029725	1			T1	3579		T2	2998		T3	4957
auto[TlIntgErrNone]	full_word	auto[0]	18274178	1			T1	3009		T2	3408		T3	5607
auto[TlIntgErrNone]	full_word	auto[1]	19127164	1			T1	2405		T2	3522		T3	11069
auto[TlIntgErrCmd]	partial	auto[0]	61	1			T59	1		T60	3		T61	6
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T59	2		T60	3		T61	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T60	1		T137	1		T141	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T59	1		T61	1		T137	1
auto[TlIntgErrData]	partial	auto[0]	62	1			T59	4		T60	6		T61	6
auto[TlIntgErrData]	partial	auto[1]	50	1			T61	8		T142	1		T135	1
auto[TlIntgErrData]	full_word	auto[0]	9	1			T61	1		T143	1		T141	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T140	1		T141	1		T144	2
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T59	1		T60	4		T61	1
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T59	1		T60	2		T61	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T139	1		T143	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T60	1		T135	1		T140	1