Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	432276750	615589	0	0
intr_enable_rd_A	432276750	2077	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432276750	615589	0	0
T7	525918	7577	0	0
T8	799470	7496	0	0
T9	0	2150	0	0
T14	0	5015	0	0
T22	0	9986	0	0
T33	535314	0	0	0
T34	352788	0	0	0
T35	791875	0	0	0
T45	280621	0	0	0
T53	1355	0	0	0
T56	3624	0	0	0
T59	0	3	0	0
T63	0	19330	0	0
T64	0	409	0	0
T65	0	4	0	0
T66	0	522	0	0
T67	41271	0	0	0
T68	367844	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432276750	2077	0	0
T14	112984	10	0	0
T69	0	49	0	0
T70	0	4	0	0
T71	0	10	0	0
T72	0	12	0	0
T73	0	60	0	0
T74	0	18	0	0
T75	0	14	0	0
T76	0	27	0	0
T77	0	30	0	0
T78	191886	0	0	0
T79	373906	0	0	0
T80	46049	0	0	0
T81	31986	0	0	0
T82	240478	0	0	0
T83	940	0	0	0
T84	11642	0	0	0
T85	277249	0	0	0
T86	736441	0	0	0