Line Coverage for Module :
prim_packer
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 66 | 66 | 100.00 |
| ALWAYS | 65 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
| ALWAYS | 78 | 6 | 6 | 100.00 |
| ALWAYS | 90 | 5 | 5 | 100.00 |
| ALWAYS | 157 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 165 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 170 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| ALWAYS | 185 | 9 | 9 | 100.00 |
| ALWAYS | 214 | 8 | 8 | 100.00 |
| ALWAYS | 235 | 3 | 3 | 100.00 |
| ALWAYS | 243 | 14 | 14 | 100.00 |
| CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 283 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 291 | 0 | 0 | |
| CONT_ASSIGN | 294 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 296 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 299 | 0 | 0 | |
64 // counting mask_i ones
65 1/1 inmask_ones = '0;
Tests: T1 T2 T3
66 1/1 for (int i = 0 ; i < InW ; i++) begin
Tests: T1 T2 T3
67 1/1 inmask_ones = inmask_ones + OnesCntW'(mask_i[i]);
Tests: T1 T2 T3
68 end
69 end
70
71 logic [PtrW-1:0] pos_with_input;
72 1/1 assign pos_with_input = pos_q + PtrW'(inmask_ones);
Tests: T1 T2 T3
73
74 if (EnProtection == 1'b 0) begin : g_pos_nodup
75 logic [PtrW-1:0] pos_d;
76
77 always_comb begin
78 1/1 pos_d = pos_q;
Tests: T1 T2 T3
79
80 1/1 unique case ({ack_in, ack_out})
Tests: T1 T2 T3
81 1/1 2'b00: pos_d = pos_q;
Tests: T1 T2 T3
82 1/1 2'b01: pos_d = (int'(pos_q) <= OutW) ? '0 : pos_q - PtrW'(OutW);
Tests: T1 T2 T3
83 1/1 2'b10: pos_d = pos_with_input;
Tests: T1 T2 T3
84 1/1 2'b11: pos_d = (int'(pos_with_input) <= OutW) ? '0 : pos_with_input - PtrW'(OutW);
Tests: T26 T27
85 default: pos_d = pos_q;
86 endcase
87 end
88
89 always_ff @(posedge clk_i or negedge rst_ni) begin
90 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
91 1/1 pos_q <= '0;
Tests: T1 T2 T3
92 1/1 end else if (flush_done) begin
Tests: T1 T2 T3
93 1/1 pos_q <= '0;
Tests: T1 T2 T3
94 end else begin
95 1/1 pos_q <= pos_d;
Tests: T1 T2 T3
96 end
97 end
98
99 assign err_o = 1'b 0; // No checker logic
100
101 end else begin : g_pos_dupcnt // EnProtection == 1'b 1
102 // incr_en: Increase the pos by cnt_step. ack_in && !ack_out
103 // decr_en: Decrease the pos by cnt_step. !ack_in && ack_out
104 // set_en: Set to specific value in case of ack_in && ack_out.
105 // This case, the value could be increased or descreased based on
106 // the input size (inmask_ones)
107 logic cnt_incr_en, cnt_decr_en, cnt_set_en;
108 logic [PtrW-1:0] cnt_step, cnt_set;
109
110 assign cnt_incr_en = ack_in && !ack_out;
111 assign cnt_decr_en = !ack_in && ack_out;
112 assign cnt_set_en = ack_in && ack_out;
113
114 // counter has underflow protection.
115 assign cnt_step = (cnt_incr_en) ? PtrW'(inmask_ones) : PtrW'(OutW);
116
117 always_comb begin : cnt_set_logic
118
119 // default, consuming all data
120 cnt_set = '0;
121
122 if (pos_with_input > PtrW'(OutW)) begin
123 // pos_q + inmask_ones is bigger than Output width. Still data remained.
124 cnt_set = pos_with_input - PtrW'(OutW);
125 end
126 end : cnt_set_logic
127
128
129 prim_count #(
130 .Width (PtrW),
131 .ResetValue ('0 )
132 ) u_pos (
133 .clk_i,
134 .rst_ni,
135
136 .clr_i (flush_done),
137
138 .set_i (cnt_set_en),
139 .set_cnt_i (cnt_set ),
140
141 .incr_en_i (cnt_incr_en),
142 .decr_en_i (cnt_decr_en),
143 .step_i (cnt_step ),
144 .commit_i (1'b1 ),
145
146 .cnt_o (pos_q ), // Current counter state
147 .cnt_after_commit_o ( ), // Next counter state
148
149 .err_o
150 );
151 end // g_pos_dupcnt
152
153 //---------------------------------------------------------------------------
154
155 // Leading one detector for mask_i
156 always_comb begin
157 1/1 lod_idx = 0;
Tests: T1 T2 T3
158 1/1 for (int i = InW-1; i >= 0 ; i--) begin
Tests: T1 T2 T3
159 1/1 if (mask_i[i] == 1'b1) begin
Tests: T1 T2 T3
160 1/1 lod_idx = IdxW'(unsigned'(i));
Tests: T1 T2 T3
161 end
MISSING_ELSE
162 end
163 end
164
165 1/1 assign ack_in = valid_i & ready_o;
Tests: T1 T2 T3
166 1/1 assign ack_out = valid_o & ready_i;
Tests: T1 T2 T3
167
168 // Data process =============================================================
169 // shiftr : Input data shifted right to put the leading one at bit zero
170 1/1 assign shiftr_data = (valid_i) ? data_i >> lod_idx : '0;
Tests: T1 T2 T3
171 1/1 assign shiftr_mask = (valid_i) ? mask_i >> lod_idx : '0;
Tests: T1 T2 T3
172
173 // shiftl : Input data shifted into the current stored position
174 1/1 assign shiftl_data = ConcatW'(shiftr_data) << pos_q;
Tests: T1 T2 T3
175 1/1 assign shiftl_mask = ConcatW'(shiftr_mask) << pos_q;
Tests: T1 T2 T3
176
177 // concat : Merging stored and shiftl
178 1/1 assign concat_data = {{(InW){1'b0}}, stored_data & stored_mask} |
Tests: T1 T2 T3
179 (shiftl_data & shiftl_mask);
180 1/1 assign concat_mask = {{(InW){1'b0}}, stored_mask} | shiftl_mask;
Tests: T1 T2 T3
181
182 logic [Width-1:0] stored_data_next, stored_mask_next;
183
184 always_comb begin
185 1/1 unique case ({ack_in, ack_out})
Tests: T1 T2 T3
186 2'b 00: begin
187 1/1 stored_data_next = stored_data;
Tests: T1 T2 T3
188 1/1 stored_mask_next = stored_mask;
Tests: T1 T2 T3
189 end
190 2'b 01: begin
191 // ack_out : shift the amount of OutW
192 1/1 stored_data_next = {{OutW{1'b0}}, stored_data[Width-1:OutW]};
Tests: T1 T2 T3
193 1/1 stored_mask_next = {{OutW{1'b0}}, stored_mask[Width-1:OutW]};
Tests: T1 T2 T3
194 end
195 2'b 10: begin
196 // ack_in : Store concat data
197 1/1 stored_data_next = concat_data[0+:Width];
Tests: T1 T2 T3
198 1/1 stored_mask_next = concat_mask[0+:Width];
Tests: T1 T2 T3
199 end
200 2'b 11: begin
201 // both : shift the concat_data
202 1/1 stored_data_next = concat_data[ConcatW-1:OutW];
Tests: T26 T27
203 1/1 stored_mask_next = concat_mask[ConcatW-1:OutW];
Tests: T26 T27
204 end
205 default: begin
206 stored_data_next = stored_data;
207 stored_mask_next = stored_mask;
208 end
209 endcase
210 end
211
212 // Store the data temporary if it doesn't exceed OutW
213 always_ff @(posedge clk_i or negedge rst_ni) begin
214 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
215 1/1 stored_data <= '0;
Tests: T1 T2 T3
216 1/1 stored_mask <= '0;
Tests: T1 T2 T3
217 1/1 end else if (flush_done) begin
Tests: T1 T2 T3
218 1/1 stored_data <= '0;
Tests: T1 T2 T3
219 1/1 stored_mask <= '0;
Tests: T1 T2 T3
220 end else begin
221 1/1 stored_data <= stored_data_next;
Tests: T1 T2 T3
222 1/1 stored_mask <= stored_mask_next;
Tests: T1 T2 T3
223 end
224 end
225 //---------------------------------------------------------------------------
226
227 // flush handling
228 typedef enum logic {
229 FlushIdle,
230 FlushSend
231 } flush_st_e;
232 flush_st_e flush_st, flush_st_next;
233
234 always_ff @(posedge clk_i or negedge rst_ni) begin
235 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
236 1/1 flush_st <= FlushIdle;
Tests: T1 T2 T3
237 end else begin
238 1/1 flush_st <= flush_st_next;
Tests: T1 T2 T3
239 end
240 end
241
242 always_comb begin
243 1/1 flush_st_next = FlushIdle;
Tests: T1 T2 T3
244
245 1/1 flush_valid = 1'b0;
Tests: T1 T2 T3
246 1/1 flush_done = 1'b0;
Tests: T1 T2 T3
247
248 1/1 unique case (flush_st)
Tests: T1 T2 T3
249 FlushIdle: begin
250 1/1 if (flush_i) begin
Tests: T1 T2 T3
251 1/1 flush_st_next = FlushSend;
Tests: T1 T2 T3
252 end else begin
253 1/1 flush_st_next = FlushIdle;
Tests: T1 T2 T3
254 end
255 end
256
257 FlushSend: begin
258 1/1 if (pos_q == '0) begin
Tests: T1 T2 T3
259 1/1 flush_st_next = FlushIdle;
Tests: T1 T2 T3
260
261 1/1 flush_valid = 1'b 0;
Tests: T1 T2 T3
262 1/1 flush_done = 1'b 1;
Tests: T1 T2 T3
263 end else begin
264 1/1 flush_st_next = FlushSend;
Tests: T1 T2 T3
265
266 1/1 flush_valid = 1'b 1;
Tests: T1 T2 T3
267 1/1 flush_done = 1'b 0;
Tests: T1 T2 T3
268 end
269 end
270 default: begin
271 flush_st_next = FlushIdle;
272
273 flush_valid = 1'b 0;
274 flush_done = 1'b 0;
275 end
276 endcase
277 end
278
279 1/1 assign flush_done_o = flush_done;
Tests: T1 T2 T3
280
281
282 // Output signals ===========================================================
283 1/1 assign valid_next = (int'(pos_q) >= OutW) ? 1'b 1 : flush_valid;
Tests: T1 T2 T3
284
285 // storage space is InW + OutW. So technically, ready_o can be asserted even
286 // if `pos_q` is greater than OutW. But in order to do that, the logic should
287 // use `inmask_ones` value whether pos_q+inmask_ones is less than (InW+OutW)
288 // with `valid_i`. It creates a path from `valid_i` --> `ready_o`.
289 // It may create a timing loop in some modules that use `ready_o` to
290 // `valid_i` (which is not a good practice though)
291 unreachable assign ready_next = int'(pos_q) <= OutW;
292
293 // Output request
294 1/1 assign valid_o = valid_next;
Tests: T1 T2 T3
295 1/1 assign data_o = stored_data[OutW-1:0];
Tests: T1 T2 T3
296 1/1 assign mask_o = stored_mask[OutW-1:0];
Tests: T1 T2 T3
297
298 // ready_o
299 unreachable assign ready_o = ready_next;
Cond Coverage for Module :
prim_packer
| Total | Covered | Percent |
|---|
| Conditions | 16 | 15 | 93.75 |
| Logical | 16 | 15 | 93.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 82
EXPRESSION ((int'(pos_q) <= OutW) ? '0 : ((pos_q - 7'(OutW))))
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Unreachable | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 84
EXPRESSION ((int'(pos_with_input) <= OutW) ? '0 : ((pos_with_input - 7'(OutW))))
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Unreachable | T26,T27 |
| 1 | Not Covered | |
LINE 159
EXPRESSION (mask_i[i] == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 165
EXPRESSION (valid_i & ready_o)
---1--- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | T11,T12,T13 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 166
EXPRESSION (valid_o & ready_i)
---1--- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T11,T12,T13 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 170
EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 171
EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 258
EXPRESSION (pos_q == '0)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 283
EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Unreachable | T1,T2,T3 |
Branch Coverage for Module :
prim_packer
| Line No. | Total | Covered | Percent |
| Branches |
|
30 |
26 |
86.67 |
| TERNARY |
170 |
2 |
2 |
100.00 |
| TERNARY |
171 |
2 |
2 |
100.00 |
| TERNARY |
283 |
1 |
1 |
100.00 |
| IF |
159 |
2 |
2 |
100.00 |
| CASE |
185 |
5 |
4 |
80.00 |
| IF |
214 |
3 |
3 |
100.00 |
| IF |
235 |
2 |
2 |
100.00 |
| CASE |
248 |
5 |
4 |
80.00 |
| CASE |
80 |
5 |
3 |
60.00 |
| IF |
90 |
3 |
3 |
100.00 |
170 assign shiftr_data = (valid_i) ? data_i >> lod_idx : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
171 assign shiftr_mask = (valid_i) ? mask_i >> lod_idx : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
283 assign valid_next = (int'(pos_q) >= OutW) ? 1'b 1 : flush_valid;
-1-
==> (Unreachable)
==>
Branches:
| -1- | Status | Tests |
| 1 |
Unreachable |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
159 if (mask_i[i] == 1'b1) begin
-1-
160 lod_idx = IdxW'(unsigned'(i));
==>
161 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
185 unique case ({ack_in, ack_out})
-1-
186 2'b 00: begin
187 stored_data_next = stored_data;
==>
188 stored_mask_next = stored_mask;
189 end
190 2'b 01: begin
191 // ack_out : shift the amount of OutW
192 stored_data_next = {{OutW{1'b0}}, stored_data[Width-1:OutW]};
==>
193 stored_mask_next = {{OutW{1'b0}}, stored_mask[Width-1:OutW]};
194 end
195 2'b 10: begin
196 // ack_in : Store concat data
197 stored_data_next = concat_data[0+:Width];
==>
198 stored_mask_next = concat_mask[0+:Width];
199 end
200 2'b 11: begin
201 // both : shift the concat_data
202 stored_data_next = concat_data[ConcatW-1:OutW];
==>
203 stored_mask_next = concat_mask[ConcatW-1:OutW];
204 end
205 default: begin
206 stored_data_next = stored_data;
==>
Branches:
| -1- | Status | Tests |
| 2'b00 |
Covered |
T1,T2,T3 |
| 2'b01 |
Covered |
T1,T2,T3 |
| 2'b10 |
Covered |
T1,T2,T3 |
| 2'b11 |
Covered |
T26,T27 |
| default |
Not Covered |
|
214 if (!rst_ni) begin
-1-
215 stored_data <= '0;
==>
216 stored_mask <= '0;
217 end else if (flush_done) begin
-2-
218 stored_data <= '0;
==>
219 stored_mask <= '0;
220 end else begin
221 stored_data <= stored_data_next;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
235 if (!rst_ni) begin
-1-
236 flush_st <= FlushIdle;
==>
237 end else begin
238 flush_st <= flush_st_next;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
248 unique case (flush_st)
-1-
249 FlushIdle: begin
250 if (flush_i) begin
-2-
251 flush_st_next = FlushSend;
==>
252 end else begin
253 flush_st_next = FlushIdle;
==>
254 end
255 end
256
257 FlushSend: begin
258 if (pos_q == '0) begin
-3-
259 flush_st_next = FlushIdle;
==>
260
261 flush_valid = 1'b 0;
262 flush_done = 1'b 1;
263 end else begin
264 flush_st_next = FlushSend;
==>
265
266 flush_valid = 1'b 1;
267 flush_done = 1'b 0;
268 end
269 end
270 default: begin
271 flush_st_next = FlushIdle;
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| FlushIdle |
1 |
- |
Covered |
T1,T2,T3 |
| FlushIdle |
0 |
- |
Covered |
T1,T2,T3 |
| FlushSend |
- |
1 |
Covered |
T1,T2,T3 |
| FlushSend |
- |
0 |
Covered |
T1,T2,T3 |
| default |
- |
- |
Not Covered |
|
80 unique case ({ack_in, ack_out})
-1-
81 2'b00: pos_d = pos_q;
==>
82 2'b01: pos_d = (int'(pos_q) <= OutW) ? '0 : pos_q - PtrW'(OutW);
-2-
==>
==> (Unreachable)
83 2'b10: pos_d = pos_with_input;
==>
84 2'b11: pos_d = (int'(pos_with_input) <= OutW) ? '0 : pos_with_input - PtrW'(OutW);
-3-
==>
==> (Unreachable)
85 default: pos_d = pos_q;
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 2'b00 |
- |
- |
Covered |
T1,T2,T3 |
| 2'b01 |
1 |
- |
Covered |
T1,T2,T3 |
| 2'b01 |
0 |
- |
Unreachable |
T1,T2,T3 |
| 2'b10 |
- |
- |
Covered |
T1,T2,T3 |
| 2'b11 |
- |
1 |
Not Covered |
|
| 2'b11 |
- |
0 |
Unreachable |
T26,T27 |
| default |
- |
- |
Not Covered |
|
90 if (!rst_ni) begin
-1-
91 pos_q <= '0;
==>
92 end else if (flush_done) begin
-2-
93 pos_q <= '0;
==>
94 end else begin
95 pos_q <= pos_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_packer
Assertion Details
DataIStable_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
124 |
0 |
491 |
| T7 |
525918 |
0 |
0 |
1 |
| T11 |
49077 |
2 |
0 |
1 |
| T12 |
0 |
6 |
0 |
0 |
| T13 |
0 |
3 |
0 |
0 |
| T23 |
64201 |
0 |
0 |
1 |
| T25 |
150727 |
0 |
0 |
1 |
| T26 |
0 |
40 |
0 |
0 |
| T27 |
0 |
40 |
0 |
0 |
| T28 |
0 |
22 |
0 |
0 |
| T29 |
0 |
11 |
0 |
0 |
| T30 |
967121 |
0 |
0 |
1 |
| T31 |
274978 |
0 |
0 |
1 |
| T32 |
118016 |
0 |
0 |
1 |
| T33 |
535314 |
0 |
0 |
1 |
| T34 |
352788 |
0 |
0 |
1 |
| T35 |
791875 |
0 |
0 |
1 |
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
263 |
0 |
491 |
| T7 |
525918 |
0 |
0 |
1 |
| T11 |
49077 |
10 |
0 |
1 |
| T12 |
0 |
12 |
0 |
0 |
| T13 |
0 |
10 |
0 |
0 |
| T23 |
64201 |
0 |
0 |
1 |
| T25 |
150727 |
0 |
0 |
1 |
| T26 |
0 |
106 |
0 |
0 |
| T27 |
0 |
80 |
0 |
0 |
| T28 |
0 |
28 |
0 |
0 |
| T29 |
0 |
17 |
0 |
0 |
| T30 |
967121 |
0 |
0 |
1 |
| T31 |
274978 |
0 |
0 |
1 |
| T32 |
118016 |
0 |
0 |
1 |
| T33 |
535314 |
0 |
0 |
1 |
| T34 |
352788 |
0 |
0 |
1 |
| T35 |
791875 |
0 |
0 |
1 |
ExFlushValid_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
16430 |
0 |
0 |
| T1 |
26133 |
5 |
0 |
0 |
| T2 |
101693 |
26 |
0 |
0 |
| T3 |
57307 |
8 |
0 |
0 |
| T4 |
6245 |
3 |
0 |
0 |
| T5 |
503225 |
22 |
0 |
0 |
| T6 |
123077 |
8 |
0 |
0 |
| T10 |
374472 |
180 |
0 |
0 |
| T15 |
4975 |
0 |
0 |
0 |
| T16 |
907 |
0 |
0 |
0 |
| T17 |
472274 |
135 |
0 |
0 |
| T18 |
0 |
17 |
0 |
0 |
| T19 |
0 |
6 |
0 |
0 |
ExcessiveDataStored_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
8 |
0 |
0 |
| T26 |
116918 |
4 |
0 |
0 |
| T27 |
0 |
4 |
0 |
0 |
| T36 |
139310 |
0 |
0 |
0 |
| T37 |
23316 |
0 |
0 |
0 |
| T38 |
49674 |
0 |
0 |
0 |
| T39 |
169668 |
0 |
0 |
0 |
| T40 |
136384 |
0 |
0 |
0 |
| T41 |
113706 |
0 |
0 |
0 |
| T42 |
190468 |
0 |
0 |
0 |
| T43 |
1303 |
0 |
0 |
0 |
| T44 |
3045 |
0 |
0 |
0 |
ExcessiveMaskStored_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
8 |
0 |
0 |
| T26 |
116918 |
4 |
0 |
0 |
| T27 |
0 |
4 |
0 |
0 |
| T36 |
139310 |
0 |
0 |
0 |
| T37 |
23316 |
0 |
0 |
0 |
| T38 |
49674 |
0 |
0 |
0 |
| T39 |
169668 |
0 |
0 |
0 |
| T40 |
136384 |
0 |
0 |
0 |
| T41 |
113706 |
0 |
0 |
0 |
| T42 |
190468 |
0 |
0 |
0 |
| T43 |
1303 |
0 |
0 |
0 |
| T44 |
3045 |
0 |
0 |
0 |
FlushFollowedByDone_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
16430 |
0 |
491 |
| T1 |
26133 |
5 |
0 |
1 |
| T2 |
101693 |
26 |
0 |
1 |
| T3 |
57307 |
8 |
0 |
1 |
| T4 |
6245 |
3 |
0 |
1 |
| T5 |
503225 |
22 |
0 |
1 |
| T6 |
123077 |
8 |
0 |
1 |
| T10 |
374472 |
180 |
0 |
1 |
| T15 |
4975 |
0 |
0 |
1 |
| T16 |
907 |
0 |
0 |
1 |
| T17 |
472274 |
135 |
0 |
1 |
| T18 |
0 |
17 |
0 |
0 |
| T19 |
0 |
6 |
0 |
0 |
ValidIDeassertedOnFlush_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
26325 |
0 |
0 |
| T1 |
26133 |
6 |
0 |
0 |
| T2 |
101693 |
45 |
0 |
0 |
| T3 |
57307 |
12 |
0 |
0 |
| T4 |
6245 |
5 |
0 |
0 |
| T5 |
503225 |
37 |
0 |
0 |
| T6 |
123077 |
11 |
0 |
0 |
| T10 |
374472 |
180 |
0 |
0 |
| T15 |
4975 |
0 |
0 |
0 |
| T16 |
907 |
0 |
0 |
0 |
| T17 |
472274 |
135 |
0 |
0 |
| T18 |
0 |
31 |
0 |
0 |
| T19 |
0 |
11 |
0 |
0 |
ValidOAssertedForStoredDataGTEOutW_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
7068105 |
0 |
0 |
| T1 |
26133 |
1766 |
0 |
0 |
| T2 |
101693 |
926 |
0 |
0 |
| T3 |
57307 |
4502 |
0 |
0 |
| T4 |
6245 |
160 |
0 |
0 |
| T5 |
503225 |
10375 |
0 |
0 |
| T6 |
123077 |
2374 |
0 |
0 |
| T10 |
374472 |
5760 |
0 |
0 |
| T15 |
4975 |
0 |
0 |
0 |
| T16 |
907 |
0 |
0 |
0 |
| T17 |
472274 |
4320 |
0 |
0 |
| T18 |
0 |
6985 |
0 |
0 |
| T19 |
0 |
3199 |
0 |
0 |
ValidOPairedWidthReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
263 |
0 |
0 |
| T7 |
525918 |
0 |
0 |
0 |
| T11 |
49077 |
10 |
0 |
0 |
| T12 |
0 |
12 |
0 |
0 |
| T13 |
0 |
10 |
0 |
0 |
| T23 |
64201 |
0 |
0 |
0 |
| T25 |
150727 |
0 |
0 |
0 |
| T26 |
0 |
106 |
0 |
0 |
| T27 |
0 |
80 |
0 |
0 |
| T28 |
0 |
28 |
0 |
0 |
| T29 |
0 |
17 |
0 |
0 |
| T30 |
967121 |
0 |
0 |
0 |
| T31 |
274978 |
0 |
0 |
0 |
| T32 |
118016 |
0 |
0 |
0 |
| T33 |
535314 |
0 |
0 |
0 |
| T34 |
352788 |
0 |
0 |
0 |
| T35 |
791875 |
0 |
0 |
0 |
gen_mask_assert.ContiguousOnesMask_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
9248780 |
0 |
0 |
| T1 |
26133 |
2415 |
0 |
0 |
| T2 |
101693 |
1315 |
0 |
0 |
| T3 |
57307 |
4775 |
0 |
0 |
| T4 |
6245 |
224 |
0 |
0 |
| T5 |
503225 |
10459 |
0 |
0 |
| T6 |
123077 |
2404 |
0 |
0 |
| T10 |
374472 |
8114 |
0 |
0 |
| T15 |
4975 |
0 |
0 |
0 |
| T16 |
907 |
0 |
0 |
0 |
| T17 |
472274 |
6098 |
0 |
0 |
| T18 |
0 |
7418 |
0 |
0 |
| T19 |
0 |
4409 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_packer
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 66 | 66 | 100.00 |
| ALWAYS | 65 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
| ALWAYS | 78 | 6 | 6 | 100.00 |
| ALWAYS | 90 | 5 | 5 | 100.00 |
| ALWAYS | 157 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 165 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 170 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| ALWAYS | 185 | 9 | 9 | 100.00 |
| ALWAYS | 214 | 8 | 8 | 100.00 |
| ALWAYS | 235 | 3 | 3 | 100.00 |
| ALWAYS | 243 | 14 | 14 | 100.00 |
| CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 283 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 291 | 0 | 0 | |
| CONT_ASSIGN | 294 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 296 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 299 | 0 | 0 | |
64 // counting mask_i ones
65 1/1 inmask_ones = '0;
Tests: T1 T2 T3
66 1/1 for (int i = 0 ; i < InW ; i++) begin
Tests: T1 T2 T3
67 1/1 inmask_ones = inmask_ones + OnesCntW'(mask_i[i]);
Tests: T1 T2 T3
68 end
69 end
70
71 logic [PtrW-1:0] pos_with_input;
72 1/1 assign pos_with_input = pos_q + PtrW'(inmask_ones);
Tests: T1 T2 T3
73
74 if (EnProtection == 1'b 0) begin : g_pos_nodup
75 logic [PtrW-1:0] pos_d;
76
77 always_comb begin
78 1/1 pos_d = pos_q;
Tests: T1 T2 T3
79
80 1/1 unique case ({ack_in, ack_out})
Tests: T1 T2 T3
81 1/1 2'b00: pos_d = pos_q;
Tests: T1 T2 T3
82 1/1 2'b01: pos_d = (int'(pos_q) <= OutW) ? '0 : pos_q - PtrW'(OutW);
Tests: T1 T2 T3
83 1/1 2'b10: pos_d = pos_with_input;
Tests: T1 T2 T3
84 1/1 2'b11: pos_d = (int'(pos_with_input) <= OutW) ? '0 : pos_with_input - PtrW'(OutW);
Tests: T26 T27
85 default: pos_d = pos_q;
Exclude Annotation: VC_COV_UNR
86 endcase
87 end
88
89 always_ff @(posedge clk_i or negedge rst_ni) begin
90 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
91 1/1 pos_q <= '0;
Tests: T1 T2 T3
92 1/1 end else if (flush_done) begin
Tests: T1 T2 T3
93 1/1 pos_q <= '0;
Tests: T1 T2 T3
94 end else begin
95 1/1 pos_q <= pos_d;
Tests: T1 T2 T3
96 end
97 end
98
99 assign err_o = 1'b 0; // No checker logic
100
101 end else begin : g_pos_dupcnt // EnProtection == 1'b 1
102 // incr_en: Increase the pos by cnt_step. ack_in && !ack_out
103 // decr_en: Decrease the pos by cnt_step. !ack_in && ack_out
104 // set_en: Set to specific value in case of ack_in && ack_out.
105 // This case, the value could be increased or descreased based on
106 // the input size (inmask_ones)
107 logic cnt_incr_en, cnt_decr_en, cnt_set_en;
108 logic [PtrW-1:0] cnt_step, cnt_set;
109
110 assign cnt_incr_en = ack_in && !ack_out;
111 assign cnt_decr_en = !ack_in && ack_out;
112 assign cnt_set_en = ack_in && ack_out;
113
114 // counter has underflow protection.
115 assign cnt_step = (cnt_incr_en) ? PtrW'(inmask_ones) : PtrW'(OutW);
116
117 always_comb begin : cnt_set_logic
118
119 // default, consuming all data
120 cnt_set = '0;
121
122 if (pos_with_input > PtrW'(OutW)) begin
123 // pos_q + inmask_ones is bigger than Output width. Still data remained.
124 cnt_set = pos_with_input - PtrW'(OutW);
125 end
126 end : cnt_set_logic
127
128
129 prim_count #(
130 .Width (PtrW),
131 .ResetValue ('0 )
132 ) u_pos (
133 .clk_i,
134 .rst_ni,
135
136 .clr_i (flush_done),
137
138 .set_i (cnt_set_en),
139 .set_cnt_i (cnt_set ),
140
141 .incr_en_i (cnt_incr_en),
142 .decr_en_i (cnt_decr_en),
143 .step_i (cnt_step ),
144 .commit_i (1'b1 ),
145
146 .cnt_o (pos_q ), // Current counter state
147 .cnt_after_commit_o ( ), // Next counter state
148
149 .err_o
150 );
151 end // g_pos_dupcnt
152
153 //---------------------------------------------------------------------------
154
155 // Leading one detector for mask_i
156 always_comb begin
157 1/1 lod_idx = 0;
Tests: T1 T2 T3
158 1/1 for (int i = InW-1; i >= 0 ; i--) begin
Tests: T1 T2 T3
159 1/1 if (mask_i[i] == 1'b1) begin
Tests: T1 T2 T3
160 1/1 lod_idx = IdxW'(unsigned'(i));
Tests: T1 T2 T3
161 end
MISSING_ELSE
162 end
163 end
164
165 1/1 assign ack_in = valid_i & ready_o;
Tests: T1 T2 T3
166 1/1 assign ack_out = valid_o & ready_i;
Tests: T1 T2 T3
167
168 // Data process =============================================================
169 // shiftr : Input data shifted right to put the leading one at bit zero
170 1/1 assign shiftr_data = (valid_i) ? data_i >> lod_idx : '0;
Tests: T1 T2 T3
171 1/1 assign shiftr_mask = (valid_i) ? mask_i >> lod_idx : '0;
Tests: T1 T2 T3
172
173 // shiftl : Input data shifted into the current stored position
174 1/1 assign shiftl_data = ConcatW'(shiftr_data) << pos_q;
Tests: T1 T2 T3
175 1/1 assign shiftl_mask = ConcatW'(shiftr_mask) << pos_q;
Tests: T1 T2 T3
176
177 // concat : Merging stored and shiftl
178 1/1 assign concat_data = {{(InW){1'b0}}, stored_data & stored_mask} |
Tests: T1 T2 T3
179 (shiftl_data & shiftl_mask);
180 1/1 assign concat_mask = {{(InW){1'b0}}, stored_mask} | shiftl_mask;
Tests: T1 T2 T3
181
182 logic [Width-1:0] stored_data_next, stored_mask_next;
183
184 always_comb begin
185 1/1 unique case ({ack_in, ack_out})
Tests: T1 T2 T3
186 2'b 00: begin
187 1/1 stored_data_next = stored_data;
Tests: T1 T2 T3
188 1/1 stored_mask_next = stored_mask;
Tests: T1 T2 T3
189 end
190 2'b 01: begin
191 // ack_out : shift the amount of OutW
192 1/1 stored_data_next = {{OutW{1'b0}}, stored_data[Width-1:OutW]};
Tests: T1 T2 T3
193 1/1 stored_mask_next = {{OutW{1'b0}}, stored_mask[Width-1:OutW]};
Tests: T1 T2 T3
194 end
195 2'b 10: begin
196 // ack_in : Store concat data
197 1/1 stored_data_next = concat_data[0+:Width];
Tests: T1 T2 T3
198 1/1 stored_mask_next = concat_mask[0+:Width];
Tests: T1 T2 T3
199 end
200 2'b 11: begin
201 // both : shift the concat_data
202 1/1 stored_data_next = concat_data[ConcatW-1:OutW];
Tests: T26 T27
203 1/1 stored_mask_next = concat_mask[ConcatW-1:OutW];
Tests: T26 T27
204 end
205 default: begin
206 stored_data_next = stored_data;
Exclude Annotation: VC_COV_UNR
207 stored_mask_next = stored_mask;
Exclude Annotation: VC_COV_UNR
208 end
209 endcase
210 end
211
212 // Store the data temporary if it doesn't exceed OutW
213 always_ff @(posedge clk_i or negedge rst_ni) begin
214 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
215 1/1 stored_data <= '0;
Tests: T1 T2 T3
216 1/1 stored_mask <= '0;
Tests: T1 T2 T3
217 1/1 end else if (flush_done) begin
Tests: T1 T2 T3
218 1/1 stored_data <= '0;
Tests: T1 T2 T3
219 1/1 stored_mask <= '0;
Tests: T1 T2 T3
220 end else begin
221 1/1 stored_data <= stored_data_next;
Tests: T1 T2 T3
222 1/1 stored_mask <= stored_mask_next;
Tests: T1 T2 T3
223 end
224 end
225 //---------------------------------------------------------------------------
226
227 // flush handling
228 typedef enum logic {
229 FlushIdle,
230 FlushSend
231 } flush_st_e;
232 flush_st_e flush_st, flush_st_next;
233
234 always_ff @(posedge clk_i or negedge rst_ni) begin
235 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
236 1/1 flush_st <= FlushIdle;
Tests: T1 T2 T3
237 end else begin
238 1/1 flush_st <= flush_st_next;
Tests: T1 T2 T3
239 end
240 end
241
242 always_comb begin
243 1/1 flush_st_next = FlushIdle;
Tests: T1 T2 T3
244
245 1/1 flush_valid = 1'b0;
Tests: T1 T2 T3
246 1/1 flush_done = 1'b0;
Tests: T1 T2 T3
247
248 1/1 unique case (flush_st)
Tests: T1 T2 T3
249 FlushIdle: begin
250 1/1 if (flush_i) begin
Tests: T1 T2 T3
251 1/1 flush_st_next = FlushSend;
Tests: T1 T2 T3
252 end else begin
253 1/1 flush_st_next = FlushIdle;
Tests: T1 T2 T3
254 end
255 end
256
257 FlushSend: begin
258 1/1 if (pos_q == '0) begin
Tests: T1 T2 T3
259 1/1 flush_st_next = FlushIdle;
Tests: T1 T2 T3
260
261 1/1 flush_valid = 1'b 0;
Tests: T1 T2 T3
262 1/1 flush_done = 1'b 1;
Tests: T1 T2 T3
263 end else begin
264 1/1 flush_st_next = FlushSend;
Tests: T1 T2 T3
265
266 1/1 flush_valid = 1'b 1;
Tests: T1 T2 T3
267 1/1 flush_done = 1'b 0;
Tests: T1 T2 T3
268 end
269 end
270 default: begin
271 flush_st_next = FlushIdle;
Exclude Annotation: VC_COV_UNR
272
273 flush_valid = 1'b 0;
Exclude Annotation: VC_COV_UNR
274 flush_done = 1'b 0;
Exclude Annotation: VC_COV_UNR
275 end
276 endcase
277 end
278
279 1/1 assign flush_done_o = flush_done;
Tests: T1 T2 T3
280
281
282 // Output signals ===========================================================
283 1/1 assign valid_next = (int'(pos_q) >= OutW) ? 1'b 1 : flush_valid;
Tests: T1 T2 T3
284
285 // storage space is InW + OutW. So technically, ready_o can be asserted even
286 // if `pos_q` is greater than OutW. But in order to do that, the logic should
287 // use `inmask_ones` value whether pos_q+inmask_ones is less than (InW+OutW)
288 // with `valid_i`. It creates a path from `valid_i` --> `ready_o`.
289 // It may create a timing loop in some modules that use `ready_o` to
290 // `valid_i` (which is not a good practice though)
291 unreachable assign ready_next = int'(pos_q) <= OutW;
292
293 // Output request
294 1/1 assign valid_o = valid_next;
Tests: T1 T2 T3
295 1/1 assign data_o = stored_data[OutW-1:0];
Tests: T1 T2 T3
296 1/1 assign mask_o = stored_mask[OutW-1:0];
Tests: T1 T2 T3
297
298 // ready_o
299 unreachable assign ready_o = ready_next;
Cond Coverage for Instance : tb.dut.u_packer
| Total | Covered | Percent |
|---|
| Conditions | 16 | 15 | 93.75 |
| Logical | 16 | 15 | 93.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 82
EXPRESSION ((int'(pos_q) <= OutW) ? '0 : ((pos_q - 7'(OutW))))
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Unreachable | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 84
EXPRESSION ((int'(pos_with_input) <= OutW) ? '0 : ((pos_with_input - 7'(OutW))))
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Unreachable | T26,T27 |
| 1 | Not Covered | |
LINE 159
EXPRESSION (mask_i[i] == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 165
EXPRESSION (valid_i & ready_o)
---1--- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | T11,T12,T13 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 166
EXPRESSION (valid_o & ready_i)
---1--- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T11,T12,T13 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 170
EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 171
EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 258
EXPRESSION (pos_q == '0)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 283
EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Unreachable | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_packer
| Line No. | Total | Covered | Percent |
| Branches |
|
27 |
26 |
96.30 |
| TERNARY |
170 |
2 |
2 |
100.00 |
| TERNARY |
171 |
2 |
2 |
100.00 |
| TERNARY |
283 |
1 |
1 |
100.00 |
| IF |
159 |
2 |
2 |
100.00 |
| CASE |
185 |
4 |
4 |
100.00 |
| IF |
214 |
3 |
3 |
100.00 |
| IF |
235 |
2 |
2 |
100.00 |
| CASE |
248 |
4 |
4 |
100.00 |
| CASE |
80 |
4 |
3 |
75.00 |
| IF |
90 |
3 |
3 |
100.00 |
170 assign shiftr_data = (valid_i) ? data_i >> lod_idx : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
171 assign shiftr_mask = (valid_i) ? mask_i >> lod_idx : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
283 assign valid_next = (int'(pos_q) >= OutW) ? 1'b 1 : flush_valid;
-1-
==> (Unreachable)
==>
Branches:
| -1- | Status | Tests |
| 1 |
Unreachable |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
159 if (mask_i[i] == 1'b1) begin
-1-
160 lod_idx = IdxW'(unsigned'(i));
==>
161 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
185 unique case ({ack_in, ack_out})
-1-
186 2'b 00: begin
187 stored_data_next = stored_data;
==>
188 stored_mask_next = stored_mask;
189 end
190 2'b 01: begin
191 // ack_out : shift the amount of OutW
192 stored_data_next = {{OutW{1'b0}}, stored_data[Width-1:OutW]};
==>
193 stored_mask_next = {{OutW{1'b0}}, stored_mask[Width-1:OutW]};
194 end
195 2'b 10: begin
196 // ack_in : Store concat data
197 stored_data_next = concat_data[0+:Width];
==>
198 stored_mask_next = concat_mask[0+:Width];
199 end
200 2'b 11: begin
201 // both : shift the concat_data
202 stored_data_next = concat_data[ConcatW-1:OutW];
==>
203 stored_mask_next = concat_mask[ConcatW-1:OutW];
204 end
205 default: begin
206 stored_data_next = stored_data;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 2'b00 |
Covered |
T1,T2,T3 |
|
| 2'b01 |
Covered |
T1,T2,T3 |
|
| 2'b10 |
Covered |
T1,T2,T3 |
|
| 2'b11 |
Covered |
T26,T27 |
|
| default |
Excluded |
|
VC_COV_UNR |
214 if (!rst_ni) begin
-1-
215 stored_data <= '0;
==>
216 stored_mask <= '0;
217 end else if (flush_done) begin
-2-
218 stored_data <= '0;
==>
219 stored_mask <= '0;
220 end else begin
221 stored_data <= stored_data_next;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
235 if (!rst_ni) begin
-1-
236 flush_st <= FlushIdle;
==>
237 end else begin
238 flush_st <= flush_st_next;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
248 unique case (flush_st)
-1-
249 FlushIdle: begin
250 if (flush_i) begin
-2-
251 flush_st_next = FlushSend;
==>
252 end else begin
253 flush_st_next = FlushIdle;
==>
254 end
255 end
256
257 FlushSend: begin
258 if (pos_q == '0) begin
-3-
259 flush_st_next = FlushIdle;
==>
260
261 flush_valid = 1'b 0;
262 flush_done = 1'b 1;
263 end else begin
264 flush_st_next = FlushSend;
==>
265
266 flush_valid = 1'b 1;
267 flush_done = 1'b 0;
268 end
269 end
270 default: begin
271 flush_st_next = FlushIdle;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
Branches:
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
| FlushIdle |
1 |
- |
Covered |
T1,T2,T3 |
|
| FlushIdle |
0 |
- |
Covered |
T1,T2,T3 |
|
| FlushSend |
- |
1 |
Covered |
T1,T2,T3 |
|
| FlushSend |
- |
0 |
Covered |
T1,T2,T3 |
|
| default |
- |
- |
Excluded |
|
VC_COV_UNR |
80 unique case ({ack_in, ack_out})
-1-
81 2'b00: pos_d = pos_q;
==>
82 2'b01: pos_d = (int'(pos_q) <= OutW) ? '0 : pos_q - PtrW'(OutW);
-2-
==>
==> (Unreachable)
83 2'b10: pos_d = pos_with_input;
==>
84 2'b11: pos_d = (int'(pos_with_input) <= OutW) ? '0 : pos_with_input - PtrW'(OutW);
-3-
==>
==> (Unreachable)
85 default: pos_d = pos_q;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
Branches:
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
| 2'b00 |
- |
- |
Covered |
T1,T2,T3 |
|
| 2'b01 |
1 |
- |
Covered |
T1,T2,T3 |
|
| 2'b01 |
0 |
- |
Unreachable |
T1,T2,T3 |
|
| 2'b10 |
- |
- |
Covered |
T1,T2,T3 |
|
| 2'b11 |
- |
1 |
Not Covered |
|
|
| 2'b11 |
- |
0 |
Unreachable |
T26,T27 |
|
| default |
- |
- |
Excluded |
|
VC_COV_UNR |
90 if (!rst_ni) begin
-1-
91 pos_q <= '0;
==>
92 end else if (flush_done) begin
-2-
93 pos_q <= '0;
==>
94 end else begin
95 pos_q <= pos_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_packer
Assertion Details
DataIStable_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
124 |
0 |
491 |
| T7 |
525918 |
0 |
0 |
1 |
| T11 |
49077 |
2 |
0 |
1 |
| T12 |
0 |
6 |
0 |
0 |
| T13 |
0 |
3 |
0 |
0 |
| T23 |
64201 |
0 |
0 |
1 |
| T25 |
150727 |
0 |
0 |
1 |
| T26 |
0 |
40 |
0 |
0 |
| T27 |
0 |
40 |
0 |
0 |
| T28 |
0 |
22 |
0 |
0 |
| T29 |
0 |
11 |
0 |
0 |
| T30 |
967121 |
0 |
0 |
1 |
| T31 |
274978 |
0 |
0 |
1 |
| T32 |
118016 |
0 |
0 |
1 |
| T33 |
535314 |
0 |
0 |
1 |
| T34 |
352788 |
0 |
0 |
1 |
| T35 |
791875 |
0 |
0 |
1 |
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
263 |
0 |
491 |
| T7 |
525918 |
0 |
0 |
1 |
| T11 |
49077 |
10 |
0 |
1 |
| T12 |
0 |
12 |
0 |
0 |
| T13 |
0 |
10 |
0 |
0 |
| T23 |
64201 |
0 |
0 |
1 |
| T25 |
150727 |
0 |
0 |
1 |
| T26 |
0 |
106 |
0 |
0 |
| T27 |
0 |
80 |
0 |
0 |
| T28 |
0 |
28 |
0 |
0 |
| T29 |
0 |
17 |
0 |
0 |
| T30 |
967121 |
0 |
0 |
1 |
| T31 |
274978 |
0 |
0 |
1 |
| T32 |
118016 |
0 |
0 |
1 |
| T33 |
535314 |
0 |
0 |
1 |
| T34 |
352788 |
0 |
0 |
1 |
| T35 |
791875 |
0 |
0 |
1 |
ExFlushValid_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
16430 |
0 |
0 |
| T1 |
26133 |
5 |
0 |
0 |
| T2 |
101693 |
26 |
0 |
0 |
| T3 |
57307 |
8 |
0 |
0 |
| T4 |
6245 |
3 |
0 |
0 |
| T5 |
503225 |
22 |
0 |
0 |
| T6 |
123077 |
8 |
0 |
0 |
| T10 |
374472 |
180 |
0 |
0 |
| T15 |
4975 |
0 |
0 |
0 |
| T16 |
907 |
0 |
0 |
0 |
| T17 |
472274 |
135 |
0 |
0 |
| T18 |
0 |
17 |
0 |
0 |
| T19 |
0 |
6 |
0 |
0 |
ExcessiveDataStored_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
8 |
0 |
0 |
| T26 |
116918 |
4 |
0 |
0 |
| T27 |
0 |
4 |
0 |
0 |
| T36 |
139310 |
0 |
0 |
0 |
| T37 |
23316 |
0 |
0 |
0 |
| T38 |
49674 |
0 |
0 |
0 |
| T39 |
169668 |
0 |
0 |
0 |
| T40 |
136384 |
0 |
0 |
0 |
| T41 |
113706 |
0 |
0 |
0 |
| T42 |
190468 |
0 |
0 |
0 |
| T43 |
1303 |
0 |
0 |
0 |
| T44 |
3045 |
0 |
0 |
0 |
ExcessiveMaskStored_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
8 |
0 |
0 |
| T26 |
116918 |
4 |
0 |
0 |
| T27 |
0 |
4 |
0 |
0 |
| T36 |
139310 |
0 |
0 |
0 |
| T37 |
23316 |
0 |
0 |
0 |
| T38 |
49674 |
0 |
0 |
0 |
| T39 |
169668 |
0 |
0 |
0 |
| T40 |
136384 |
0 |
0 |
0 |
| T41 |
113706 |
0 |
0 |
0 |
| T42 |
190468 |
0 |
0 |
0 |
| T43 |
1303 |
0 |
0 |
0 |
| T44 |
3045 |
0 |
0 |
0 |
FlushFollowedByDone_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
16430 |
0 |
491 |
| T1 |
26133 |
5 |
0 |
1 |
| T2 |
101693 |
26 |
0 |
1 |
| T3 |
57307 |
8 |
0 |
1 |
| T4 |
6245 |
3 |
0 |
1 |
| T5 |
503225 |
22 |
0 |
1 |
| T6 |
123077 |
8 |
0 |
1 |
| T10 |
374472 |
180 |
0 |
1 |
| T15 |
4975 |
0 |
0 |
1 |
| T16 |
907 |
0 |
0 |
1 |
| T17 |
472274 |
135 |
0 |
1 |
| T18 |
0 |
17 |
0 |
0 |
| T19 |
0 |
6 |
0 |
0 |
ValidIDeassertedOnFlush_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
26325 |
0 |
0 |
| T1 |
26133 |
6 |
0 |
0 |
| T2 |
101693 |
45 |
0 |
0 |
| T3 |
57307 |
12 |
0 |
0 |
| T4 |
6245 |
5 |
0 |
0 |
| T5 |
503225 |
37 |
0 |
0 |
| T6 |
123077 |
11 |
0 |
0 |
| T10 |
374472 |
180 |
0 |
0 |
| T15 |
4975 |
0 |
0 |
0 |
| T16 |
907 |
0 |
0 |
0 |
| T17 |
472274 |
135 |
0 |
0 |
| T18 |
0 |
31 |
0 |
0 |
| T19 |
0 |
11 |
0 |
0 |
ValidOAssertedForStoredDataGTEOutW_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
7068105 |
0 |
0 |
| T1 |
26133 |
1766 |
0 |
0 |
| T2 |
101693 |
926 |
0 |
0 |
| T3 |
57307 |
4502 |
0 |
0 |
| T4 |
6245 |
160 |
0 |
0 |
| T5 |
503225 |
10375 |
0 |
0 |
| T6 |
123077 |
2374 |
0 |
0 |
| T10 |
374472 |
5760 |
0 |
0 |
| T15 |
4975 |
0 |
0 |
0 |
| T16 |
907 |
0 |
0 |
0 |
| T17 |
472274 |
4320 |
0 |
0 |
| T18 |
0 |
6985 |
0 |
0 |
| T19 |
0 |
3199 |
0 |
0 |
ValidOPairedWidthReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
263 |
0 |
0 |
| T7 |
525918 |
0 |
0 |
0 |
| T11 |
49077 |
10 |
0 |
0 |
| T12 |
0 |
12 |
0 |
0 |
| T13 |
0 |
10 |
0 |
0 |
| T23 |
64201 |
0 |
0 |
0 |
| T25 |
150727 |
0 |
0 |
0 |
| T26 |
0 |
106 |
0 |
0 |
| T27 |
0 |
80 |
0 |
0 |
| T28 |
0 |
28 |
0 |
0 |
| T29 |
0 |
17 |
0 |
0 |
| T30 |
967121 |
0 |
0 |
0 |
| T31 |
274978 |
0 |
0 |
0 |
| T32 |
118016 |
0 |
0 |
0 |
| T33 |
535314 |
0 |
0 |
0 |
| T34 |
352788 |
0 |
0 |
0 |
| T35 |
791875 |
0 |
0 |
0 |
gen_mask_assert.ContiguousOnesMask_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
418448798 |
9248780 |
0 |
0 |
| T1 |
26133 |
2415 |
0 |
0 |
| T2 |
101693 |
1315 |
0 |
0 |
| T3 |
57307 |
4775 |
0 |
0 |
| T4 |
6245 |
224 |
0 |
0 |
| T5 |
503225 |
10459 |
0 |
0 |
| T6 |
123077 |
2404 |
0 |
0 |
| T10 |
374472 |
8114 |
0 |
0 |
| T15 |
4975 |
0 |
0 |
0 |
| T16 |
907 |
0 |
0 |
0 |
| T17 |
472274 |
6098 |
0 |
0 |
| T18 |
0 |
7418 |
0 |
0 |
| T19 |
0 |
4409 |
0 |
0 |