Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16791534	1			T2	582		T4	557		T5	1957
all_values[1]	16791534	1			T2	582		T4	557		T5	1957
all_values[2]	16791534	1			T2	582		T4	557		T5	1957

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

236671

1

T2

55

T5

230

T6

94

auto[1]

50137931

1

T2

1691

T4

1671

T5

5641

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42954806

1

T2

1187

T4

1422

T5

5213

auto[1]

7419796

1

T2

559

T4

249

T5

658

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	71498	1			T5	113		T7	134		T60	937
all_values[0]	auto[0]	auto[1]	331	1			T5	2		T7	2		T28	2
all_values[0]	auto[1]	auto[0]	16701346	1			T2	582		T4	551		T5	1812
all_values[0]	auto[1]	auto[1]	18359	1			T4	6		T5	30		T6	23
all_values[1]	auto[0]	auto[0]	76993	1			T5	115		T6	94		T16	401
all_values[1]	auto[0]	auto[1]	144	1			T71	3		T12	2		T24	1
all_values[1]	auto[1]	auto[0]	16714126	1			T2	582		T4	557		T5	1842
all_values[1]	auto[1]	auto[1]	271	1			T28	3		T21	1		T22	3
all_values[2]	auto[0]	auto[0]	41554	1			T2	14		T9	1		T60	239
all_values[2]	auto[0]	auto[1]	46151	1			T2	41		T9	1		T60	698
all_values[2]	auto[1]	auto[0]	9349289	1			T2	9		T4	314		T5	1331
all_values[2]	auto[1]	auto[1]	7354540	1			T2	518		T4	243		T5	626