ASSERT | PROPERTIES | SEQUENCES | |
Total | 385 | 0 | 10 |
Category 0 | 385 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 385 | 0 | 10 |
Severity 0 | 385 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 385 | 100.00 |
Uncovered | 8 | 2.08 |
Success | 377 | 97.92 |
Failure | 0 | 0.00 |
Incomplete | 3 | 0.78 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_packer.ExcessiveDataStored_A | 0 | 0 | 445635965 | 0 | 0 | 0 | |
tb.dut.u_packer.ExcessiveMaskStored_A | 0 | 0 | 445635965 | 0 | 0 | 0 | |
tb.dut.u_tlul_adapter.rvalidHighReqFifoEmpty | 0 | 0 | 445635965 | 0 | 0 | 0 | |
tb.dut.u_tlul_adapter.rvalidHighWhenRspFifoFull | 0 | 0 | 445635965 | 0 | 0 | 0 | |
tb.dut.u_tlul_adapter.u_rspfifo.DataKnown_A | 0 | 0 | 445635965 | 0 | 0 | 0 | |
tb.dut.u_tlul_adapter.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth | 0 | 0 | 445635965 | 0 | 0 | 0 | |
tb.dut.u_tlul_adapter.u_sramreqfifo.DataKnown_A | 0 | 0 | 445635965 | 0 | 0 | 0 | |
tb.dut.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth | 0 | 0 | 445635965 | 0 | 0 | 0 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_packer.DataIStable_M | 0 | 0 | 445635965 | 19 | 0 | 492 | |
tb.dut.u_packer.DataOStableWhenPending_A | 0 | 0 | 445635965 | 40 | 0 | 492 | |
tb.dut.u_packer.FlushFollowedByDone_A | 0 | 0 | 445635965 | 16081 | 0 | 492 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 458564658 | 2184 | 2184 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 458564658 | 807 | 807 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 458564658 | 821 | 821 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 458564658 | 547 | 547 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 458564658 | 54 | 54 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 458564658 | 437 | 437 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 458564658 | 129 | 129 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 458564658 | 8220 | 8220 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 458564658 | 16405 | 16405 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 458564658 | 39585869 | 39585869 | 632 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 458564658 | 2184 | 2184 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 458564658 | 807 | 807 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 458564658 | 821 | 821 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 458564658 | 547 | 547 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 458564658 | 54 | 54 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 458564658 | 437 | 437 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 458564658 | 129 | 129 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 458564658 | 8220 | 8220 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 458564658 | 16405 | 16405 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 458564658 | 39585869 | 39585869 | 632 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |