Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114110

1

T2

4

T4

14

T5

24

auto[1]

113534

1

T4

338

T5

32

T6

20

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	85541	1			T4	70		T9	4		T7	2
len_1026_2046	5771	1			T4	7		T5	1		T6	3
len_514_1022	3292	1			T4	2		T5	3		T6	2
len_2_510	3442	1			T4	1		T6	3		T31	14
len_2056	158	1			T5	5		T53	2		T142	1
len_2048	303	1			T18	2		T31	2		T17	1
len_2040	157	1			T5	2		T7	2		T53	3
len_1032	167	1			T5	3		T7	3		T18	3
len_1024	1790	1			T4	1		T5	2		T6	8
len_1016	118	1			T5	3		T6	2		T7	2
len_520	462	1			T5	4		T6	2		T51	1
len_512	416	1			T5	3		T6	1		T7	2
len_504	208	1			T5	1		T7	4		T18	2
len_8	898	1			T12	4		T143	9		T144	3
len_0	11098	1			T2	2		T4	95		T5	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

104

1

T7

2

T31

2

T17

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	44539	1			T9	4		T7	2		T8	12
auto[0]	len_1026_2046	3055	1			T5	1		T6	1		T7	2
auto[0]	len_514_1022	1876	1			T5	1		T6	2		T7	1
auto[0]	len_2_510	1931	1			T6	3		T31	11		T17	116
auto[0]	len_2056	76	1			T5	4		T53	1		T94	2
auto[0]	len_2048	164	1			T31	1		T17	1		T54	3
auto[0]	len_2040	81	1			T5	1		T7	2		T53	1
auto[0]	len_1032	84	1			T7	1		T18	2		T53	2
auto[0]	len_1024	238	1			T5	2		T6	3		T7	2
auto[0]	len_1016	63	1			T5	1		T6	2		T142	1
auto[0]	len_520	315	1			T5	2		T78	1		T145	4
auto[0]	len_512	209	1			T7	2		T31	2		T17	1
auto[0]	len_504	112	1			T7	2		T53	1		T146	1
auto[0]	len_8	29	1			T84	10		T147	1		T148	2
auto[0]	len_0	4282	1			T2	2		T4	7		T6	3
auto[1]	len_2050_plus	41002	1			T4	70		T8	5		T16	9
auto[1]	len_1026_2046	2716	1			T4	7		T6	2		T18	1
auto[1]	len_514_1022	1416	1			T4	2		T5	2		T18	4
auto[1]	len_2_510	1511	1			T4	1		T31	3		T17	172
auto[1]	len_2056	82	1			T5	1		T53	1		T142	1
auto[1]	len_2048	139	1			T18	2		T31	1		T53	1
auto[1]	len_2040	76	1			T5	1		T53	2		T146	2
auto[1]	len_1032	83	1			T5	3		T7	2		T18	1
auto[1]	len_1024	1552	1			T4	1		T6	5		T30	65
auto[1]	len_1016	55	1			T5	2		T7	2		T53	1
auto[1]	len_520	147	1			T5	2		T6	2		T51	1
auto[1]	len_512	207	1			T5	3		T6	1		T17	1
auto[1]	len_504	96	1			T5	1		T7	2		T18	2
auto[1]	len_8	869	1			T12	4		T143	9		T144	3
auto[1]	len_0	6816	1			T4	88		T5	1		T16	1

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

43

1

T7

2

T31

2

T17

1

auto[1]

len_upper

61

1

T28

1

T21

1

T45

1