Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4179704

1

T2

2

T4

38

T5

372

auto[1]

2499837

1

T2

30

T4

724

T5

562

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2513327

1

T2

1

T4

580

T5

359

auto[1]

4166214

1

T2

31

T4

182

T5

575

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3040099

1

T2

3

T4

65

T5

454

auto[1]

3639442

1

T2

29

T4

697

T5

480

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4205356

1

T2

2

T4

558

T5

564

auto[1]

2474185

1

T2

30

T4

204

T5

370

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6141700	1			T2	32		T4	731		T5	915
fifo_depth[1]	104425	1			T4	6		T5	10		T6	11
fifo_depth[2]	75448	1			T4	14		T5	6		T6	4
fifo_depth[3]	56919	1			T4	5		T6	1		T9	52
fifo_depth[4]	50120	1			T4	4		T5	2		T9	47
fifo_depth[5]	39362	1			T4	1		T5	1		T9	44
fifo_depth[6]	31141	1			T9	27		T7	5		T30	138
fifo_depth[7]	20995	1			T4	1		T9	19		T7	2

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

537841

1

T4

31

T5

19

T6

16

auto[1]

6141700

1

T2

32

T4

731

T5

915

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6672364

1

T2

32

T4

762

T5

934

auto[1]

7177

1

T27

54

T28

398

T29

1091

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

18672

1

T9

131

T7

6

T31

64

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

19604

1

T5

1

T31

38

T17

38

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

23960

1

T7

3

T8

1

T16

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

19777

1

T9

117

T7

5

T16

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

135868

1

T16

1

T31

2

T54

29

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

24172

1

T5

1

T6

1

T9

43

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

22224

1

T5

4

T6

2

T8

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

16730

1

T7

10

T31

19

T17

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

33842

1

T4

4

T6

6

T16

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

34325

1

T5

5

T7

3

T18

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

33282

1

T4

2

T6

3

T18

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

31433

1

T4

19

T7

14

T8

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

33743

1

T6

2

T30

1260

T8

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

27382

1

T7

10

T18

3

T17

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

30309

1

T4

6

T5

4

T18

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

32518

1

T5

4

T6

2

T16

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

153911

1

T5

84

T6

1

T9

246

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

149129

1

T5

62

T6

70

T7

15

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

142664

1

T2

1

T5

26

T6

17

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

160488

1

T5

7

T6

23

T9

374

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1709409

1

T5

60

T8

1

T16

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

148749

1

T2

2

T5

22

T6

124

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

152759

1

T4

65

T5

96

T6

63

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

141983

1

T5

91

T6

43

T7

68

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

427318

1

T4

34

T5

4

T6

62

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

431351

1

T5

50

T6

48

T9

497

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

410475

1

T4

376

T5

75

T6

65

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

423096

1

T4

145

T5

45

T6

6

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

432774

1

T5

83

T6

15

T7

67

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

399455

1

T7

37

T18

21

T8

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

444146

1

T2

1

T4

71

T5

128

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

413993

1

T2

28

T4

40

T5

82

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

172309

1

T5

84

T6

1

T9

377

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

168548

1

T5

63

T6

70

T7

15

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

166066

1

T2

1

T5

26

T6

17

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

179756

1

T5

7

T6

23

T9

491

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1844738

1

T5

60

T8

1

T16

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

172249

1

T2

2

T5

23

T6

125

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

174625

1

T4

65

T5

100

T6

65

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

158435

1

T5

91

T6

43

T7

78

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

460842

1

T4

38

T5

4

T6

68

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

465329

1

T5

55

T6

48

T9

497

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

442987

1

T4

378

T5

75

T6

68

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

454256

1

T4

164

T5

45

T6

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

466351

1

T5

83

T6

17

T7

67

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

426374

1

T7

47

T18

24

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

474241

1

T2

1

T4

77

T5

132

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

445258

1

T2

28

T4

40

T5

86

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

274

1

T56

6

T151

47

T152

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

185

1

T28

6

T151

7

T152

35

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

558

1

T56

7

T24

12

T152

22

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

509

1

T29

7

T56

258

T153

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

539

1

T29

54

T151

11

T154

132

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

672

1

T28

33

T29

6

T56

117

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

358

1

T28

144

T24

82

T152

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

278

1

T27

54

T28

112

T155

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

318

1

T28

19

T24

1

T152

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

347

1

T152

11

T156

8

T157

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

770

1

T56

8

T151

35

T152

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

273

1

T28

25

T22

69

T151

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

166

1

T28

3

T158

6

T159

149

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

463

1

T155

3

T154

1

T158

26

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

214

1

T29

4

T22

15

T158

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1253

1

T28

56

T29

1020

T151

19

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

153911

1

T5

84

T6

1

T9

246

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

149129

1

T5

62

T6

70

T7

15

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

142664

1

T2

1

T5

26

T6

17

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

160488

1

T5

7

T6

23

T9

374

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1709409

1

T5

60

T8

1

T16

2

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

148749

1

T2

2

T5

22

T6

124

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

152759

1

T4

65

T5

96

T6

63

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

141983

1

T5

91

T6

43

T7

68

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

427318

1

T4

34

T5

4

T6

62

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

431351

1

T5

50

T6

48

T9

497

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

410475

1

T4

376

T5

75

T6

65

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

423096

1

T4

145

T5

45

T6

6

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

432774

1

T5

83

T6

15

T7

67

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

399455

1

T7

37

T18

21

T8

1

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

444146

1

T2

1

T4

71

T5

128

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

413993

1

T2

28

T4

40

T5

82

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3089

1

T9

22

T7

3

T31

5

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

2626

1

T5

1

T31

8

T17

1

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

2717

1

T7

1

T17

1

T52

5

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3004

1

T9

20

T7

1

T16

1

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

38884

1

T31

2

T54

24

T23

16

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3105

1

T5

1

T9

4

T31

4

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

2763

1

T5

3

T6

2

T16

1

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

2441

1

T7

1

T27

1

T54

12

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

6068

1

T6

5

T53

1

T51

14

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

5866

1

T7

1

T17

1

T52

5

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

5902

1

T6

2

T18

2

T60

11

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

5480

1

T4

6

T17

36

T51

18

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

6969

1

T6

1

T30

216

T31

7

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

4912

1

T7

1

T53

3

T149

17

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

5190

1

T5

3

T18

2

T8

1

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

5409

1

T5

2

T6

1

T31

2

fifo_depth[2]

auto[0]

auto[0]

auto[0]

auto[0]

2378

1

T9

17

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1

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28

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1

T31

6

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5

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2

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1

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1

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4

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2

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1

T9

19

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3

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3

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1

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1

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20

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8

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1

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1

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6

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4

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1

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1

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1

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12

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1

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13

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26

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1

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2

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1

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1

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1

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4

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1

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15

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1

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2

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1

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6

fifo_depth[2]

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1

T4

4

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2

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30

fifo_depth[2]

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1

T6

1

T30

201

T31

15

fifo_depth[2]

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3753

1

T18

1

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9

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8

fifo_depth[2]

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1

T4

6

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1

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3

fifo_depth[2]

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1

T6

1

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4

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1

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1

T9

31

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1

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6

fifo_depth[3]

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1

T31

8

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1

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2

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1

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1

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5

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6

fifo_depth[3]

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1

T9

15

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1

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3

fifo_depth[3]

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1

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14

T45

3

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5

fifo_depth[3]

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1

T9

6

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7

T51

20

fifo_depth[3]

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1

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3

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20

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6

fifo_depth[3]

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1

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1

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1

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11

fifo_depth[3]

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1

T51

11

T52

1

T10

5

fifo_depth[3]

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auto[0]

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1

T17

1

T52

1

T46

28

fifo_depth[3]

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auto[0]

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1

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1

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1

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1

fifo_depth[3]

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3383

1

T4

5

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2

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15

fifo_depth[3]

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1

T30

194

T31

4

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9

fifo_depth[3]

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auto[1]

3067

1

T7

3

T18

2

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2

fifo_depth[3]

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auto[0]

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1

T31

6

T17

1

T29

5

fifo_depth[3]

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auto[1]

auto[1]

3349

1

T16

1

T31

4

T23

21

fifo_depth[4]

auto[0]

auto[0]

auto[0]

auto[0]

1560

1

T9

24

T7

1

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9

fifo_depth[4]

auto[0]

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1355

1

T31

9

T17

13

T23

16

fifo_depth[4]

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auto[0]

1256

1

T17

4

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2

T28

8

fifo_depth[4]

auto[0]

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1

T9

18

T7

1

T31

3

fifo_depth[4]

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auto[0]

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1

T23

18

T29

2

T46

9

fifo_depth[4]

auto[0]

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auto[0]

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1576

1

T9

5

T31

6

T51

28

fifo_depth[4]

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auto[0]

1519

1

T31

11

T51

30

T52

1

fifo_depth[4]

auto[0]

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auto[1]

auto[1]

1155

1

T7

1

T31

13

T17

8

fifo_depth[4]

auto[1]

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auto[0]

auto[0]

3352

1

T4

2

T51

20

T10

4

fifo_depth[4]

auto[1]

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auto[0]

auto[1]

3489

1

T5

1

T7

1

T17

14

fifo_depth[4]

auto[1]

auto[0]

auto[1]

auto[0]

3238

1

T54

6

T56

1

T26

16

fifo_depth[4]

auto[1]

auto[0]

auto[1]

auto[1]

3194

1

T4

2

T7

2

T31

30

fifo_depth[4]

auto[1]

auto[1]

auto[0]

auto[0]

3704

1

T30

189

T8

1

T31

12

fifo_depth[4]

auto[1]

auto[1]

auto[0]

auto[1]

2858

1

T17

3

T54

11

T45

1

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[0]

3001

1

T31

8

T29

6

T22

12

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[1]

3049

1

T5

1

T31

3

T23

11

fifo_depth[5]

auto[0]

auto[0]

auto[0]

auto[0]

1197

1

T9

20

T31

7

T17

4

fifo_depth[5]

auto[0]

auto[0]

auto[0]

auto[1]

909

1

T31

2

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2

T52

1

fifo_depth[5]

auto[0]

auto[0]

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auto[0]

949

1

T7

2

T17

1

T10

2

fifo_depth[5]

auto[0]

auto[0]

auto[1]

auto[1]

1117

1

T9

19

T31

2

T27

2

fifo_depth[5]

auto[0]

auto[1]

auto[0]

auto[0]

9909

1

T54

3

T23

22

T150

1

fifo_depth[5]

auto[0]

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auto[1]

1204

1

T9

5

T31

4

T51

21

fifo_depth[5]

auto[0]

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auto[0]

1155

1

T31

2

T51

21

T52

1

fifo_depth[5]

auto[0]

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auto[1]

830

1

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3

T17

1

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1

fifo_depth[5]

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auto[0]

2859

1

T54

1

T51

13

T23

20

fifo_depth[5]

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auto[0]

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2974

1

T18

1

T46

18

T47

29

fifo_depth[5]

auto[1]

auto[0]

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auto[0]

2825

1

T145

1

T160

11

T161

2

fifo_depth[5]

auto[1]

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auto[1]

auto[1]

2681

1

T4

1

T7

1

T31

2

fifo_depth[5]

auto[1]

auto[1]

auto[0]

auto[0]

3076

1

T30

175

T31

6

T162

159

fifo_depth[5]

auto[1]

auto[1]

auto[0]

auto[1]

2346

1

T54

1

T78

1

T45

1

fifo_depth[5]

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auto[1]

auto[0]

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1

T18

1

T31

6

T29

4

fifo_depth[5]

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auto[1]

auto[1]

2631

1

T5

1

T31

2

T23

9

fifo_depth[6]

auto[0]

auto[0]

auto[0]

auto[0]

1035

1

T9

11

T31

4

T17

5

fifo_depth[6]

auto[0]

auto[0]

auto[0]

auto[1]

716

1

T31

2

T17

5

T54

1

fifo_depth[6]

auto[0]

auto[0]

auto[1]

auto[0]

819

1

T17

2

T10

1

T28

7

fifo_depth[6]

auto[0]

auto[0]

auto[1]

auto[1]

945

1

T9

11

T7

2

T31

1

fifo_depth[6]

auto[0]

auto[1]

auto[0]

auto[0]

7212

1

T23

26

T20

1

T46

10

fifo_depth[6]

auto[0]

auto[1]

auto[0]

auto[1]

886

1

T9

5

T31

2

T51

12

fifo_depth[6]

auto[0]

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auto[1]

auto[0]

1022

1

T31

7

T51

18

T23

10

fifo_depth[6]

auto[0]

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auto[1]

auto[1]

664

1

T7

1

T54

7

T51

29

fifo_depth[6]

auto[1]

auto[0]

auto[0]

auto[0]

2284

1

T51

21

T10

1

T23

8

fifo_depth[6]

auto[1]

auto[0]

auto[0]

auto[1]

2429

1

T7

1

T17

4

T46

9

fifo_depth[6]

auto[1]

auto[0]

auto[1]

auto[0]

2247

1

T26

9

T160

4

T161

1

fifo_depth[6]

auto[1]

auto[0]

auto[1]

auto[1]

2252

1

T7

1

T31

8

T54

1

fifo_depth[6]

auto[1]

auto[1]

auto[0]

auto[0]

2419

1

T30

138

T31

14

T162

161

fifo_depth[6]

auto[1]

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auto[0]

auto[1]

1858

1

T54

2

T47

9

T94

1

fifo_depth[6]

auto[1]

auto[1]

auto[1]

auto[0]

2164

1

T31

4

T29

2

T22

9

fifo_depth[6]

auto[1]

auto[1]

auto[1]

auto[1]

2189

1

T31

2

T23

1

T94

1

fifo_depth[7]

auto[0]

auto[0]

auto[0]

auto[0]

611

1

T9

3

T31

3

T17

3

fifo_depth[7]

auto[0]

auto[0]

auto[0]

auto[1]

522

1

T31

2

T17

1

T23

1

fifo_depth[7]

auto[0]

auto[0]

auto[1]

auto[0]

657

1

T28

6

T56

1

T160

3

fifo_depth[7]

auto[0]

auto[0]

auto[1]

auto[1]

620

1

T9

9

T31

1

T27

3

fifo_depth[7]

auto[0]

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auto[0]

auto[0]

4224

1

T23

12

T46

6

T47

20

fifo_depth[7]

auto[0]

auto[1]

auto[0]

auto[1]

620

1

T9

7

T31

4

T51

10

fifo_depth[7]

auto[0]

auto[1]

auto[1]

auto[0]

629

1

T31

1

T51

14

T23

6

fifo_depth[7]

auto[0]

auto[1]

auto[1]

auto[1]

534

1

T27

6

T54

5

T51

13

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[0]

1568

1

T51

10

T23

10

T28

18

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[1]

1560

1

T46

3

T47

6

T55

1

fifo_depth[7]

auto[1]

auto[0]

auto[1]

auto[0]

1581

1

T17

2

T56

13

T26

1

fifo_depth[7]

auto[1]

auto[0]

auto[1]

auto[1]

1504

1

T4

1

T7

1

T16

1

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[0]

1795

1

T30

77

T31

2

T162

179

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[1]

1386

1

T7

1

T47

10

T163

8

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[0]

1608

1

T31

3

T29

4

T22

6

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[1]

1576

1

T31

5

T23

1

T28

1