Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16791534	1			T2	582		T4	557		T5	1957
all_pins[1]	16791534	1			T2	582		T4	557		T5	1957
all_pins[2]	16791534	1			T2	582		T4	557		T5	1957

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	43000653	1			T2	1228		T4	1421		T5	5215
values[0x1]	7373949	1			T2	518		T4	250		T5	656
transitions[0x0=>0x1]	7373811	1			T2	518		T4	250		T5	656
transitions[0x1=>0x0]	7373824	1			T2	518		T4	250		T5	656

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16772410	1			T2	582		T4	550		T5	1927
all_pins[0]	values[0x1]	19124	1			T4	7		T5	30		T6	24
all_pins[0]	transitions[0x0=>0x1]	19069	1			T4	7		T5	30		T6	24
all_pins[0]	transitions[0x1=>0x0]	7354498	1			T2	518		T4	243		T5	626
all_pins[1]	values[0x0]	16791249	1			T2	582		T4	557		T5	1957
all_pins[1]	values[0x1]	285	1			T28	4		T21	1		T22	3
all_pins[1]	transitions[0x0=>0x1]	254	1			T28	4		T21	1		T22	3
all_pins[1]	transitions[0x1=>0x0]	19093	1			T4	7		T5	30		T6	24
all_pins[2]	values[0x0]	9436994	1			T2	64		T4	314		T5	1331
all_pins[2]	values[0x1]	7354540	1			T2	518		T4	243		T5	626
all_pins[2]	transitions[0x0=>0x1]	7354488	1			T2	518		T4	243		T5	626
all_pins[2]	transitions[0x1=>0x0]	233	1			T28	4		T21	1		T22	3