Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 827 1 T71 20 T12 10 T24 10
all_values[1] 827 1 T71 20 T12 10 T24 10
all_values[2] 827 1 T71 20 T12 10 T24 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1272 1 T71 30 T12 5 T24 8
auto[1] 1209 1 T71 30 T12 25 T24 22


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 880 1 T71 23 T12 9 T24 12
auto[1] 1601 1 T71 37 T12 21 T24 18


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1450 1 T71 36 T12 18 T24 19
auto[1] 1031 1 T71 24 T12 12 T24 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 173 1 T71 3 T24 1 T84 3
all_values[0] auto[0] auto[0] auto[1] 85 1 T71 2 T24 1 T83 1
all_values[0] auto[0] auto[1] auto[0] 147 1 T71 3 T12 4 T24 3
all_values[0] auto[0] auto[1] auto[1] 92 1 T71 3 T12 3 T24 2
all_values[0] auto[1] auto[0] auto[1] 190 1 T71 5 T12 1 T24 3
all_values[0] auto[1] auto[1] auto[1] 140 1 T71 4 T12 2 T84 1
all_values[1] auto[0] auto[0] auto[0] 148 1 T71 8 T25 2 T86 4
all_values[1] auto[0] auto[0] auto[1] 94 1 T71 2 T12 1 T24 1
all_values[1] auto[0] auto[1] auto[0] 140 1 T71 5 T12 1 T24 5
all_values[1] auto[0] auto[1] auto[1] 111 1 T71 1 T12 3 T24 1
all_values[1] auto[1] auto[0] auto[1] 164 1 T71 2 T12 3 T83 2
all_values[1] auto[1] auto[1] auto[1] 170 1 T71 2 T12 2 T24 3
all_values[2] auto[0] auto[0] auto[0] 142 1 T71 1 T83 2 T84 1
all_values[2] auto[0] auto[0] auto[1] 93 1 T71 3 T83 1 T84 1
all_values[2] auto[0] auto[1] auto[0] 130 1 T71 3 T12 4 T24 3
all_values[2] auto[0] auto[1] auto[1] 95 1 T71 2 T12 2 T24 2
all_values[2] auto[1] auto[0] auto[1] 183 1 T71 4 T24 2 T83 1
all_values[2] auto[1] auto[1] auto[1] 184 1 T71 7 T12 4 T24 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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