Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	3619	1			T2	1		T4	1		T5	8
sha2_none	3599	1			T2	1		T4	2		T5	5
sha2_512	7094	1			T4	3		T5	8		T6	10
sha2_384	6901	1			T2	1		T4	1		T5	9
sha2_256	5740	1			T2	2		T4	2		T5	12

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17379

1

T2

2

T4

2

T5

18

auto[1]

9918

1

T2

3

T4

7

T5

25

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9948

1

T2

1

T4

6

T5

19

auto[1]

17349

1

T2

4

T4

3

T5

24

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

14161

1

T2

2

T4

8

T5

20

disabled

13136

1

T2

3

T4

1

T5

23

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4076	1			T2	2		T5	9		T6	12
key_none	7390	1			T5	4		T6	5		T7	8
key_1024	4021	1			T2	1		T4	3		T5	6
key_512	3466	1			T4	1		T5	2		T6	3
key_384	2985	1			T2	1		T4	2		T5	5
key_256	2641	1			T4	1		T5	4		T6	9
key_128	2654	1			T2	1		T4	2		T5	13

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17565

1

T2

3

T4

6

T5

27

auto[1]

9732

1

T2

2

T4

3

T5

16

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

27083

1

T2

5

T4

9

T5

43

disabled

214

1

T60

1

T59

2

T61

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1451

1

T4

2

T5

2

T6

4

enabled

auto[0]

auto[0]

auto[1]

1460

1

T5

2

T6

2

T9

1

enabled

auto[0]

auto[1]

auto[0]

1431

1

T4

2

T5

2

T6

2

enabled

auto[0]

auto[1]

auto[1]

1425

1

T4

2

T5

1

T6

1

enabled

auto[1]

auto[0]

auto[0]

4131

1

T5

3

T6

3

T7

2

enabled

auto[1]

auto[0]

auto[1]

1378

1

T7

3

T18

1

T8

1

enabled

auto[1]

auto[1]

auto[0]

1572

1

T2

1

T4

1

T5

6

enabled

auto[1]

auto[1]

auto[1]

1313

1

T2

1

T4

1

T5

4

disabled

auto[0]

auto[0]

auto[0]

1050

1

T5

4

T6

1

T9

1

disabled

auto[0]

auto[0]

auto[1]

1003

1

T5

3

T6

4

T7

1

disabled

auto[0]

auto[1]

auto[0]

1043

1

T2

1

T5

4

T6

3

disabled

auto[0]

auto[1]

auto[1]

1085

1

T5

1

T6

4

T9

1

disabled

auto[1]

auto[0]

auto[0]

5846

1

T2

1

T5

3

T8

1

disabled

auto[1]

auto[0]

auto[1]

1060

1

T2

1

T5

1

T6

4

disabled

auto[1]

auto[1]

auto[0]

1041

1

T4

1

T5

3

T6

3

disabled

auto[1]

auto[1]

auto[1]

1008

1

T5

4

T6

3

T7

2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

14073

1

T2

2

T4

8

T5

20

enabled

disabled

88

1

T60

1

T59

1

T61

1

disabled

disabled

126

1

T59

1

T62

1

T63

3

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13010

1

T2

3

T4

1

T5

23

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	966	1			T5	3		T6	2		T9	1
key_invalid	sha2_none	729	1			T2	1		T6	2		T7	2
key_invalid	sha2_512	798	1			T5	1		T6	4		T7	1
key_invalid	sha2_384	734	1			T2	1		T5	2		T6	3
key_invalid	sha2_256	747	1			T5	3		T6	1		T9	1
key_none	sha2_invalid	422	1			T5	1		T6	1		T8	1
key_none	sha2_none	487	1			T6	1		T7	2		T53	1
key_none	sha2_512	2456	1			T5	1		T6	3		T7	2
key_none	sha2_384	2489	1			T5	2		T7	1		T18	1
key_none	sha2_256	1502	1			T7	2		T16	2		T31	3
key_1024	sha2_invalid	455	1			T5	1		T6	2		T8	2
key_1024	sha2_none	479	1			T18	2		T31	2		T17	1
key_1024	sha2_512	1654	1			T4	3		T5	1		T9	1
key_1024	sha2_384	843	1			T5	2		T8	1		T31	2
key_512	sha2_invalid	454	1			T6	1		T7	1		T8	2
key_512	sha2_none	473	1			T7	1		T18	2		T8	1
key_512	sha2_512	502	1			T5	1		T6	1		T18	1
key_512	sha2_384	1188	1			T4	1		T6	1		T7	2
key_512	sha2_256	813	1			T5	1		T30	45		T8	1
key_384	sha2_invalid	428	1			T5	1		T6	1		T7	2
key_384	sha2_none	470	1			T4	1		T5	1		T6	1
key_384	sha2_512	562	1			T5	1		T7	1		T8	1
key_384	sha2_384	513	1			T5	1		T6	2		T16	1
key_384	sha2_256	974	1			T2	1		T4	1		T5	1
key_256	sha2_invalid	420	1			T4	1		T5	1		T6	1
key_256	sha2_none	483	1			T5	1		T6	2		T7	2
key_256	sha2_512	537	1			T6	2		T53	1		T19	1
key_256	sha2_384	554	1			T7	2		T53	2		T27	1
key_256	sha2_256	621	1			T5	1		T6	4		T16	3
key_128	sha2_invalid	461	1			T2	1		T5	1		T6	1
key_128	sha2_none	468	1			T4	1		T5	3		T6	1
key_128	sha2_512	570	1			T5	3		T7	1		T8	1
key_128	sha2_384	569	1			T5	2		T6	2		T9	1
key_128	sha2_256	536	1			T4	1		T5	4		T8	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

532

1

T2

1

T5

2

T16

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	966	1			T5	3		T6	2		T9	1
key_invalid	sha2_none	729	1			T2	1		T6	2		T7	2
key_invalid	sha2_512	798	1			T5	1		T6	4		T7	1
key_invalid	sha2_384	734	1			T2	1		T5	2		T6	3
key_invalid	sha2_256	747	1			T5	3		T6	1		T9	1
key_none	sha2_invalid	422	1			T5	1		T6	1		T8	1
key_none	sha2_none	487	1			T6	1		T7	2		T53	1
key_none	sha2_512	2456	1			T5	1		T6	3		T7	2
key_none	sha2_384	2489	1			T5	2		T7	1		T18	1
key_none	sha2_256	1502	1			T7	2		T16	2		T31	3
key_1024	sha2_invalid	455	1			T5	1		T6	2		T8	2
key_1024	sha2_none	479	1			T18	2		T31	2		T17	1
key_1024	sha2_512	1654	1			T4	3		T5	1		T9	1
key_1024	sha2_384	843	1			T5	2		T8	1		T31	2
key_1024	sha2_256	532	1			T2	1		T5	2		T16	2
key_512	sha2_invalid	454	1			T6	1		T7	1		T8	2
key_512	sha2_none	473	1			T7	1		T18	2		T8	1
key_512	sha2_512	502	1			T5	1		T6	1		T18	1
key_512	sha2_384	1188	1			T4	1		T6	1		T7	2
key_512	sha2_256	813	1			T5	1		T30	45		T8	1
key_384	sha2_invalid	428	1			T5	1		T6	1		T7	2
key_384	sha2_none	470	1			T4	1		T5	1		T6	1
key_384	sha2_512	562	1			T5	1		T7	1		T8	1
key_384	sha2_384	513	1			T5	1		T6	2		T16	1
key_384	sha2_256	974	1			T2	1		T4	1		T5	1
key_256	sha2_invalid	420	1			T4	1		T5	1		T6	1
key_256	sha2_none	483	1			T5	1		T6	2		T7	2
key_256	sha2_512	537	1			T6	2		T53	1		T19	1
key_256	sha2_384	554	1			T7	2		T53	2		T27	1
key_256	sha2_256	621	1			T5	1		T6	4		T16	3
key_128	sha2_invalid	461	1			T2	1		T5	1		T6	1
key_128	sha2_none	468	1			T4	1		T5	3		T6	1
key_128	sha2_512	570	1			T5	3		T7	1		T8	1
key_128	sha2_384	569	1			T5	2		T6	2		T9	1
key_128	sha2_256	536	1			T4	1		T5	4		T8	1