Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.93 95.26 97.27 100.00 97.06 98.12 97.97 99.85


Total test records in report: 657
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html
T537 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.3362665197 Sep 09 07:48:36 PM UTC 24 Sep 09 07:48:38 PM UTC 24 54625232 ps
T538 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.114928523 Sep 09 07:48:37 PM UTC 24 Sep 09 07:48:40 PM UTC 24 15785844 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.1744459494 Sep 09 07:48:38 PM UTC 24 Sep 09 07:48:40 PM UTC 24 28987301 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.135609847 Sep 09 07:48:36 PM UTC 24 Sep 09 07:48:40 PM UTC 24 325949016 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.2688522756 Sep 09 07:48:34 PM UTC 24 Sep 09 07:48:41 PM UTC 24 158129296 ps
T539 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.439217972 Sep 09 07:48:41 PM UTC 24 Sep 09 07:48:44 PM UTC 24 52045481 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4255317866 Sep 09 07:48:41 PM UTC 24 Sep 09 07:48:45 PM UTC 24 137771122 ps
T540 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.3524850158 Sep 09 07:48:46 PM UTC 24 Sep 09 07:48:48 PM UTC 24 56220140 ps
T541 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.1015546501 Sep 09 07:48:42 PM UTC 24 Sep 09 07:48:49 PM UTC 24 317448805 ps
T542 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.4245325917 Sep 09 07:48:41 PM UTC 24 Sep 09 07:48:49 PM UTC 24 429973773 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.4241507051 Sep 09 07:48:31 PM UTC 24 Sep 09 07:48:51 PM UTC 24 3209812788 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.1883003544 Sep 09 07:48:45 PM UTC 24 Sep 09 07:48:51 PM UTC 24 372980922 ps
T543 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.3223456338 Sep 09 07:48:40 PM UTC 24 Sep 09 07:48:51 PM UTC 24 210164024 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.2414006875 Sep 09 07:48:49 PM UTC 24 Sep 09 07:48:51 PM UTC 24 21632001 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.1034533623 Sep 09 07:48:50 PM UTC 24 Sep 09 07:48:53 PM UTC 24 30852099 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1766773954 Sep 09 07:48:52 PM UTC 24 Sep 09 07:48:55 PM UTC 24 23154426 ps
T544 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.3334700349 Sep 09 07:48:53 PM UTC 24 Sep 09 07:48:56 PM UTC 24 974714783 ps
T545 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1712996847 Sep 09 07:48:52 PM UTC 24 Sep 09 07:48:57 PM UTC 24 107777443 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.3348268628 Sep 09 07:48:54 PM UTC 24 Sep 09 07:48:57 PM UTC 24 82360379 ps
T546 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.3703752117 Sep 09 07:48:56 PM UTC 24 Sep 09 07:48:58 PM UTC 24 19826990 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.1861225481 Sep 09 07:48:56 PM UTC 24 Sep 09 07:48:59 PM UTC 24 20792859 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.2767863602 Sep 09 07:48:51 PM UTC 24 Sep 09 07:49:02 PM UTC 24 1853260870 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.3496488976 Sep 09 07:49:01 PM UTC 24 Sep 09 07:49:04 PM UTC 24 36604681 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2686112069 Sep 09 07:49:02 PM UTC 24 Sep 09 07:49:07 PM UTC 24 418860454 ps
T547 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.2213245695 Sep 09 07:49:01 PM UTC 24 Sep 09 07:49:07 PM UTC 24 633800936 ps
T548 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.3776745800 Sep 09 07:49:02 PM UTC 24 Sep 09 07:49:07 PM UTC 24 218242459 ps
T549 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.2162830295 Sep 09 07:48:50 PM UTC 24 Sep 09 07:49:07 PM UTC 24 6093373859 ps
T550 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.3014439012 Sep 09 07:49:05 PM UTC 24 Sep 09 07:49:07 PM UTC 24 13587167 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.2160525558 Sep 09 07:49:04 PM UTC 24 Sep 09 07:49:09 PM UTC 24 363514046 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.1094097161 Sep 09 07:49:08 PM UTC 24 Sep 09 07:49:10 PM UTC 24 61760723 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.218465369 Sep 09 07:49:08 PM UTC 24 Sep 09 07:49:10 PM UTC 24 77111974 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.316060246 Sep 09 07:49:08 PM UTC 24 Sep 09 07:49:12 PM UTC 24 117172624 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.2193148407 Sep 09 07:49:08 PM UTC 24 Sep 09 07:49:14 PM UTC 24 743612776 ps
T551 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.784285467 Sep 09 07:49:10 PM UTC 24 Sep 09 07:49:15 PM UTC 24 353151893 ps
T552 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.2265266564 Sep 09 07:49:11 PM UTC 24 Sep 09 07:49:15 PM UTC 24 194796413 ps
T553 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.151056560 Sep 09 07:49:14 PM UTC 24 Sep 09 07:49:16 PM UTC 24 43084885 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.101754751 Sep 09 07:49:14 PM UTC 24 Sep 09 07:49:16 PM UTC 24 26582963 ps
T554 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.3137019902 Sep 09 07:49:11 PM UTC 24 Sep 09 07:49:17 PM UTC 24 84127870 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3192344038 Sep 09 07:49:14 PM UTC 24 Sep 09 07:49:17 PM UTC 24 219725942 ps
T555 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4008694697 Sep 09 07:49:15 PM UTC 24 Sep 09 07:49:18 PM UTC 24 25480793 ps
T556 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.483573243 Sep 09 07:49:15 PM UTC 24 Sep 09 07:49:18 PM UTC 24 96266489 ps
T557 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.1262695017 Sep 09 07:49:16 PM UTC 24 Sep 09 07:49:18 PM UTC 24 17846933 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.1776749876 Sep 09 07:49:17 PM UTC 24 Sep 09 07:49:20 PM UTC 24 16668394 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1219119795 Sep 09 07:49:17 PM UTC 24 Sep 09 07:49:20 PM UTC 24 118379263 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.2121764858 Sep 09 07:49:01 PM UTC 24 Sep 09 07:49:21 PM UTC 24 2227957555 ps
T558 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.1528501139 Sep 09 07:49:20 PM UTC 24 Sep 09 07:49:22 PM UTC 24 23886473 ps
T559 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.430789192 Sep 09 07:49:17 PM UTC 24 Sep 09 07:49:22 PM UTC 24 429988810 ps
T560 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.1925250684 Sep 09 07:49:18 PM UTC 24 Sep 09 07:49:22 PM UTC 24 181548409 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.1900225617 Sep 09 07:49:16 PM UTC 24 Sep 09 07:49:23 PM UTC 24 122328573 ps
T561 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.3203205698 Sep 09 07:49:21 PM UTC 24 Sep 09 07:49:23 PM UTC 24 44466259 ps
T562 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.806201353 Sep 09 07:49:21 PM UTC 24 Sep 09 07:49:24 PM UTC 24 90452921 ps
T563 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.2641952011 Sep 09 07:49:18 PM UTC 24 Sep 09 07:49:24 PM UTC 24 562456698 ps
T564 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.1249793040 Sep 09 07:49:23 PM UTC 24 Sep 09 07:49:25 PM UTC 24 17222855 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.3785513217 Sep 09 07:49:24 PM UTC 24 Sep 09 07:49:27 PM UTC 24 187757271 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.599424852 Sep 09 07:49:23 PM UTC 24 Sep 09 07:49:27 PM UTC 24 371351512 ps
T565 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.556541020 Sep 09 07:49:23 PM UTC 24 Sep 09 07:49:27 PM UTC 24 49391117 ps
T566 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.49883881 Sep 09 07:49:22 PM UTC 24 Sep 09 07:49:27 PM UTC 24 92865420 ps
T567 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.4088831250 Sep 09 07:49:24 PM UTC 24 Sep 09 07:49:28 PM UTC 24 112956635 ps
T568 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1197096833 Sep 09 07:49:25 PM UTC 24 Sep 09 07:49:29 PM UTC 24 277430764 ps
T569 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.1779413713 Sep 09 07:49:27 PM UTC 24 Sep 09 07:49:29 PM UTC 24 42656120 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.3974341154 Sep 09 07:49:27 PM UTC 24 Sep 09 07:49:30 PM UTC 24 155305853 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.4093865688 Sep 09 07:49:26 PM UTC 24 Sep 09 07:49:30 PM UTC 24 212373499 ps
T570 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.1873247712 Sep 09 07:49:25 PM UTC 24 Sep 09 07:49:31 PM UTC 24 268824470 ps
T571 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3409922866 Sep 09 07:49:29 PM UTC 24 Sep 09 07:49:32 PM UTC 24 48058291 ps
T572 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.1573078998 Sep 09 07:49:08 PM UTC 24 Sep 09 07:49:32 PM UTC 24 15065140841 ps
T573 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1357378163 Sep 09 07:49:28 PM UTC 24 Sep 09 07:49:33 PM UTC 24 86354356 ps
T574 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.3895440283 Sep 09 07:49:31 PM UTC 24 Sep 09 07:49:33 PM UTC 24 36972749 ps
T575 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.1673656330 Sep 09 07:49:31 PM UTC 24 Sep 09 07:49:33 PM UTC 24 23626503 ps
T576 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.585208852 Sep 09 07:49:30 PM UTC 24 Sep 09 07:49:33 PM UTC 24 371469319 ps
T577 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.3468217169 Sep 09 07:49:32 PM UTC 24 Sep 09 07:49:38 PM UTC 24 141546522 ps
T578 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2729017580 Sep 09 07:49:31 PM UTC 24 Sep 09 07:49:34 PM UTC 24 298307195 ps
T579 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.191560216 Sep 09 07:49:33 PM UTC 24 Sep 09 07:49:35 PM UTC 24 16549821 ps
T580 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.2640492659 Sep 09 07:49:30 PM UTC 24 Sep 09 07:49:35 PM UTC 24 322309792 ps
T581 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2292258609 Sep 09 07:49:32 PM UTC 24 Sep 09 07:49:36 PM UTC 24 319737934 ps
T582 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1018114595 Sep 09 07:49:34 PM UTC 24 Sep 09 07:49:37 PM UTC 24 218833940 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.2047032141 Sep 09 07:49:34 PM UTC 24 Sep 09 07:49:38 PM UTC 24 90380692 ps
T583 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.3973188305 Sep 09 07:49:34 PM UTC 24 Sep 09 07:49:38 PM UTC 24 233835550 ps
T584 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.1005792099 Sep 09 07:49:36 PM UTC 24 Sep 09 07:49:38 PM UTC 24 44274262 ps
T585 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.943306106 Sep 09 07:49:37 PM UTC 24 Sep 09 07:49:38 PM UTC 24 36569931 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.485961628 Sep 09 07:49:33 PM UTC 24 Sep 09 07:49:39 PM UTC 24 196195395 ps
T586 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.1825590010 Sep 09 07:49:36 PM UTC 24 Sep 09 07:49:40 PM UTC 24 88367839 ps
T587 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.2073869277 Sep 09 07:49:39 PM UTC 24 Sep 09 07:49:41 PM UTC 24 56197918 ps
T588 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.933048626 Sep 09 07:49:34 PM UTC 24 Sep 09 07:49:41 PM UTC 24 118376388 ps
T589 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1366522393 Sep 09 07:49:38 PM UTC 24 Sep 09 07:49:41 PM UTC 24 164687535 ps
T590 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.3568554701 Sep 09 07:49:39 PM UTC 24 Sep 09 07:49:42 PM UTC 24 217659003 ps
T591 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.935541021 Sep 09 07:49:39 PM UTC 24 Sep 09 07:49:44 PM UTC 24 621724331 ps
T592 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.92566484 Sep 09 07:49:42 PM UTC 24 Sep 09 07:49:45 PM UTC 24 45044785 ps
T593 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.1942784649 Sep 09 07:49:42 PM UTC 24 Sep 09 07:49:45 PM UTC 24 28568320 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.435583918 Sep 09 07:49:39 PM UTC 24 Sep 09 07:49:46 PM UTC 24 551422886 ps
T594 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.2264113873 Sep 09 07:49:44 PM UTC 24 Sep 09 07:49:46 PM UTC 24 14739299 ps
T595 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.1069362179 Sep 09 07:49:45 PM UTC 24 Sep 09 07:49:47 PM UTC 24 46192262 ps
T596 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3994912881 Sep 09 07:49:45 PM UTC 24 Sep 09 07:49:47 PM UTC 24 26171221 ps
T597 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1316153201 Sep 09 07:49:45 PM UTC 24 Sep 09 07:49:47 PM UTC 24 313725101 ps
T598 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.647001019 Sep 09 07:49:44 PM UTC 24 Sep 09 07:49:48 PM UTC 24 93641644 ps
T599 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.856483775 Sep 09 07:49:46 PM UTC 24 Sep 09 07:49:48 PM UTC 24 14525754 ps
T600 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.2990634062 Sep 09 07:49:47 PM UTC 24 Sep 09 07:49:49 PM UTC 24 37344237 ps
T601 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1601088529 Sep 09 07:49:47 PM UTC 24 Sep 09 07:49:50 PM UTC 24 174803445 ps
T602 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.3902773632 Sep 09 07:49:48 PM UTC 24 Sep 09 07:49:50 PM UTC 24 58651202 ps
T603 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.1181770046 Sep 09 07:49:48 PM UTC 24 Sep 09 07:49:50 PM UTC 24 16279441 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.1690477097 Sep 09 07:49:44 PM UTC 24 Sep 09 07:49:51 PM UTC 24 1108275116 ps
T604 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3175372645 Sep 09 07:49:44 PM UTC 24 Sep 09 07:49:51 PM UTC 24 201147998 ps
T605 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.2334408741 Sep 09 07:49:46 PM UTC 24 Sep 09 07:49:52 PM UTC 24 2163536341 ps
T606 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.127320823 Sep 09 07:49:48 PM UTC 24 Sep 09 07:49:52 PM UTC 24 42953826 ps
T607 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2500876884 Sep 09 07:49:47 PM UTC 24 Sep 09 07:49:53 PM UTC 24 48012949 ps
T608 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.3046307819 Sep 09 07:49:46 PM UTC 24 Sep 09 07:49:53 PM UTC 24 770806506 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.1202008968 Sep 09 07:49:48 PM UTC 24 Sep 09 07:49:53 PM UTC 24 85966298 ps
T609 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.3219076699 Sep 09 07:49:52 PM UTC 24 Sep 09 07:49:53 PM UTC 24 14580671 ps
T610 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2612293072 Sep 09 07:49:50 PM UTC 24 Sep 09 07:49:54 PM UTC 24 47011222 ps
T611 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.828826518 Sep 09 07:49:52 PM UTC 24 Sep 09 07:49:54 PM UTC 24 30178574 ps
T612 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.3590803239 Sep 09 07:49:51 PM UTC 24 Sep 09 07:49:56 PM UTC 24 126695204 ps
T613 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.722595727 Sep 09 07:49:54 PM UTC 24 Sep 09 07:49:56 PM UTC 24 20500749 ps
T614 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2567972088 Sep 09 07:49:53 PM UTC 24 Sep 09 07:49:56 PM UTC 24 43242543 ps
T615 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.1615674858 Sep 09 07:49:54 PM UTC 24 Sep 09 07:49:56 PM UTC 24 31354990 ps
T616 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.15794466 Sep 09 07:49:54 PM UTC 24 Sep 09 07:49:57 PM UTC 24 82447350 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.2525500831 Sep 09 07:49:52 PM UTC 24 Sep 09 07:49:57 PM UTC 24 242997955 ps
T617 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.226113954 Sep 09 07:49:53 PM UTC 24 Sep 09 07:49:57 PM UTC 24 448615134 ps
T618 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.2214149732 Sep 09 07:49:54 PM UTC 24 Sep 09 07:49:57 PM UTC 24 79704000 ps
T619 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.567506610 Sep 09 07:49:55 PM UTC 24 Sep 09 07:49:58 PM UTC 24 53361701 ps
T620 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.4104615609 Sep 09 07:49:56 PM UTC 24 Sep 09 07:49:58 PM UTC 24 51104588 ps
T621 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.2110404413 Sep 09 07:49:57 PM UTC 24 Sep 09 07:50:00 PM UTC 24 69382387 ps
T622 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2352682354 Sep 09 07:49:58 PM UTC 24 Sep 09 07:50:00 PM UTC 24 38734051 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.1573843178 Sep 09 07:49:56 PM UTC 24 Sep 09 07:50:00 PM UTC 24 82831477 ps
T623 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.640759741 Sep 09 07:49:59 PM UTC 24 Sep 09 07:50:00 PM UTC 24 59127878 ps
T624 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.189927036 Sep 09 07:49:59 PM UTC 24 Sep 09 07:50:00 PM UTC 24 46928933 ps
T625 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.3659225682 Sep 09 07:49:59 PM UTC 24 Sep 09 07:50:01 PM UTC 24 15485070 ps
T626 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.1287599998 Sep 09 07:49:59 PM UTC 24 Sep 09 07:50:01 PM UTC 24 14900204 ps
T627 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2599458122 Sep 09 07:49:57 PM UTC 24 Sep 09 07:50:01 PM UTC 24 140897636 ps
T628 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.1284669165 Sep 09 07:49:56 PM UTC 24 Sep 09 07:50:02 PM UTC 24 152999163 ps
T629 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.2491877093 Sep 09 07:50:01 PM UTC 24 Sep 09 07:50:03 PM UTC 24 28069603 ps
T630 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.3416532500 Sep 09 07:50:01 PM UTC 24 Sep 09 07:50:03 PM UTC 24 28319173 ps
T631 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.1713467531 Sep 09 07:50:01 PM UTC 24 Sep 09 07:50:03 PM UTC 24 12458719 ps
T632 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.3231264121 Sep 09 07:50:01 PM UTC 24 Sep 09 07:50:03 PM UTC 24 53100628 ps
T633 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.3023718528 Sep 09 07:50:01 PM UTC 24 Sep 09 07:50:03 PM UTC 24 23016573 ps
T634 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.971986404 Sep 09 07:50:01 PM UTC 24 Sep 09 07:50:03 PM UTC 24 25809468 ps
T635 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.2471336260 Sep 09 07:50:02 PM UTC 24 Sep 09 07:50:04 PM UTC 24 12625765 ps
T636 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.2353178579 Sep 09 07:50:02 PM UTC 24 Sep 09 07:50:04 PM UTC 24 34944788 ps
T637 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.1039019823 Sep 09 07:50:02 PM UTC 24 Sep 09 07:50:04 PM UTC 24 29736869 ps
T638 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.2071618770 Sep 09 07:50:03 PM UTC 24 Sep 09 07:50:05 PM UTC 24 18444675 ps
T639 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.1404348738 Sep 09 07:50:04 PM UTC 24 Sep 09 07:50:05 PM UTC 24 43078572 ps
T640 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.2141062930 Sep 09 07:50:03 PM UTC 24 Sep 09 07:50:05 PM UTC 24 120618493 ps
T641 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.2723963097 Sep 09 07:50:04 PM UTC 24 Sep 09 07:50:05 PM UTC 24 19036534 ps
T642 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.2741826587 Sep 09 07:50:04 PM UTC 24 Sep 09 07:50:05 PM UTC 24 23892415 ps
T643 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.3739042697 Sep 09 07:50:04 PM UTC 24 Sep 09 07:50:06 PM UTC 24 40501586 ps
T644 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.1677171518 Sep 09 07:50:05 PM UTC 24 Sep 09 07:50:07 PM UTC 24 29608004 ps
T645 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.810287527 Sep 09 07:50:05 PM UTC 24 Sep 09 07:50:07 PM UTC 24 41047352 ps
T646 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.2709077964 Sep 09 07:50:05 PM UTC 24 Sep 09 07:50:07 PM UTC 24 45386177 ps
T647 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.374325751 Sep 09 07:50:06 PM UTC 24 Sep 09 07:50:08 PM UTC 24 12277783 ps
T648 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.2140569631 Sep 09 07:50:06 PM UTC 24 Sep 09 07:50:08 PM UTC 24 17788477 ps
T649 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.2414128789 Sep 09 07:50:06 PM UTC 24 Sep 09 07:50:08 PM UTC 24 38822990 ps
T650 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.3266068203 Sep 09 07:50:06 PM UTC 24 Sep 09 07:50:08 PM UTC 24 12760807 ps
T651 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.4292202708 Sep 09 07:50:06 PM UTC 24 Sep 09 07:50:08 PM UTC 24 236002374 ps
T652 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.2908436605 Sep 09 07:50:06 PM UTC 24 Sep 09 07:50:08 PM UTC 24 32929134 ps
T653 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.3469001745 Sep 09 07:50:07 PM UTC 24 Sep 09 07:50:09 PM UTC 24 46333906 ps
T654 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.2868209481 Sep 09 07:50:07 PM UTC 24 Sep 09 07:50:09 PM UTC 24 20520978 ps
T655 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.4053494329 Sep 09 07:49:02 PM UTC 24 Sep 09 07:50:51 PM UTC 24 5833302116 ps
T656 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1374733390 Sep 09 07:49:50 PM UTC 24 Sep 09 07:59:49 PM UTC 24 328752073130 ps
T657 /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1166336734 Sep 09 07:49:55 PM UTC 24 Sep 09 08:06:25 PM UTC 24 539504786023 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/2.hmac_smoke.985937891
Short name T7
Test name
Test status
Simulation time 478650475 ps
CPU time 10.17 seconds
Started Sep 09 07:19:49 PM UTC 24
Finished Sep 09 07:20:00 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985937891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.985937891
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/2.hmac_stress_all_with_rand_reset.2787672535
Short name T10
Test name
Test status
Simulation time 8948686776 ps
CPU time 73.59 seconds
Started Sep 09 07:20:06 PM UTC 24
Finished Sep 09 07:21:22 PM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27876725
35 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.2787672535
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/9.hmac_stress_all_with_rand_reset.4115791350
Short name T24
Test name
Test status
Simulation time 4507556215 ps
CPU time 75.54 seconds
Started Sep 09 07:23:09 PM UTC 24
Finished Sep 09 07:24:27 PM UTC 24
Peak memory 216084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41157913
50 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.4115791350
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/3.hmac_burst_wr.1564841927
Short name T54
Test name
Test status
Simulation time 3891923588 ps
CPU time 45.73 seconds
Started Sep 09 07:20:13 PM UTC 24
Finished Sep 09 07:21:00 PM UTC 24
Peak memory 215940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564841927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1564841927
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/1.hmac_burst_wr.3398190323
Short name T31
Test name
Test status
Simulation time 2734557636 ps
CPU time 53.36 seconds
Started Sep 09 07:19:41 PM UTC 24
Finished Sep 09 07:20:36 PM UTC 24
Peak memory 216004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398190323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3398190323
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/1.hmac_stress_all_with_rand_reset.3017175935
Short name T26
Test name
Test status
Simulation time 43897861000 ps
CPU time 229.08 seconds
Started Sep 09 07:19:47 PM UTC 24
Finished Sep 09 07:23:40 PM UTC 24
Peak memory 223908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30171759
35 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3017175935
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_intg_err.380448001
Short name T68
Test name
Test status
Simulation time 164083921 ps
CPU time 2.15 seconds
Started Sep 09 07:48:27 PM UTC 24
Finished Sep 09 07:48:30 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380448001 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.380448001
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/0.hmac_sec_cm.528981224
Short name T3
Test name
Test status
Simulation time 136712551 ps
CPU time 0.75 seconds
Started Sep 09 07:19:38 PM UTC 24
Finished Sep 09 07:19:40 PM UTC 24
Peak memory 235572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528981224 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.528981224
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/5.hmac_wipe_secret.3315829428
Short name T46
Test name
Test status
Simulation time 26174892078 ps
CPU time 69.61 seconds
Started Sep 09 07:21:35 PM UTC 24
Finished Sep 09 07:22:46 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315829428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3315829428
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/5.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/10.hmac_stress_all.1392930255
Short name T159
Test name
Test status
Simulation time 18786038509 ps
CPU time 793.59 seconds
Started Sep 09 07:23:41 PM UTC 24
Finished Sep 09 07:37:03 PM UTC 24
Peak memory 686384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392930255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1392930255
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/10.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.4241507051
Short name T107
Test name
Test status
Simulation time 3209812788 ps
CPU time 17.87 seconds
Started Sep 09 07:48:31 PM UTC 24
Finished Sep 09 07:48:51 PM UTC 24
Peak memory 207724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241507051 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.4241507051
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/1.hmac_error.134717345
Short name T60
Test name
Test status
Simulation time 11647759818 ps
CPU time 55.81 seconds
Started Sep 09 07:19:41 PM UTC 24
Finished Sep 09 07:20:39 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134717345 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.134717345
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/17.hmac_stress_all.266078953
Short name T13
Test name
Test status
Simulation time 20768283920 ps
CPU time 1856.33 seconds
Started Sep 09 07:27:08 PM UTC 24
Finished Sep 09 07:58:25 PM UTC 24
Peak memory 758048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266078953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.266078953
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/17.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/6.hmac_stress_all.2299294686
Short name T223
Test name
Test status
Simulation time 15597142980 ps
CPU time 297.97 seconds
Started Sep 09 07:21:55 PM UTC 24
Finished Sep 09 07:26:57 PM UTC 24
Peak memory 235884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299294686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2299294686
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/6.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.485961628
Short name T137
Test name
Test status
Simulation time 196195395 ps
CPU time 5.2 seconds
Started Sep 09 07:49:33 PM UTC 24
Finished Sep 09 07:49:39 PM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485961628 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.485961628
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/11.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/6.hmac_back_pressure.975073109
Short name T176
Test name
Test status
Simulation time 8800448734 ps
CPU time 110.14 seconds
Started Sep 09 07:21:47 PM UTC 24
Finished Sep 09 07:23:39 PM UTC 24
Peak memory 223696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975073109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.975073109
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/6.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.1690477097
Short name T139
Test name
Test status
Simulation time 1108275116 ps
CPU time 5.21 seconds
Started Sep 09 07:49:44 PM UTC 24
Finished Sep 09 07:49:51 PM UTC 24
Peak memory 207668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690477097 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1690477097
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/14.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/5.hmac_stress_all.3543787698
Short name T84
Test name
Test status
Simulation time 25293982360 ps
CPU time 470.34 seconds
Started Sep 09 07:21:36 PM UTC 24
Finished Sep 09 07:29:32 PM UTC 24
Peak memory 454996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543787698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3543787698
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/5.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/0.hmac_alert_test.2543884497
Short name T1
Test name
Test status
Simulation time 61443366 ps
CPU time 0.55 seconds
Started Sep 09 07:19:38 PM UTC 24
Finished Sep 09 07:19:39 PM UTC 24
Peak memory 204528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543884497 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2543884497
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3231104855
Short name T121
Test name
Test status
Simulation time 45290775 ps
CPU time 2.92 seconds
Started Sep 09 07:48:32 PM UTC 24
Finished Sep 09 07:48:36 PM UTC 24
Peak memory 207660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231104855 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_outstanding.3231104855
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/0.hmac_smoke.2257071939
Short name T5
Test name
Test status
Simulation time 893306615 ps
CPU time 13.03 seconds
Started Sep 09 07:19:35 PM UTC 24
Finished Sep 09 07:19:49 PM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257071939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2257071939
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.1202008968
Short name T72
Test name
Test status
Simulation time 85966298 ps
CPU time 4.06 seconds
Started Sep 09 07:49:48 PM UTC 24
Finished Sep 09 07:49:53 PM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202008968 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1202008968
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/16.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.1573843178
Short name T73
Test name
Test status
Simulation time 82831477 ps
CPU time 2.86 seconds
Started Sep 09 07:49:56 PM UTC 24
Finished Sep 09 07:50:00 PM UTC 24
Peak memory 207732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573843178 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1573843178
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/19.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.1535964474
Short name T536
Test name
Test status
Simulation time 159700591 ps
CPU time 4.22 seconds
Started Sep 09 07:48:32 PM UTC 24
Finished Sep 09 07:48:37 PM UTC 24
Peak memory 207672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535964474 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1535964474
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_hw_reset.3507630540
Short name T534
Test name
Test status
Simulation time 125738459 ps
CPU time 1.54 seconds
Started Sep 09 07:48:28 PM UTC 24
Finished Sep 09 07:48:31 PM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507630540 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3507630540
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2544554543
Short name T76
Test name
Test status
Simulation time 34697689 ps
CPU time 1.53 seconds
Started Sep 09 07:48:34 PM UTC 24
Finished Sep 09 07:48:37 PM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2544554543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_r
eset.2544554543
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_rw.2114443518
Short name T535
Test name
Test status
Simulation time 79065457 ps
CPU time 1.1 seconds
Started Sep 09 07:48:31 PM UTC 24
Finished Sep 09 07:48:34 PM UTC 24
Peak memory 206832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114443518 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2114443518
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_intr_test.733582612
Short name T533
Test name
Test status
Simulation time 19382427 ps
CPU time 0.92 seconds
Started Sep 09 07:48:28 PM UTC 24
Finished Sep 09 07:48:30 PM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733582612 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.733582612
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.2036178977
Short name T75
Test name
Test status
Simulation time 590268645 ps
CPU time 4.84 seconds
Started Sep 09 07:48:18 PM UTC 24
Finished Sep 09 07:48:24 PM UTC 24
Peak memory 208004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036178977 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2036178977
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.4245325917
Short name T542
Test name
Test status
Simulation time 429973773 ps
CPU time 7.11 seconds
Started Sep 09 07:48:41 PM UTC 24
Finished Sep 09 07:48:49 PM UTC 24
Peak memory 207672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245325917 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.4245325917
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.3223456338
Short name T543
Test name
Test status
Simulation time 210164024 ps
CPU time 10.52 seconds
Started Sep 09 07:48:40 PM UTC 24
Finished Sep 09 07:48:51 PM UTC 24
Peak memory 207608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223456338 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3223456338
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.114928523
Short name T538
Test name
Test status
Simulation time 15785844 ps
CPU time 1.14 seconds
Started Sep 09 07:48:37 PM UTC 24
Finished Sep 09 07:48:40 PM UTC 24
Peak memory 206196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114928523 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.114928523
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.439217972
Short name T539
Test name
Test status
Simulation time 52045481 ps
CPU time 1.92 seconds
Started Sep 09 07:48:41 PM UTC 24
Finished Sep 09 07:48:44 PM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=439217972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_re
set.439217972
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.1744459494
Short name T106
Test name
Test status
Simulation time 28987301 ps
CPU time 1.19 seconds
Started Sep 09 07:48:38 PM UTC 24
Finished Sep 09 07:48:40 PM UTC 24
Peak memory 206716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744459494 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1744459494
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.3362665197
Short name T537
Test name
Test status
Simulation time 54625232 ps
CPU time 0.91 seconds
Started Sep 09 07:48:36 PM UTC 24
Finished Sep 09 07:48:38 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362665197 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3362665197
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4255317866
Short name T122
Test name
Test status
Simulation time 137771122 ps
CPU time 3.42 seconds
Started Sep 09 07:48:41 PM UTC 24
Finished Sep 09 07:48:45 PM UTC 24
Peak memory 207660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255317866 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_outstanding.4255317866
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.2688522756
Short name T92
Test name
Test status
Simulation time 158129296 ps
CPU time 5.81 seconds
Started Sep 09 07:48:34 PM UTC 24
Finished Sep 09 07:48:41 PM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688522756 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2688522756
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.135609847
Short name T69
Test name
Test status
Simulation time 325949016 ps
CPU time 2.65 seconds
Started Sep 09 07:48:36 PM UTC 24
Finished Sep 09 07:48:40 PM UTC 24
Peak memory 207740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135609847 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.135609847
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2292258609
Short name T581
Test name
Test status
Simulation time 319737934 ps
CPU time 2.92 seconds
Started Sep 09 07:49:32 PM UTC 24
Finished Sep 09 07:49:36 PM UTC 24
Peak memory 218248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2292258609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_
reset.2292258609
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.1673656330
Short name T575
Test name
Test status
Simulation time 23626503 ps
CPU time 1.14 seconds
Started Sep 09 07:49:31 PM UTC 24
Finished Sep 09 07:49:33 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673656330 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1673656330
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/10.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.3895440283
Short name T574
Test name
Test status
Simulation time 36972749 ps
CPU time 0.9 seconds
Started Sep 09 07:49:31 PM UTC 24
Finished Sep 09 07:49:33 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895440283 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3895440283
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/10.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2729017580
Short name T578
Test name
Test status
Simulation time 298307195 ps
CPU time 1.75 seconds
Started Sep 09 07:49:31 PM UTC 24
Finished Sep 09 07:49:34 PM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729017580 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_outstanding.2729017580
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/10.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.2640492659
Short name T580
Test name
Test status
Simulation time 322309792 ps
CPU time 4.51 seconds
Started Sep 09 07:49:30 PM UTC 24
Finished Sep 09 07:49:35 PM UTC 24
Peak memory 207984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640492659 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2640492659
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/10.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.585208852
Short name T576
Test name
Test status
Simulation time 371469319 ps
CPU time 2.67 seconds
Started Sep 09 07:49:30 PM UTC 24
Finished Sep 09 07:49:33 PM UTC 24
Peak memory 207656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585208852 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.585208852
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/10.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.933048626
Short name T588
Test name
Test status
Simulation time 118376388 ps
CPU time 5.77 seconds
Started Sep 09 07:49:34 PM UTC 24
Finished Sep 09 07:49:41 PM UTC 24
Peak memory 218092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=933048626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_r
eset.933048626
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.2047032141
Short name T120
Test name
Test status
Simulation time 90380692 ps
CPU time 1.31 seconds
Started Sep 09 07:49:34 PM UTC 24
Finished Sep 09 07:49:38 PM UTC 24
Peak memory 206660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047032141 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2047032141
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/11.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.191560216
Short name T579
Test name
Test status
Simulation time 16549821 ps
CPU time 0.91 seconds
Started Sep 09 07:49:33 PM UTC 24
Finished Sep 09 07:49:35 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191560216 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.191560216
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/11.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1018114595
Short name T582
Test name
Test status
Simulation time 218833940 ps
CPU time 1.76 seconds
Started Sep 09 07:49:34 PM UTC 24
Finished Sep 09 07:49:37 PM UTC 24
Peak memory 206788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018114595 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr_outstanding.1018114595
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/11.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.3468217169
Short name T577
Test name
Test status
Simulation time 141546522 ps
CPU time 4.58 seconds
Started Sep 09 07:49:32 PM UTC 24
Finished Sep 09 07:49:38 PM UTC 24
Peak memory 207812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468217169 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3468217169
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/11.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.935541021
Short name T591
Test name
Test status
Simulation time 621724331 ps
CPU time 3.87 seconds
Started Sep 09 07:49:39 PM UTC 24
Finished Sep 09 07:49:44 PM UTC 24
Peak memory 207812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=935541021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_r
eset.935541021
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.943306106
Short name T585
Test name
Test status
Simulation time 36569931 ps
CPU time 0.95 seconds
Started Sep 09 07:49:37 PM UTC 24
Finished Sep 09 07:49:38 PM UTC 24
Peak memory 205656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943306106 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.943306106
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/12.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.1005792099
Short name T584
Test name
Test status
Simulation time 44274262 ps
CPU time 0.84 seconds
Started Sep 09 07:49:36 PM UTC 24
Finished Sep 09 07:49:38 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005792099 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1005792099
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/12.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1366522393
Short name T589
Test name
Test status
Simulation time 164687535 ps
CPU time 2.61 seconds
Started Sep 09 07:49:38 PM UTC 24
Finished Sep 09 07:49:41 PM UTC 24
Peak memory 207636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366522393 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr_outstanding.1366522393
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/12.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.3973188305
Short name T583
Test name
Test status
Simulation time 233835550 ps
CPU time 2.4 seconds
Started Sep 09 07:49:34 PM UTC 24
Finished Sep 09 07:49:38 PM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973188305 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3973188305
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/12.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.1825590010
Short name T586
Test name
Test status
Simulation time 88367839 ps
CPU time 2.48 seconds
Started Sep 09 07:49:36 PM UTC 24
Finished Sep 09 07:49:40 PM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825590010 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1825590010
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/12.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3175372645
Short name T604
Test name
Test status
Simulation time 201147998 ps
CPU time 5.4 seconds
Started Sep 09 07:49:44 PM UTC 24
Finished Sep 09 07:49:51 PM UTC 24
Peak memory 218064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3175372645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_
reset.3175372645
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.1942784649
Short name T593
Test name
Test status
Simulation time 28568320 ps
CPU time 1.46 seconds
Started Sep 09 07:49:42 PM UTC 24
Finished Sep 09 07:49:45 PM UTC 24
Peak memory 206892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942784649 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1942784649
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/13.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.2073869277
Short name T587
Test name
Test status
Simulation time 56197918 ps
CPU time 0.82 seconds
Started Sep 09 07:49:39 PM UTC 24
Finished Sep 09 07:49:41 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073869277 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2073869277
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/13.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.92566484
Short name T592
Test name
Test status
Simulation time 45044785 ps
CPU time 1.42 seconds
Started Sep 09 07:49:42 PM UTC 24
Finished Sep 09 07:49:45 PM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92566484 -assert nopostproc +UVM_
TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_outstanding.92566484
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/13.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.3568554701
Short name T590
Test name
Test status
Simulation time 217659003 ps
CPU time 2.53 seconds
Started Sep 09 07:49:39 PM UTC 24
Finished Sep 09 07:49:42 PM UTC 24
Peak memory 207792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568554701 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3568554701
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/13.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.435583918
Short name T134
Test name
Test status
Simulation time 551422886 ps
CPU time 6.03 seconds
Started Sep 09 07:49:39 PM UTC 24
Finished Sep 09 07:49:46 PM UTC 24
Peak memory 207792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435583918 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.435583918
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/13.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3994912881
Short name T596
Test name
Test status
Simulation time 26171221 ps
CPU time 1.5 seconds
Started Sep 09 07:49:45 PM UTC 24
Finished Sep 09 07:49:47 PM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3994912881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_
reset.3994912881
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.1069362179
Short name T595
Test name
Test status
Simulation time 46192262 ps
CPU time 1.07 seconds
Started Sep 09 07:49:45 PM UTC 24
Finished Sep 09 07:49:47 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069362179 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1069362179
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/14.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.2264113873
Short name T594
Test name
Test status
Simulation time 14739299 ps
CPU time 0.95 seconds
Started Sep 09 07:49:44 PM UTC 24
Finished Sep 09 07:49:46 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264113873 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2264113873
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/14.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1316153201
Short name T597
Test name
Test status
Simulation time 313725101 ps
CPU time 1.66 seconds
Started Sep 09 07:49:45 PM UTC 24
Finished Sep 09 07:49:47 PM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316153201 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr_outstanding.1316153201
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/14.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.647001019
Short name T598
Test name
Test status
Simulation time 93641644 ps
CPU time 2.39 seconds
Started Sep 09 07:49:44 PM UTC 24
Finished Sep 09 07:49:48 PM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647001019 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.647001019
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/14.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2500876884
Short name T607
Test name
Test status
Simulation time 48012949 ps
CPU time 4.72 seconds
Started Sep 09 07:49:47 PM UTC 24
Finished Sep 09 07:49:53 PM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2500876884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_
reset.2500876884
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.2990634062
Short name T600
Test name
Test status
Simulation time 37344237 ps
CPU time 1.36 seconds
Started Sep 09 07:49:47 PM UTC 24
Finished Sep 09 07:49:49 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990634062 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2990634062
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/15.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.856483775
Short name T599
Test name
Test status
Simulation time 14525754 ps
CPU time 0.93 seconds
Started Sep 09 07:49:46 PM UTC 24
Finished Sep 09 07:49:48 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856483775 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.856483775
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/15.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1601088529
Short name T601
Test name
Test status
Simulation time 174803445 ps
CPU time 1.69 seconds
Started Sep 09 07:49:47 PM UTC 24
Finished Sep 09 07:49:50 PM UTC 24
Peak memory 206856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601088529 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr_outstanding.1601088529
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/15.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.3046307819
Short name T608
Test name
Test status
Simulation time 770806506 ps
CPU time 6.06 seconds
Started Sep 09 07:49:46 PM UTC 24
Finished Sep 09 07:49:53 PM UTC 24
Peak memory 207812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046307819 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3046307819
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/15.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.2334408741
Short name T605
Test name
Test status
Simulation time 2163536341 ps
CPU time 4.88 seconds
Started Sep 09 07:49:46 PM UTC 24
Finished Sep 09 07:49:52 PM UTC 24
Peak memory 207792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334408741 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2334408741
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/15.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1374733390
Short name T656
Test name
Test status
Simulation time 328752073130 ps
CPU time 589.99 seconds
Started Sep 09 07:49:50 PM UTC 24
Finished Sep 09 07:59:49 PM UTC 24
Peak memory 224216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1374733390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_
reset.1374733390
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.3902773632
Short name T602
Test name
Test status
Simulation time 58651202 ps
CPU time 0.88 seconds
Started Sep 09 07:49:48 PM UTC 24
Finished Sep 09 07:49:50 PM UTC 24
Peak memory 205920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902773632 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3902773632
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/16.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.1181770046
Short name T603
Test name
Test status
Simulation time 16279441 ps
CPU time 0.93 seconds
Started Sep 09 07:49:48 PM UTC 24
Finished Sep 09 07:49:50 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181770046 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1181770046
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/16.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2612293072
Short name T610
Test name
Test status
Simulation time 47011222 ps
CPU time 2.35 seconds
Started Sep 09 07:49:50 PM UTC 24
Finished Sep 09 07:49:54 PM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612293072 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr_outstanding.2612293072
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/16.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.127320823
Short name T606
Test name
Test status
Simulation time 42953826 ps
CPU time 2.59 seconds
Started Sep 09 07:49:48 PM UTC 24
Finished Sep 09 07:49:52 PM UTC 24
Peak memory 207988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127320823 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.127320823
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/16.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2567972088
Short name T614
Test name
Test status
Simulation time 43242543 ps
CPU time 2.19 seconds
Started Sep 09 07:49:53 PM UTC 24
Finished Sep 09 07:49:56 PM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2567972088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_
reset.2567972088
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.828826518
Short name T611
Test name
Test status
Simulation time 30178574 ps
CPU time 1.54 seconds
Started Sep 09 07:49:52 PM UTC 24
Finished Sep 09 07:49:54 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828826518 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.828826518
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/17.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.3219076699
Short name T609
Test name
Test status
Simulation time 14580671 ps
CPU time 0.8 seconds
Started Sep 09 07:49:52 PM UTC 24
Finished Sep 09 07:49:53 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219076699 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3219076699
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/17.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.226113954
Short name T617
Test name
Test status
Simulation time 448615134 ps
CPU time 3.45 seconds
Started Sep 09 07:49:53 PM UTC 24
Finished Sep 09 07:49:57 PM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226113954 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr_outstanding.226113954
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/17.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.3590803239
Short name T612
Test name
Test status
Simulation time 126695204 ps
CPU time 3.12 seconds
Started Sep 09 07:49:51 PM UTC 24
Finished Sep 09 07:49:56 PM UTC 24
Peak memory 208132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590803239 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3590803239
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/17.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.2525500831
Short name T140
Test name
Test status
Simulation time 242997955 ps
CPU time 4.43 seconds
Started Sep 09 07:49:52 PM UTC 24
Finished Sep 09 07:49:57 PM UTC 24
Peak memory 208060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525500831 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2525500831
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/17.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1166336734
Short name T657
Test name
Test status
Simulation time 539504786023 ps
CPU time 978.04 seconds
Started Sep 09 07:49:55 PM UTC 24
Finished Sep 09 08:06:25 PM UTC 24
Peak memory 224224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1166336734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_
reset.1166336734
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.1615674858
Short name T615
Test name
Test status
Simulation time 31354990 ps
CPU time 1.26 seconds
Started Sep 09 07:49:54 PM UTC 24
Finished Sep 09 07:49:56 PM UTC 24
Peak memory 206712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615674858 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1615674858
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/18.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.722595727
Short name T613
Test name
Test status
Simulation time 20500749 ps
CPU time 0.88 seconds
Started Sep 09 07:49:54 PM UTC 24
Finished Sep 09 07:49:56 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722595727 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.722595727
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/18.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.567506610
Short name T619
Test name
Test status
Simulation time 53361701 ps
CPU time 1.64 seconds
Started Sep 09 07:49:55 PM UTC 24
Finished Sep 09 07:49:58 PM UTC 24
Peak memory 206780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567506610 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr_outstanding.567506610
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/18.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.2214149732
Short name T618
Test name
Test status
Simulation time 79704000 ps
CPU time 2.43 seconds
Started Sep 09 07:49:54 PM UTC 24
Finished Sep 09 07:49:57 PM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214149732 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2214149732
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/18.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.15794466
Short name T616
Test name
Test status
Simulation time 82447350 ps
CPU time 2.06 seconds
Started Sep 09 07:49:54 PM UTC 24
Finished Sep 09 07:49:57 PM UTC 24
Peak memory 207732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15794466 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.15794466
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/18.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2352682354
Short name T622
Test name
Test status
Simulation time 38734051 ps
CPU time 1.38 seconds
Started Sep 09 07:49:58 PM UTC 24
Finished Sep 09 07:50:00 PM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2352682354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_
reset.2352682354
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.2110404413
Short name T621
Test name
Test status
Simulation time 69382387 ps
CPU time 1.42 seconds
Started Sep 09 07:49:57 PM UTC 24
Finished Sep 09 07:50:00 PM UTC 24
Peak memory 206772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110404413 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2110404413
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/19.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.4104615609
Short name T620
Test name
Test status
Simulation time 51104588 ps
CPU time 0.88 seconds
Started Sep 09 07:49:56 PM UTC 24
Finished Sep 09 07:49:58 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104615609 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.4104615609
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/19.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2599458122
Short name T627
Test name
Test status
Simulation time 140897636 ps
CPU time 2.48 seconds
Started Sep 09 07:49:57 PM UTC 24
Finished Sep 09 07:50:01 PM UTC 24
Peak memory 207804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599458122 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_outstanding.2599458122
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/19.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.1284669165
Short name T628
Test name
Test status
Simulation time 152999163 ps
CPU time 4.5 seconds
Started Sep 09 07:49:56 PM UTC 24
Finished Sep 09 07:50:02 PM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284669165 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1284669165
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/19.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.2767863602
Short name T110
Test name
Test status
Simulation time 1853260870 ps
CPU time 9.62 seconds
Started Sep 09 07:48:51 PM UTC 24
Finished Sep 09 07:49:02 PM UTC 24
Peak memory 207940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767863602 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2767863602
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.2162830295
Short name T549
Test name
Test status
Simulation time 6093373859 ps
CPU time 15.8 seconds
Started Sep 09 07:48:50 PM UTC 24
Finished Sep 09 07:49:07 PM UTC 24
Peak memory 207744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162830295 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2162830295
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.2414006875
Short name T108
Test name
Test status
Simulation time 21632001 ps
CPU time 1.11 seconds
Started Sep 09 07:48:49 PM UTC 24
Finished Sep 09 07:48:51 PM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414006875 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2414006875
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1712996847
Short name T545
Test name
Test status
Simulation time 107777443 ps
CPU time 3.52 seconds
Started Sep 09 07:48:52 PM UTC 24
Finished Sep 09 07:48:57 PM UTC 24
Peak memory 217988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1712996847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_r
eset.1712996847
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.1034533623
Short name T123
Test name
Test status
Simulation time 30852099 ps
CPU time 1.38 seconds
Started Sep 09 07:48:50 PM UTC 24
Finished Sep 09 07:48:53 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034533623 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1034533623
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.3524850158
Short name T540
Test name
Test status
Simulation time 56220140 ps
CPU time 0.95 seconds
Started Sep 09 07:48:46 PM UTC 24
Finished Sep 09 07:48:48 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524850158 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3524850158
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1766773954
Short name T124
Test name
Test status
Simulation time 23154426 ps
CPU time 1.65 seconds
Started Sep 09 07:48:52 PM UTC 24
Finished Sep 09 07:48:55 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766773954 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_outstanding.1766773954
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.1015546501
Short name T541
Test name
Test status
Simulation time 317448805 ps
CPU time 5.68 seconds
Started Sep 09 07:48:42 PM UTC 24
Finished Sep 09 07:48:49 PM UTC 24
Peak memory 208060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015546501 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1015546501
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.1883003544
Short name T70
Test name
Test status
Simulation time 372980922 ps
CPU time 5.07 seconds
Started Sep 09 07:48:45 PM UTC 24
Finished Sep 09 07:48:51 PM UTC 24
Peak memory 208012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883003544 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1883003544
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.189927036
Short name T624
Test name
Test status
Simulation time 46928933 ps
CPU time 0.9 seconds
Started Sep 09 07:49:59 PM UTC 24
Finished Sep 09 07:50:00 PM UTC 24
Peak memory 203380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189927036 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.189927036
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/20.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.640759741
Short name T623
Test name
Test status
Simulation time 59127878 ps
CPU time 0.84 seconds
Started Sep 09 07:49:59 PM UTC 24
Finished Sep 09 07:50:00 PM UTC 24
Peak memory 203448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640759741 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.640759741
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/21.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.3659225682
Short name T625
Test name
Test status
Simulation time 15485070 ps
CPU time 0.93 seconds
Started Sep 09 07:49:59 PM UTC 24
Finished Sep 09 07:50:01 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659225682 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3659225682
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/22.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.1287599998
Short name T626
Test name
Test status
Simulation time 14900204 ps
CPU time 0.98 seconds
Started Sep 09 07:49:59 PM UTC 24
Finished Sep 09 07:50:01 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287599998 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1287599998
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/23.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.2491877093
Short name T629
Test name
Test status
Simulation time 28069603 ps
CPU time 0.88 seconds
Started Sep 09 07:50:01 PM UTC 24
Finished Sep 09 07:50:03 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491877093 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2491877093
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/24.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.3416532500
Short name T630
Test name
Test status
Simulation time 28319173 ps
CPU time 0.87 seconds
Started Sep 09 07:50:01 PM UTC 24
Finished Sep 09 07:50:03 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416532500 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3416532500
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/25.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.1713467531
Short name T631
Test name
Test status
Simulation time 12458719 ps
CPU time 0.85 seconds
Started Sep 09 07:50:01 PM UTC 24
Finished Sep 09 07:50:03 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713467531 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1713467531
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/26.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.3231264121
Short name T632
Test name
Test status
Simulation time 53100628 ps
CPU time 0.94 seconds
Started Sep 09 07:50:01 PM UTC 24
Finished Sep 09 07:50:03 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231264121 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3231264121
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/27.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.3023718528
Short name T633
Test name
Test status
Simulation time 23016573 ps
CPU time 0.85 seconds
Started Sep 09 07:50:01 PM UTC 24
Finished Sep 09 07:50:03 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023718528 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3023718528
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/28.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.971986404
Short name T634
Test name
Test status
Simulation time 25809468 ps
CPU time 0.93 seconds
Started Sep 09 07:50:01 PM UTC 24
Finished Sep 09 07:50:03 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971986404 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.971986404
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/29.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.2213245695
Short name T547
Test name
Test status
Simulation time 633800936 ps
CPU time 4.3 seconds
Started Sep 09 07:49:01 PM UTC 24
Finished Sep 09 07:49:07 PM UTC 24
Peak memory 207600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213245695 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2213245695
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.2121764858
Short name T117
Test name
Test status
Simulation time 2227957555 ps
CPU time 17.77 seconds
Started Sep 09 07:49:01 PM UTC 24
Finished Sep 09 07:49:21 PM UTC 24
Peak memory 207724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121764858 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2121764858
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.1861225481
Short name T109
Test name
Test status
Simulation time 20792859 ps
CPU time 1.36 seconds
Started Sep 09 07:48:56 PM UTC 24
Finished Sep 09 07:48:59 PM UTC 24
Peak memory 206724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861225481 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1861225481
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.4053494329
Short name T655
Test name
Test status
Simulation time 5833302116 ps
CPU time 106.48 seconds
Started Sep 09 07:49:02 PM UTC 24
Finished Sep 09 07:50:51 PM UTC 24
Peak memory 218176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4053494329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_r
eset.4053494329
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.3496488976
Short name T111
Test name
Test status
Simulation time 36604681 ps
CPU time 1.52 seconds
Started Sep 09 07:49:01 PM UTC 24
Finished Sep 09 07:49:04 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496488976 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3496488976
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.3703752117
Short name T546
Test name
Test status
Simulation time 19826990 ps
CPU time 0.94 seconds
Started Sep 09 07:48:56 PM UTC 24
Finished Sep 09 07:48:58 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703752117 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3703752117
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2686112069
Short name T125
Test name
Test status
Simulation time 418860454 ps
CPU time 3.27 seconds
Started Sep 09 07:49:02 PM UTC 24
Finished Sep 09 07:49:07 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686112069 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_outstanding.2686112069
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.3334700349
Short name T544
Test name
Test status
Simulation time 974714783 ps
CPU time 2.75 seconds
Started Sep 09 07:48:53 PM UTC 24
Finished Sep 09 07:48:56 PM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334700349 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3334700349
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.3348268628
Short name T138
Test name
Test status
Simulation time 82360379 ps
CPU time 2.75 seconds
Started Sep 09 07:48:54 PM UTC 24
Finished Sep 09 07:48:57 PM UTC 24
Peak memory 207876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348268628 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.3348268628
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.2471336260
Short name T635
Test name
Test status
Simulation time 12625765 ps
CPU time 0.85 seconds
Started Sep 09 07:50:02 PM UTC 24
Finished Sep 09 07:50:04 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471336260 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2471336260
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/30.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.2353178579
Short name T636
Test name
Test status
Simulation time 34944788 ps
CPU time 0.83 seconds
Started Sep 09 07:50:02 PM UTC 24
Finished Sep 09 07:50:04 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353178579 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2353178579
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/31.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.1039019823
Short name T637
Test name
Test status
Simulation time 29736869 ps
CPU time 0.81 seconds
Started Sep 09 07:50:02 PM UTC 24
Finished Sep 09 07:50:04 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039019823 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1039019823
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/32.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.2141062930
Short name T640
Test name
Test status
Simulation time 120618493 ps
CPU time 0.97 seconds
Started Sep 09 07:50:03 PM UTC 24
Finished Sep 09 07:50:05 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141062930 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2141062930
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/33.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.2071618770
Short name T638
Test name
Test status
Simulation time 18444675 ps
CPU time 0.8 seconds
Started Sep 09 07:50:03 PM UTC 24
Finished Sep 09 07:50:05 PM UTC 24
Peak memory 203416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071618770 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2071618770
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/34.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.1404348738
Short name T639
Test name
Test status
Simulation time 43078572 ps
CPU time 0.86 seconds
Started Sep 09 07:50:04 PM UTC 24
Finished Sep 09 07:50:05 PM UTC 24
Peak memory 203432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404348738 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1404348738
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/35.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.2741826587
Short name T642
Test name
Test status
Simulation time 23892415 ps
CPU time 0.92 seconds
Started Sep 09 07:50:04 PM UTC 24
Finished Sep 09 07:50:05 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741826587 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2741826587
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/36.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.2723963097
Short name T641
Test name
Test status
Simulation time 19036534 ps
CPU time 0.84 seconds
Started Sep 09 07:50:04 PM UTC 24
Finished Sep 09 07:50:05 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723963097 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2723963097
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/37.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.3739042697
Short name T643
Test name
Test status
Simulation time 40501586 ps
CPU time 0.8 seconds
Started Sep 09 07:50:04 PM UTC 24
Finished Sep 09 07:50:06 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739042697 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3739042697
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/38.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.810287527
Short name T645
Test name
Test status
Simulation time 41047352 ps
CPU time 0.86 seconds
Started Sep 09 07:50:05 PM UTC 24
Finished Sep 09 07:50:07 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810287527 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.810287527
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/39.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.2193148407
Short name T114
Test name
Test status
Simulation time 743612776 ps
CPU time 4.5 seconds
Started Sep 09 07:49:08 PM UTC 24
Finished Sep 09 07:49:14 PM UTC 24
Peak memory 207608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193148407 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2193148407
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.1573078998
Short name T572
Test name
Test status
Simulation time 15065140841 ps
CPU time 22.34 seconds
Started Sep 09 07:49:08 PM UTC 24
Finished Sep 09 07:49:32 PM UTC 24
Peak memory 208056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573078998 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1573078998
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.1094097161
Short name T112
Test name
Test status
Simulation time 61760723 ps
CPU time 1.2 seconds
Started Sep 09 07:49:08 PM UTC 24
Finished Sep 09 07:49:10 PM UTC 24
Peak memory 206716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094097161 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1094097161
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.784285467
Short name T551
Test name
Test status
Simulation time 353151893 ps
CPU time 3.29 seconds
Started Sep 09 07:49:10 PM UTC 24
Finished Sep 09 07:49:15 PM UTC 24
Peak memory 207800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=784285467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_re
set.784285467
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.218465369
Short name T113
Test name
Test status
Simulation time 77111974 ps
CPU time 1.38 seconds
Started Sep 09 07:49:08 PM UTC 24
Finished Sep 09 07:49:10 PM UTC 24
Peak memory 206536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218465369 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.218465369
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.3014439012
Short name T550
Test name
Test status
Simulation time 13587167 ps
CPU time 0.85 seconds
Started Sep 09 07:49:05 PM UTC 24
Finished Sep 09 07:49:07 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014439012 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3014439012
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.316060246
Short name T126
Test name
Test status
Simulation time 117172624 ps
CPU time 2.24 seconds
Started Sep 09 07:49:08 PM UTC 24
Finished Sep 09 07:49:12 PM UTC 24
Peak memory 207804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316060246 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_outstanding.316060246
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.3776745800
Short name T548
Test name
Test status
Simulation time 218242459 ps
CPU time 3.59 seconds
Started Sep 09 07:49:02 PM UTC 24
Finished Sep 09 07:49:07 PM UTC 24
Peak memory 207724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776745800 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3776745800
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.2160525558
Short name T135
Test name
Test status
Simulation time 363514046 ps
CPU time 4.2 seconds
Started Sep 09 07:49:04 PM UTC 24
Finished Sep 09 07:49:09 PM UTC 24
Peak memory 207928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160525558 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2160525558
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.1677171518
Short name T644
Test name
Test status
Simulation time 29608004 ps
CPU time 0.82 seconds
Started Sep 09 07:50:05 PM UTC 24
Finished Sep 09 07:50:07 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677171518 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1677171518
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/40.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.2709077964
Short name T646
Test name
Test status
Simulation time 45386177 ps
CPU time 0.85 seconds
Started Sep 09 07:50:05 PM UTC 24
Finished Sep 09 07:50:07 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709077964 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2709077964
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/41.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.374325751
Short name T647
Test name
Test status
Simulation time 12277783 ps
CPU time 0.86 seconds
Started Sep 09 07:50:06 PM UTC 24
Finished Sep 09 07:50:08 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374325751 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.374325751
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/42.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.2140569631
Short name T648
Test name
Test status
Simulation time 17788477 ps
CPU time 0.99 seconds
Started Sep 09 07:50:06 PM UTC 24
Finished Sep 09 07:50:08 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140569631 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2140569631
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/43.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.4292202708
Short name T651
Test name
Test status
Simulation time 236002374 ps
CPU time 0.93 seconds
Started Sep 09 07:50:06 PM UTC 24
Finished Sep 09 07:50:08 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292202708 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.4292202708
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/44.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.2908436605
Short name T652
Test name
Test status
Simulation time 32929134 ps
CPU time 0.93 seconds
Started Sep 09 07:50:06 PM UTC 24
Finished Sep 09 07:50:08 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908436605 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2908436605
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/45.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.3266068203
Short name T650
Test name
Test status
Simulation time 12760807 ps
CPU time 0.81 seconds
Started Sep 09 07:50:06 PM UTC 24
Finished Sep 09 07:50:08 PM UTC 24
Peak memory 203552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266068203 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3266068203
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/46.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.2414128789
Short name T649
Test name
Test status
Simulation time 38822990 ps
CPU time 0.84 seconds
Started Sep 09 07:50:06 PM UTC 24
Finished Sep 09 07:50:08 PM UTC 24
Peak memory 203564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414128789 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2414128789
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/47.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.2868209481
Short name T654
Test name
Test status
Simulation time 20520978 ps
CPU time 0.99 seconds
Started Sep 09 07:50:07 PM UTC 24
Finished Sep 09 07:50:09 PM UTC 24
Peak memory 203324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868209481 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2868209481
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/48.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.3469001745
Short name T653
Test name
Test status
Simulation time 46333906 ps
CPU time 0.83 seconds
Started Sep 09 07:50:07 PM UTC 24
Finished Sep 09 07:50:09 PM UTC 24
Peak memory 203412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469001745 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3469001745
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/49.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4008694697
Short name T555
Test name
Test status
Simulation time 25480793 ps
CPU time 1.45 seconds
Started Sep 09 07:49:15 PM UTC 24
Finished Sep 09 07:49:18 PM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4008694697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_r
eset.4008694697
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.101754751
Short name T115
Test name
Test status
Simulation time 26582963 ps
CPU time 1.2 seconds
Started Sep 09 07:49:14 PM UTC 24
Finished Sep 09 07:49:16 PM UTC 24
Peak memory 206536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101754751 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.101754751
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/5.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.151056560
Short name T553
Test name
Test status
Simulation time 43084885 ps
CPU time 0.88 seconds
Started Sep 09 07:49:14 PM UTC 24
Finished Sep 09 07:49:16 PM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151056560 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.151056560
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/5.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3192344038
Short name T127
Test name
Test status
Simulation time 219725942 ps
CPU time 1.82 seconds
Started Sep 09 07:49:14 PM UTC 24
Finished Sep 09 07:49:17 PM UTC 24
Peak memory 206784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192344038 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_outstanding.3192344038
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/5.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.3137019902
Short name T554
Test name
Test status
Simulation time 84127870 ps
CPU time 4.26 seconds
Started Sep 09 07:49:11 PM UTC 24
Finished Sep 09 07:49:17 PM UTC 24
Peak memory 208068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137019902 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3137019902
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/5.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.2265266564
Short name T552
Test name
Test status
Simulation time 194796413 ps
CPU time 2.74 seconds
Started Sep 09 07:49:11 PM UTC 24
Finished Sep 09 07:49:15 PM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265266564 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2265266564
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/5.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.430789192
Short name T559
Test name
Test status
Simulation time 429988810 ps
CPU time 3.57 seconds
Started Sep 09 07:49:17 PM UTC 24
Finished Sep 09 07:49:22 PM UTC 24
Peak memory 217968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=430789192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_re
set.430789192
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.1776749876
Short name T116
Test name
Test status
Simulation time 16668394 ps
CPU time 1.35 seconds
Started Sep 09 07:49:17 PM UTC 24
Finished Sep 09 07:49:20 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776749876 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1776749876
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/6.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.1262695017
Short name T557
Test name
Test status
Simulation time 17846933 ps
CPU time 0.93 seconds
Started Sep 09 07:49:16 PM UTC 24
Finished Sep 09 07:49:18 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262695017 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1262695017
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/6.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1219119795
Short name T128
Test name
Test status
Simulation time 118379263 ps
CPU time 1.72 seconds
Started Sep 09 07:49:17 PM UTC 24
Finished Sep 09 07:49:20 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219119795 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_outstanding.1219119795
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/6.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.483573243
Short name T556
Test name
Test status
Simulation time 96266489 ps
CPU time 1.86 seconds
Started Sep 09 07:49:15 PM UTC 24
Finished Sep 09 07:49:18 PM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483573243 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.483573243
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/6.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.1900225617
Short name T136
Test name
Test status
Simulation time 122328573 ps
CPU time 5.74 seconds
Started Sep 09 07:49:16 PM UTC 24
Finished Sep 09 07:49:23 PM UTC 24
Peak memory 207940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900225617 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1900225617
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/6.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.49883881
Short name T566
Test name
Test status
Simulation time 92865420 ps
CPU time 4.29 seconds
Started Sep 09 07:49:22 PM UTC 24
Finished Sep 09 07:49:27 PM UTC 24
Peak memory 218044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=49883881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.49883881
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.3203205698
Short name T561
Test name
Test status
Simulation time 44466259 ps
CPU time 1.08 seconds
Started Sep 09 07:49:21 PM UTC 24
Finished Sep 09 07:49:23 PM UTC 24
Peak memory 205980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203205698 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3203205698
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/7.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.1528501139
Short name T558
Test name
Test status
Simulation time 23886473 ps
CPU time 0.89 seconds
Started Sep 09 07:49:20 PM UTC 24
Finished Sep 09 07:49:22 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528501139 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1528501139
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/7.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.806201353
Short name T562
Test name
Test status
Simulation time 90452921 ps
CPU time 1.69 seconds
Started Sep 09 07:49:21 PM UTC 24
Finished Sep 09 07:49:24 PM UTC 24
Peak memory 206784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806201353 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_outstanding.806201353
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/7.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.2641952011
Short name T563
Test name
Test status
Simulation time 562456698 ps
CPU time 4.23 seconds
Started Sep 09 07:49:18 PM UTC 24
Finished Sep 09 07:49:24 PM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641952011 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2641952011
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/7.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.1925250684
Short name T560
Test name
Test status
Simulation time 181548409 ps
CPU time 2.42 seconds
Started Sep 09 07:49:18 PM UTC 24
Finished Sep 09 07:49:22 PM UTC 24
Peak memory 207928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925250684 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1925250684
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/7.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1197096833
Short name T568
Test name
Test status
Simulation time 277430764 ps
CPU time 2.86 seconds
Started Sep 09 07:49:25 PM UTC 24
Finished Sep 09 07:49:29 PM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1197096833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_r
eset.1197096833
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.3785513217
Short name T118
Test name
Test status
Simulation time 187757271 ps
CPU time 1.26 seconds
Started Sep 09 07:49:24 PM UTC 24
Finished Sep 09 07:49:27 PM UTC 24
Peak memory 206576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785513217 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3785513217
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/8.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.1249793040
Short name T564
Test name
Test status
Simulation time 17222855 ps
CPU time 0.91 seconds
Started Sep 09 07:49:23 PM UTC 24
Finished Sep 09 07:49:25 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249793040 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1249793040
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/8.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.4088831250
Short name T567
Test name
Test status
Simulation time 112956635 ps
CPU time 3.06 seconds
Started Sep 09 07:49:24 PM UTC 24
Finished Sep 09 07:49:28 PM UTC 24
Peak memory 207816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088831250 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_outstanding.4088831250
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/8.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.556541020
Short name T565
Test name
Test status
Simulation time 49391117 ps
CPU time 2.92 seconds
Started Sep 09 07:49:23 PM UTC 24
Finished Sep 09 07:49:27 PM UTC 24
Peak memory 208060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556541020 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.556541020
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/8.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.599424852
Short name T133
Test name
Test status
Simulation time 371351512 ps
CPU time 2.51 seconds
Started Sep 09 07:49:23 PM UTC 24
Finished Sep 09 07:49:27 PM UTC 24
Peak memory 207732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599424852 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.599424852
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/8.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3409922866
Short name T571
Test name
Test status
Simulation time 48058291 ps
CPU time 1.83 seconds
Started Sep 09 07:49:29 PM UTC 24
Finished Sep 09 07:49:32 PM UTC 24
Peak memory 206360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3409922866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_r
eset.3409922866
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.3974341154
Short name T119
Test name
Test status
Simulation time 155305853 ps
CPU time 1.31 seconds
Started Sep 09 07:49:27 PM UTC 24
Finished Sep 09 07:49:30 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974341154 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3974341154
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/9.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.1779413713
Short name T569
Test name
Test status
Simulation time 42656120 ps
CPU time 0.87 seconds
Started Sep 09 07:49:27 PM UTC 24
Finished Sep 09 07:49:29 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779413713 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1779413713
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/9.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1357378163
Short name T573
Test name
Test status
Simulation time 86354356 ps
CPU time 2.8 seconds
Started Sep 09 07:49:28 PM UTC 24
Finished Sep 09 07:49:33 PM UTC 24
Peak memory 207556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357378163 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_outstanding.1357378163
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/9.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.1873247712
Short name T570
Test name
Test status
Simulation time 268824470 ps
CPU time 4.45 seconds
Started Sep 09 07:49:25 PM UTC 24
Finished Sep 09 07:49:31 PM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873247712 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1873247712
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/9.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.4093865688
Short name T141
Test name
Test status
Simulation time 212373499 ps
CPU time 2.48 seconds
Started Sep 09 07:49:26 PM UTC 24
Finished Sep 09 07:49:30 PM UTC 24
Peak memory 207684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093865688 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.4093865688
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/9.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/0.hmac_back_pressure.788460970
Short name T16
Test name
Test status
Simulation time 1030473521 ps
CPU time 52.37 seconds
Started Sep 09 07:19:35 PM UTC 24
Finished Sep 09 07:20:29 PM UTC 24
Peak memory 207380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788460970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.788460970
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/0.hmac_burst_wr.2215914571
Short name T4
Test name
Test status
Simulation time 2651584271 ps
CPU time 8.61 seconds
Started Sep 09 07:19:35 PM UTC 24
Finished Sep 09 07:19:45 PM UTC 24
Peak memory 207272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215914571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2215914571
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/0.hmac_datapath_stress.3024340898
Short name T143
Test name
Test status
Simulation time 14118216985 ps
CPU time 393.17 seconds
Started Sep 09 07:19:35 PM UTC 24
Finished Sep 09 07:26:13 PM UTC 24
Peak memory 651804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024340898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3024340898
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/0.hmac_error.527290632
Short name T2
Test name
Test status
Simulation time 268087113 ps
CPU time 3.22 seconds
Started Sep 09 07:19:35 PM UTC 24
Finished Sep 09 07:19:39 PM UTC 24
Peak memory 207060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527290632 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.527290632
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/0.hmac_long_msg.1053095172
Short name T95
Test name
Test status
Simulation time 15316678117 ps
CPU time 203.88 seconds
Started Sep 09 07:19:35 PM UTC 24
Finished Sep 09 07:23:02 PM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053095172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1053095172
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/0.hmac_stress_all.1806107050
Short name T71
Test name
Test status
Simulation time 11378807983 ps
CPU time 212.76 seconds
Started Sep 09 07:19:37 PM UTC 24
Finished Sep 09 07:23:13 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806107050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1806107050
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/0.hmac_test_hmac256_vectors.1785077278
Short name T30
Test name
Test status
Simulation time 2166354086 ps
CPU time 35.14 seconds
Started Sep 09 07:19:36 PM UTC 24
Finished Sep 09 07:20:13 PM UTC 24
Peak memory 207344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785077278 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.1785077278
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/0.hmac_test_hmac384_vectors.572509434
Short name T57
Test name
Test status
Simulation time 7459714675 ps
CPU time 89.04 seconds
Started Sep 09 07:19:36 PM UTC 24
Finished Sep 09 07:21:08 PM UTC 24
Peak memory 207276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572509434 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.572509434
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/0.hmac_test_hmac512_vectors.3176958590
Short name T162
Test name
Test status
Simulation time 4298414161 ps
CPU time 65.49 seconds
Started Sep 09 07:19:36 PM UTC 24
Finished Sep 09 07:20:44 PM UTC 24
Peak memory 207592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176958590 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.3176958590
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/0.hmac_test_sha256_vectors.2119216209
Short name T287
Test name
Test status
Simulation time 52458726812 ps
CPU time 743.83 seconds
Started Sep 09 07:19:35 PM UTC 24
Finished Sep 09 07:32:09 PM UTC 24
Peak memory 207352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119216209 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.2119216209
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/0.hmac_test_sha384_vectors.3176651935
Short name T34
Test name
Test status
Simulation time 41082570411 ps
CPU time 2315.7 seconds
Started Sep 09 07:19:36 PM UTC 24
Finished Sep 09 07:58:38 PM UTC 24
Peak memory 221436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176651935 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.3176651935
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/0.hmac_test_sha512_vectors.2703293523
Short name T35
Test name
Test status
Simulation time 178827926453 ps
CPU time 2333 seconds
Started Sep 09 07:19:36 PM UTC 24
Finished Sep 09 07:58:57 PM UTC 24
Peak memory 227424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703293523 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.2703293523
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/0.hmac_wipe_secret.1950935652
Short name T129
Test name
Test status
Simulation time 173987411865 ps
CPU time 155.87 seconds
Started Sep 09 07:19:35 PM UTC 24
Finished Sep 09 07:22:14 PM UTC 24
Peak memory 207276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950935652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1950935652
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/1.hmac_alert_test.4112963701
Short name T14
Test name
Test status
Simulation time 17220530 ps
CPU time 0.52 seconds
Started Sep 09 07:19:48 PM UTC 24
Finished Sep 09 07:19:50 PM UTC 24
Peak memory 203328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112963701 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.4112963701
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/1.hmac_back_pressure.3085572902
Short name T8
Test name
Test status
Simulation time 1625227004 ps
CPU time 44.72 seconds
Started Sep 09 07:19:40 PM UTC 24
Finished Sep 09 07:20:26 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085572902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3085572902
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/1.hmac_datapath_stress.330425734
Short name T318
Test name
Test status
Simulation time 6421754433 ps
CPU time 893.11 seconds
Started Sep 09 07:19:40 PM UTC 24
Finished Sep 09 07:34:43 PM UTC 24
Peak memory 756200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330425734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.330425734
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/1.hmac_long_msg.3905998601
Short name T93
Test name
Test status
Simulation time 11528942542 ps
CPU time 195.07 seconds
Started Sep 09 07:19:40 PM UTC 24
Finished Sep 09 07:22:58 PM UTC 24
Peak memory 215704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905998601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3905998601
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/1.hmac_sec_cm.1804344276
Short name T15
Test name
Test status
Simulation time 76922732 ps
CPU time 0.79 seconds
Started Sep 09 07:19:48 PM UTC 24
Finished Sep 09 07:19:50 PM UTC 24
Peak memory 235168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804344276 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1804344276
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/1.hmac_smoke.2767623676
Short name T6
Test name
Test status
Simulation time 643869530 ps
CPU time 9.6 seconds
Started Sep 09 07:19:39 PM UTC 24
Finished Sep 09 07:19:50 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767623676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2767623676
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/1.hmac_stress_all.1810367574
Short name T531
Test name
Test status
Simulation time 237541849233 ps
CPU time 4577.33 seconds
Started Sep 09 07:19:47 PM UTC 24
Finished Sep 09 08:36:51 PM UTC 24
Peak memory 864372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810367574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1810367574
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/1.hmac_test_hmac256_vectors.4074404353
Short name T64
Test name
Test status
Simulation time 6920087835 ps
CPU time 53.67 seconds
Started Sep 09 07:19:43 PM UTC 24
Finished Sep 09 07:20:39 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074404353 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.4074404353
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/1.hmac_test_hmac384_vectors.2949519885
Short name T58
Test name
Test status
Simulation time 9221345393 ps
CPU time 86.77 seconds
Started Sep 09 07:19:44 PM UTC 24
Finished Sep 09 07:21:13 PM UTC 24
Peak memory 207400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949519885 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2949519885
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/1.hmac_test_hmac512_vectors.3357318025
Short name T167
Test name
Test status
Simulation time 22446027802 ps
CPU time 126.69 seconds
Started Sep 09 07:19:46 PM UTC 24
Finished Sep 09 07:21:55 PM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357318025 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.3357318025
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/1.hmac_test_sha256_vectors.2900243545
Short name T239
Test name
Test status
Simulation time 8984653223 ps
CPU time 510.66 seconds
Started Sep 09 07:19:42 PM UTC 24
Finished Sep 09 07:28:19 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900243545 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.2900243545
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/1.hmac_test_sha384_vectors.3647092287
Short name T515
Test name
Test status
Simulation time 205797647608 ps
CPU time 2664.93 seconds
Started Sep 09 07:19:42 PM UTC 24
Finished Sep 09 08:04:37 PM UTC 24
Peak memory 225400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647092287 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.3647092287
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/1.hmac_test_sha512_vectors.4019534525
Short name T518
Test name
Test status
Simulation time 391926700676 ps
CPU time 2779.67 seconds
Started Sep 09 07:19:43 PM UTC 24
Finished Sep 09 08:06:35 PM UTC 24
Peak memory 227428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019534525 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.4019534525
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/1.hmac_wipe_secret.308205729
Short name T9
Test name
Test status
Simulation time 2722667256 ps
CPU time 17.8 seconds
Started Sep 09 07:19:41 PM UTC 24
Finished Sep 09 07:20:00 PM UTC 24
Peak memory 207416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308205729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.308205729
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/1.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/10.hmac_alert_test.2775902771
Short name T177
Test name
Test status
Simulation time 19489706 ps
CPU time 0.83 seconds
Started Sep 09 07:23:41 PM UTC 24
Finished Sep 09 07:23:42 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775902771 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2775902771
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/10.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/10.hmac_back_pressure.2648392635
Short name T182
Test name
Test status
Simulation time 4690699145 ps
CPU time 61.93 seconds
Started Sep 09 07:23:15 PM UTC 24
Finished Sep 09 07:24:19 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648392635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2648392635
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/10.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/10.hmac_burst_wr.1595663418
Short name T181
Test name
Test status
Simulation time 6576081953 ps
CPU time 37.01 seconds
Started Sep 09 07:23:31 PM UTC 24
Finished Sep 09 07:24:09 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595663418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1595663418
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/10.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/10.hmac_datapath_stress.1207476900
Short name T406
Test name
Test status
Simulation time 20892856411 ps
CPU time 1069.76 seconds
Started Sep 09 07:23:22 PM UTC 24
Finished Sep 09 07:41:23 PM UTC 24
Peak memory 774572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207476900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1207476900
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/10.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/10.hmac_error.3174988365
Short name T189
Test name
Test status
Simulation time 3733290167 ps
CPU time 72.37 seconds
Started Sep 09 07:23:32 PM UTC 24
Finished Sep 09 07:24:46 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174988365 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3174988365
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/10.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/10.hmac_long_msg.495575943
Short name T206
Test name
Test status
Simulation time 38595268844 ps
CPU time 148.35 seconds
Started Sep 09 07:23:12 PM UTC 24
Finished Sep 09 07:25:43 PM UTC 24
Peak memory 215960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495575943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.495575943
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/10.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/10.hmac_smoke.3925369260
Short name T175
Test name
Test status
Simulation time 873365431 ps
CPU time 18.12 seconds
Started Sep 09 07:23:12 PM UTC 24
Finished Sep 09 07:23:31 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925369260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3925369260
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/10.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/10.hmac_wipe_secret.186499283
Short name T131
Test name
Test status
Simulation time 9628196110 ps
CPU time 136.21 seconds
Started Sep 09 07:23:37 PM UTC 24
Finished Sep 09 07:25:56 PM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186499283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.186499283
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/10.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/11.hmac_alert_test.3035133585
Short name T180
Test name
Test status
Simulation time 14002569 ps
CPU time 0.87 seconds
Started Sep 09 07:24:02 PM UTC 24
Finished Sep 09 07:24:05 PM UTC 24
Peak memory 203644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035133585 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3035133585
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/11.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/11.hmac_back_pressure.1147552478
Short name T190
Test name
Test status
Simulation time 4598596617 ps
CPU time 63.62 seconds
Started Sep 09 07:23:43 PM UTC 24
Finished Sep 09 07:24:49 PM UTC 24
Peak memory 215800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147552478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1147552478
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/11.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/11.hmac_burst_wr.779795486
Short name T199
Test name
Test status
Simulation time 4453579576 ps
CPU time 90.98 seconds
Started Sep 09 07:23:50 PM UTC 24
Finished Sep 09 07:25:23 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779795486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.779795486
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/11.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/11.hmac_datapath_stress.2788391163
Short name T254
Test name
Test status
Simulation time 2029301289 ps
CPU time 333.46 seconds
Started Sep 09 07:23:47 PM UTC 24
Finished Sep 09 07:29:24 PM UTC 24
Peak memory 694560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788391163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2788391163
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/11.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/11.hmac_error.668103075
Short name T214
Test name
Test status
Simulation time 5986410319 ps
CPU time 125.8 seconds
Started Sep 09 07:23:51 PM UTC 24
Finished Sep 09 07:25:59 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668103075 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.668103075
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/11.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/11.hmac_long_msg.3976207881
Short name T207
Test name
Test status
Simulation time 7609885829 ps
CPU time 120.76 seconds
Started Sep 09 07:23:43 PM UTC 24
Finished Sep 09 07:25:48 PM UTC 24
Peak memory 215704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976207881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3976207881
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/11.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/11.hmac_smoke.394356477
Short name T161
Test name
Test status
Simulation time 1009462228 ps
CPU time 15.88 seconds
Started Sep 09 07:23:43 PM UTC 24
Finished Sep 09 07:24:00 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394356477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.394356477
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/11.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/11.hmac_stress_all.3082842991
Short name T417
Test name
Test status
Simulation time 43564018748 ps
CPU time 1070.85 seconds
Started Sep 09 07:24:02 PM UTC 24
Finished Sep 09 07:42:07 PM UTC 24
Peak memory 489600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082842991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3082842991
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/11.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/11.hmac_wipe_secret.3818401911
Short name T193
Test name
Test status
Simulation time 6588814315 ps
CPU time 54.89 seconds
Started Sep 09 07:23:59 PM UTC 24
Finished Sep 09 07:24:56 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818401911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3818401911
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/11.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/12.hmac_alert_test.749348687
Short name T187
Test name
Test status
Simulation time 12894666 ps
CPU time 0.83 seconds
Started Sep 09 07:24:39 PM UTC 24
Finished Sep 09 07:24:41 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749348687 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.749348687
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/12.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/12.hmac_back_pressure.2016311542
Short name T202
Test name
Test status
Simulation time 4388551087 ps
CPU time 76.93 seconds
Started Sep 09 07:24:20 PM UTC 24
Finished Sep 09 07:25:39 PM UTC 24
Peak memory 207360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016311542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2016311542
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/12.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/12.hmac_burst_wr.519402477
Short name T151
Test name
Test status
Simulation time 19410613467 ps
CPU time 68.38 seconds
Started Sep 09 07:24:26 PM UTC 24
Finished Sep 09 07:25:36 PM UTC 24
Peak memory 217928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519402477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.519402477
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/12.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/12.hmac_datapath_stress.4227637473
Short name T184
Test name
Test status
Simulation time 26773808 ps
CPU time 1.07 seconds
Started Sep 09 07:24:23 PM UTC 24
Finished Sep 09 07:24:25 PM UTC 24
Peak memory 205860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227637473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.4227637473
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/12.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/12.hmac_error.4115195599
Short name T218
Test name
Test status
Simulation time 10794907211 ps
CPU time 109.09 seconds
Started Sep 09 07:24:28 PM UTC 24
Finished Sep 09 07:26:19 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115195599 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.4115195599
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/12.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/12.hmac_long_msg.3613397576
Short name T210
Test name
Test status
Simulation time 12084279663 ps
CPU time 100.61 seconds
Started Sep 09 07:24:10 PM UTC 24
Finished Sep 09 07:25:53 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613397576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3613397576
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/12.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/12.hmac_smoke.3468274115
Short name T183
Test name
Test status
Simulation time 8499583012 ps
CPU time 16.05 seconds
Started Sep 09 07:24:05 PM UTC 24
Finished Sep 09 07:24:23 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468274115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3468274115
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/12.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/12.hmac_stress_all.636026828
Short name T83
Test name
Test status
Simulation time 37161122 ps
CPU time 0.92 seconds
Started Sep 09 07:24:35 PM UTC 24
Finished Sep 09 07:24:37 PM UTC 24
Peak memory 203676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636026828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.636026828
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/12.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/12.hmac_wipe_secret.3273909570
Short name T204
Test name
Test status
Simulation time 10635732042 ps
CPU time 68 seconds
Started Sep 09 07:24:30 PM UTC 24
Finished Sep 09 07:25:40 PM UTC 24
Peak memory 207484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273909570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3273909570
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/12.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/13.hmac_alert_test.3504749556
Short name T197
Test name
Test status
Simulation time 14858229 ps
CPU time 0.92 seconds
Started Sep 09 07:25:04 PM UTC 24
Finished Sep 09 07:25:06 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504749556 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3504749556
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/13.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/13.hmac_back_pressure.2827961771
Short name T200
Test name
Test status
Simulation time 2391699478 ps
CPU time 38.4 seconds
Started Sep 09 07:24:44 PM UTC 24
Finished Sep 09 07:25:24 PM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827961771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2827961771
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/13.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/13.hmac_burst_wr.2612306523
Short name T194
Test name
Test status
Simulation time 848139975 ps
CPU time 12.82 seconds
Started Sep 09 07:24:50 PM UTC 24
Finished Sep 09 07:25:04 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612306523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2612306523
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/13.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/13.hmac_datapath_stress.2856837366
Short name T458
Test name
Test status
Simulation time 13238499639 ps
CPU time 1270.41 seconds
Started Sep 09 07:24:47 PM UTC 24
Finished Sep 09 07:46:12 PM UTC 24
Peak memory 536900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856837366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2856837366
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/13.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/13.hmac_error.788339392
Short name T225
Test name
Test status
Simulation time 29072830795 ps
CPU time 139.04 seconds
Started Sep 09 07:24:52 PM UTC 24
Finished Sep 09 07:27:13 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788339392 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.788339392
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/13.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/13.hmac_long_msg.3359937922
Short name T219
Test name
Test status
Simulation time 17287002125 ps
CPU time 94.84 seconds
Started Sep 09 07:24:42 PM UTC 24
Finished Sep 09 07:26:19 PM UTC 24
Peak memory 215900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359937922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3359937922
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/13.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/13.hmac_smoke.2478984207
Short name T192
Test name
Test status
Simulation time 539615494 ps
CPU time 12.63 seconds
Started Sep 09 07:24:39 PM UTC 24
Finished Sep 09 07:24:53 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478984207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2478984207
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/13.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/13.hmac_stress_all.4275908674
Short name T468
Test name
Test status
Simulation time 33352072185 ps
CPU time 1314.28 seconds
Started Sep 09 07:24:56 PM UTC 24
Finished Sep 09 07:47:06 PM UTC 24
Peak memory 758240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275908674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.4275908674
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/13.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/13.hmac_wipe_secret.3171136121
Short name T97
Test name
Test status
Simulation time 15215115303 ps
CPU time 136.4 seconds
Started Sep 09 07:24:54 PM UTC 24
Finished Sep 09 07:27:13 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171136121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3171136121
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/13.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/14.hmac_alert_test.2740821921
Short name T205
Test name
Test status
Simulation time 77427617 ps
CPU time 0.88 seconds
Started Sep 09 07:25:41 PM UTC 24
Finished Sep 09 07:25:43 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740821921 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2740821921
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/14.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/14.hmac_back_pressure.1685511781
Short name T203
Test name
Test status
Simulation time 764768614 ps
CPU time 31.09 seconds
Started Sep 09 07:25:07 PM UTC 24
Finished Sep 09 07:25:39 PM UTC 24
Peak memory 207176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685511781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1685511781
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/14.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/14.hmac_burst_wr.642619213
Short name T201
Test name
Test status
Simulation time 288669696 ps
CPU time 2.19 seconds
Started Sep 09 07:25:24 PM UTC 24
Finished Sep 09 07:25:27 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642619213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.642619213
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/14.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/14.hmac_datapath_stress.241322922
Short name T436
Test name
Test status
Simulation time 10932221032 ps
CPU time 1126.94 seconds
Started Sep 09 07:25:16 PM UTC 24
Finished Sep 09 07:44:15 PM UTC 24
Peak memory 786660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241322922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.241322922
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/14.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/14.hmac_error.538674366
Short name T244
Test name
Test status
Simulation time 182165475408 ps
CPU time 197.87 seconds
Started Sep 09 07:25:25 PM UTC 24
Finished Sep 09 07:28:47 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538674366 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.538674366
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/14.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/14.hmac_long_msg.3045359114
Short name T211
Test name
Test status
Simulation time 601287217 ps
CPU time 45.03 seconds
Started Sep 09 07:25:07 PM UTC 24
Finished Sep 09 07:25:53 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045359114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3045359114
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/14.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/14.hmac_smoke.2164947920
Short name T198
Test name
Test status
Simulation time 1082174043 ps
CPU time 6.99 seconds
Started Sep 09 07:25:07 PM UTC 24
Finished Sep 09 07:25:15 PM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164947920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2164947920
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/14.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/14.hmac_stress_all.4276922479
Short name T524
Test name
Test status
Simulation time 286080641406 ps
CPU time 2747.33 seconds
Started Sep 09 07:25:38 PM UTC 24
Finished Sep 09 08:11:56 PM UTC 24
Peak memory 801064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276922479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.4276922479
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/14.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/14.hmac_wipe_secret.2243100759
Short name T232
Test name
Test status
Simulation time 8698700091 ps
CPU time 134.87 seconds
Started Sep 09 07:25:29 PM UTC 24
Finished Sep 09 07:27:47 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243100759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2243100759
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/14.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/15.hmac_alert_test.3898835696
Short name T213
Test name
Test status
Simulation time 13475783 ps
CPU time 0.91 seconds
Started Sep 09 07:25:56 PM UTC 24
Finished Sep 09 07:25:57 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898835696 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3898835696
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/15.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/15.hmac_back_pressure.1978794324
Short name T212
Test name
Test status
Simulation time 595769912 ps
CPU time 10.3 seconds
Started Sep 09 07:25:44 PM UTC 24
Finished Sep 09 07:25:55 PM UTC 24
Peak memory 207216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978794324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1978794324
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/15.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/15.hmac_burst_wr.2382388551
Short name T222
Test name
Test status
Simulation time 13629882838 ps
CPU time 61.85 seconds
Started Sep 09 07:25:49 PM UTC 24
Finished Sep 09 07:26:54 PM UTC 24
Peak memory 207436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382388551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2382388551
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/15.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/15.hmac_datapath_stress.2486480969
Short name T248
Test name
Test status
Simulation time 2869690098 ps
CPU time 197.29 seconds
Started Sep 09 07:25:44 PM UTC 24
Finished Sep 09 07:29:04 PM UTC 24
Peak memory 708952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486480969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2486480969
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/15.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/15.hmac_error.1030600064
Short name T230
Test name
Test status
Simulation time 1307827923 ps
CPU time 97.21 seconds
Started Sep 09 07:25:53 PM UTC 24
Finished Sep 09 07:27:32 PM UTC 24
Peak memory 207156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030600064 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1030600064
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/15.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/15.hmac_long_msg.1574320071
Short name T234
Test name
Test status
Simulation time 4594001688 ps
CPU time 130.48 seconds
Started Sep 09 07:25:42 PM UTC 24
Finished Sep 09 07:27:55 PM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574320071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1574320071
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/15.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/15.hmac_smoke.3923658577
Short name T208
Test name
Test status
Simulation time 411340460 ps
CPU time 9.58 seconds
Started Sep 09 07:25:41 PM UTC 24
Finished Sep 09 07:25:52 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923658577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3923658577
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/15.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/15.hmac_stress_all.1351235984
Short name T36
Test name
Test status
Simulation time 58435952161 ps
CPU time 1992.59 seconds
Started Sep 09 07:25:56 PM UTC 24
Finished Sep 09 07:59:27 PM UTC 24
Peak memory 772324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351235984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1351235984
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/15.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/15.hmac_wipe_secret.2919507855
Short name T132
Test name
Test status
Simulation time 981449689 ps
CPU time 34 seconds
Started Sep 09 07:25:55 PM UTC 24
Finished Sep 09 07:26:31 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919507855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2919507855
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/15.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/16.hmac_alert_test.828769373
Short name T220
Test name
Test status
Simulation time 39733264 ps
CPU time 0.93 seconds
Started Sep 09 07:26:20 PM UTC 24
Finished Sep 09 07:26:22 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828769373 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.828769373
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/16.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/16.hmac_back_pressure.1540264219
Short name T229
Test name
Test status
Simulation time 1132133082 ps
CPU time 83.81 seconds
Started Sep 09 07:25:58 PM UTC 24
Finished Sep 09 07:27:24 PM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540264219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1540264219
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/16.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/16.hmac_burst_wr.1064020622
Short name T228
Test name
Test status
Simulation time 2878416900 ps
CPU time 72.51 seconds
Started Sep 09 07:26:07 PM UTC 24
Finished Sep 09 07:27:21 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064020622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1064020622
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/16.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/16.hmac_datapath_stress.4240718192
Short name T282
Test name
Test status
Simulation time 5491267622 ps
CPU time 350.73 seconds
Started Sep 09 07:26:01 PM UTC 24
Finished Sep 09 07:31:56 PM UTC 24
Peak memory 674016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240718192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.4240718192
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/16.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/16.hmac_error.3005279537
Short name T258
Test name
Test status
Simulation time 15358807702 ps
CPU time 210.15 seconds
Started Sep 09 07:26:11 PM UTC 24
Finished Sep 09 07:29:44 PM UTC 24
Peak memory 207484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005279537 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3005279537
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/16.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/16.hmac_long_msg.2595579951
Short name T235
Test name
Test status
Simulation time 1629338028 ps
CPU time 115.85 seconds
Started Sep 09 07:25:57 PM UTC 24
Finished Sep 09 07:27:55 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595579951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2595579951
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/16.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/16.hmac_smoke.397574671
Short name T215
Test name
Test status
Simulation time 307131111 ps
CPU time 8.29 seconds
Started Sep 09 07:25:57 PM UTC 24
Finished Sep 09 07:26:07 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397574671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.397574671
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/16.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/16.hmac_stress_all.2673077481
Short name T509
Test name
Test status
Simulation time 117566778129 ps
CPU time 1893.42 seconds
Started Sep 09 07:26:18 PM UTC 24
Finished Sep 09 07:58:12 PM UTC 24
Peak memory 747748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673077481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2673077481
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/16.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/16.hmac_wipe_secret.638203500
Short name T217
Test name
Test status
Simulation time 15025025 ps
CPU time 1.33 seconds
Started Sep 09 07:26:15 PM UTC 24
Finished Sep 09 07:26:17 PM UTC 24
Peak memory 206460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638203500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.638203500
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/16.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/17.hmac_alert_test.3546013346
Short name T226
Test name
Test status
Simulation time 57650651 ps
CPU time 0.83 seconds
Started Sep 09 07:27:16 PM UTC 24
Finished Sep 09 07:27:17 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546013346 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3546013346
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/17.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/17.hmac_back_pressure.838598808
Short name T224
Test name
Test status
Simulation time 519035119 ps
CPU time 40.41 seconds
Started Sep 09 07:26:25 PM UTC 24
Finished Sep 09 07:27:07 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838598808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.838598808
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/17.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/17.hmac_burst_wr.586290154
Short name T231
Test name
Test status
Simulation time 5418186045 ps
CPU time 51.86 seconds
Started Sep 09 07:26:51 PM UTC 24
Finished Sep 09 07:27:45 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586290154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.586290154
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/17.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/17.hmac_datapath_stress.1634202699
Short name T144
Test name
Test status
Simulation time 555039249 ps
CPU time 76.26 seconds
Started Sep 09 07:26:32 PM UTC 24
Finished Sep 09 07:27:50 PM UTC 24
Peak memory 405708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634202699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1634202699
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/17.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/17.hmac_error.736820724
Short name T253
Test name
Test status
Simulation time 8353430834 ps
CPU time 142.94 seconds
Started Sep 09 07:26:55 PM UTC 24
Finished Sep 09 07:29:22 PM UTC 24
Peak memory 207280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736820724 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.736820724
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/17.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/17.hmac_long_msg.1010150950
Short name T250
Test name
Test status
Simulation time 83467958995 ps
CPU time 167.03 seconds
Started Sep 09 07:26:23 PM UTC 24
Finished Sep 09 07:29:13 PM UTC 24
Peak memory 217824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010150950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1010150950
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/17.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/17.hmac_smoke.1571433413
Short name T221
Test name
Test status
Simulation time 46716931 ps
CPU time 2.93 seconds
Started Sep 09 07:26:20 PM UTC 24
Finished Sep 09 07:26:24 PM UTC 24
Peak memory 207168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571433413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1571433413
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/17.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/17.hmac_wipe_secret.3925317663
Short name T238
Test name
Test status
Simulation time 8352808318 ps
CPU time 75.31 seconds
Started Sep 09 07:27:00 PM UTC 24
Finished Sep 09 07:28:17 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925317663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3925317663
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/17.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/18.hmac_alert_test.1957956724
Short name T233
Test name
Test status
Simulation time 13204242 ps
CPU time 0.85 seconds
Started Sep 09 07:27:50 PM UTC 24
Finished Sep 09 07:27:52 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957956724 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1957956724
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/18.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/18.hmac_back_pressure.2258744668
Short name T241
Test name
Test status
Simulation time 3876458914 ps
CPU time 76.97 seconds
Started Sep 09 07:27:22 PM UTC 24
Finished Sep 09 07:28:41 PM UTC 24
Peak memory 215752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258744668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2258744668
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/18.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/18.hmac_burst_wr.219373858
Short name T236
Test name
Test status
Simulation time 2093915647 ps
CPU time 40.24 seconds
Started Sep 09 07:27:26 PM UTC 24
Finished Sep 09 07:28:07 PM UTC 24
Peak memory 215880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219373858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.219373858
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/18.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/18.hmac_datapath_stress.2711416822
Short name T358
Test name
Test status
Simulation time 3233340924 ps
CPU time 623.89 seconds
Started Sep 09 07:27:23 PM UTC 24
Finished Sep 09 07:37:54 PM UTC 24
Peak memory 700956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711416822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2711416822
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/18.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/18.hmac_error.2477954799
Short name T299
Test name
Test status
Simulation time 77119756130 ps
CPU time 303.03 seconds
Started Sep 09 07:27:33 PM UTC 24
Finished Sep 09 07:32:41 PM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477954799 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2477954799
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/18.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/18.hmac_long_msg.1457235936
Short name T246
Test name
Test status
Simulation time 3108348846 ps
CPU time 98.33 seconds
Started Sep 09 07:27:19 PM UTC 24
Finished Sep 09 07:28:59 PM UTC 24
Peak memory 215764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457235936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1457235936
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/18.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/18.hmac_smoke.969498227
Short name T227
Test name
Test status
Simulation time 611878212 ps
CPU time 4.24 seconds
Started Sep 09 07:27:16 PM UTC 24
Finished Sep 09 07:27:21 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969498227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.969498227
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/18.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/18.hmac_stress_all.1866841770
Short name T501
Test name
Test status
Simulation time 147417351189 ps
CPU time 1624.66 seconds
Started Sep 09 07:27:48 PM UTC 24
Finished Sep 09 07:55:11 PM UTC 24
Peak memory 698600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866841770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1866841770
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/18.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/18.hmac_wipe_secret.470769231
Short name T261
Test name
Test status
Simulation time 6143457100 ps
CPU time 135.43 seconds
Started Sep 09 07:27:46 PM UTC 24
Finished Sep 09 07:30:04 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470769231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.470769231
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/18.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/19.hmac_alert_test.957476199
Short name T242
Test name
Test status
Simulation time 41599159 ps
CPU time 0.87 seconds
Started Sep 09 07:28:42 PM UTC 24
Finished Sep 09 07:28:44 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957476199 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.957476199
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/19.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/19.hmac_back_pressure.4115672499
Short name T255
Test name
Test status
Simulation time 1237917178 ps
CPU time 88.66 seconds
Started Sep 09 07:27:57 PM UTC 24
Finished Sep 09 07:29:28 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115672499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.4115672499
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/19.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/19.hmac_burst_wr.3086465063
Short name T240
Test name
Test status
Simulation time 480450843 ps
CPU time 8.07 seconds
Started Sep 09 07:28:12 PM UTC 24
Finished Sep 09 07:28:21 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086465063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3086465063
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/19.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/19.hmac_datapath_stress.3329927133
Short name T482
Test name
Test status
Simulation time 42231122564 ps
CPU time 1201.87 seconds
Started Sep 09 07:28:08 PM UTC 24
Finished Sep 09 07:48:23 PM UTC 24
Peak memory 712984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329927133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3329927133
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/19.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/19.hmac_error.1070735129
Short name T280
Test name
Test status
Simulation time 10423806068 ps
CPU time 206.84 seconds
Started Sep 09 07:28:18 PM UTC 24
Finished Sep 09 07:31:48 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070735129 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1070735129
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/19.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/19.hmac_long_msg.3671996100
Short name T249
Test name
Test status
Simulation time 3733754938 ps
CPU time 67.35 seconds
Started Sep 09 07:27:57 PM UTC 24
Finished Sep 09 07:29:06 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671996100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3671996100
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/19.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/19.hmac_smoke.2801858461
Short name T237
Test name
Test status
Simulation time 12216574287 ps
CPU time 15.98 seconds
Started Sep 09 07:27:54 PM UTC 24
Finished Sep 09 07:28:11 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801858461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2801858461
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/19.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/19.hmac_stress_all.3619025573
Short name T38
Test name
Test status
Simulation time 45004157753 ps
CPU time 1890.2 seconds
Started Sep 09 07:28:23 PM UTC 24
Finished Sep 09 08:00:13 PM UTC 24
Peak memory 753964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619025573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3619025573
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/19.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/19.hmac_wipe_secret.1958247994
Short name T247
Test name
Test status
Simulation time 768194517 ps
CPU time 36.48 seconds
Started Sep 09 07:28:23 PM UTC 24
Finished Sep 09 07:29:01 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958247994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1958247994
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/19.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/2.hmac_alert_test.1042447783
Short name T33
Test name
Test status
Simulation time 11600367 ps
CPU time 0.88 seconds
Started Sep 09 07:20:11 PM UTC 24
Finished Sep 09 07:20:12 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042447783 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1042447783
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/2.hmac_back_pressure.1253702345
Short name T19
Test name
Test status
Simulation time 1132608687 ps
CPU time 64.69 seconds
Started Sep 09 07:19:50 PM UTC 24
Finished Sep 09 07:20:57 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253702345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1253702345
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/2.hmac_burst_wr.3926906746
Short name T17
Test name
Test status
Simulation time 42638539093 ps
CPU time 57.56 seconds
Started Sep 09 07:19:50 PM UTC 24
Finished Sep 09 07:20:49 PM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926906746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3926906746
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/2.hmac_datapath_stress.3651873648
Short name T359
Test name
Test status
Simulation time 23744364691 ps
CPU time 1076.2 seconds
Started Sep 09 07:19:50 PM UTC 24
Finished Sep 09 07:37:57 PM UTC 24
Peak memory 770536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651873648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3651873648
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/2.hmac_error.1183249726
Short name T61
Test name
Test status
Simulation time 4160115752 ps
CPU time 116.83 seconds
Started Sep 09 07:19:56 PM UTC 24
Finished Sep 09 07:21:55 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183249726 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1183249726
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/2.hmac_long_msg.3842364367
Short name T48
Test name
Test status
Simulation time 53511303348 ps
CPU time 178.48 seconds
Started Sep 09 07:19:50 PM UTC 24
Finished Sep 09 07:22:52 PM UTC 24
Peak memory 217752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842364367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3842364367
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/2.hmac_sec_cm.854971404
Short name T32
Test name
Test status
Simulation time 82367274 ps
CPU time 1.6 seconds
Started Sep 09 07:20:09 PM UTC 24
Finished Sep 09 07:20:12 PM UTC 24
Peak memory 235568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854971404 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.854971404
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/2.hmac_stress_all.2343328905
Short name T86
Test name
Test status
Simulation time 54902252867 ps
CPU time 928.56 seconds
Started Sep 09 07:20:06 PM UTC 24
Finished Sep 09 07:35:46 PM UTC 24
Peak memory 499992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343328905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2343328905
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/2.hmac_test_hmac256_vectors.270203237
Short name T65
Test name
Test status
Simulation time 3032306151 ps
CPU time 46.99 seconds
Started Sep 09 07:20:03 PM UTC 24
Finished Sep 09 07:20:51 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270203237 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.270203237
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/2.hmac_test_hmac384_vectors.3960339999
Short name T164
Test name
Test status
Simulation time 5436647571 ps
CPU time 61.41 seconds
Started Sep 09 07:20:04 PM UTC 24
Finished Sep 09 07:21:07 PM UTC 24
Peak memory 207400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960339999 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.3960339999
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/2.hmac_test_hmac512_vectors.1479117412
Short name T77
Test name
Test status
Simulation time 9461288903 ps
CPU time 83.09 seconds
Started Sep 09 07:20:04 PM UTC 24
Finished Sep 09 07:21:29 PM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479117412 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1479117412
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/2.hmac_test_sha256_vectors.2194019763
Short name T147
Test name
Test status
Simulation time 90452481360 ps
CPU time 579.21 seconds
Started Sep 09 07:20:02 PM UTC 24
Finished Sep 09 07:29:48 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194019763 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.2194019763
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/2.hmac_test_sha384_vectors.3892052615
Short name T516
Test name
Test status
Simulation time 204241240564 ps
CPU time 2673.8 seconds
Started Sep 09 07:20:02 PM UTC 24
Finished Sep 09 08:05:05 PM UTC 24
Peak memory 223280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892052615 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3892052615
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/2.hmac_test_sha512_vectors.1544765055
Short name T41
Test name
Test status
Simulation time 380325962827 ps
CPU time 2508.8 seconds
Started Sep 09 07:20:03 PM UTC 24
Finished Sep 09 08:02:20 PM UTC 24
Peak memory 217724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544765055 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1544765055
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/2.hmac_wipe_secret.1757584728
Short name T51
Test name
Test status
Simulation time 3122817426 ps
CPU time 74.64 seconds
Started Sep 09 07:19:56 PM UTC 24
Finished Sep 09 07:21:13 PM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757584728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1757584728
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/2.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/20.hmac_alert_test.123680992
Short name T251
Test name
Test status
Simulation time 31819111 ps
CPU time 0.82 seconds
Started Sep 09 07:29:15 PM UTC 24
Finished Sep 09 07:29:17 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123680992 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.123680992
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/20.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/20.hmac_back_pressure.695703336
Short name T252
Test name
Test status
Simulation time 371463924 ps
CPU time 28.37 seconds
Started Sep 09 07:28:49 PM UTC 24
Finished Sep 09 07:29:19 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695703336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.695703336
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/20.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/20.hmac_burst_wr.207672486
Short name T262
Test name
Test status
Simulation time 21674530504 ps
CPU time 71.1 seconds
Started Sep 09 07:29:01 PM UTC 24
Finished Sep 09 07:30:14 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207672486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.207672486
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/20.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/20.hmac_datapath_stress.2856326823
Short name T364
Test name
Test status
Simulation time 12025628428 ps
CPU time 559.89 seconds
Started Sep 09 07:28:52 PM UTC 24
Finished Sep 09 07:38:18 PM UTC 24
Peak memory 704808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856326823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2856326823
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/20.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/20.hmac_error.1651104475
Short name T270
Test name
Test status
Simulation time 25606633441 ps
CPU time 111.17 seconds
Started Sep 09 07:29:02 PM UTC 24
Finished Sep 09 07:30:55 PM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651104475 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1651104475
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/20.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/20.hmac_long_msg.4126011307
Short name T277
Test name
Test status
Simulation time 12058376679 ps
CPU time 160.49 seconds
Started Sep 09 07:28:47 PM UTC 24
Finished Sep 09 07:31:30 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126011307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.4126011307
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/20.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/20.hmac_smoke.681111910
Short name T245
Test name
Test status
Simulation time 665742215 ps
CPU time 5.11 seconds
Started Sep 09 07:28:45 PM UTC 24
Finished Sep 09 07:28:51 PM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681111910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.681111910
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/20.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/20.hmac_stress_all.3041422428
Short name T284
Test name
Test status
Simulation time 27147856120 ps
CPU time 170.78 seconds
Started Sep 09 07:29:08 PM UTC 24
Finished Sep 09 07:32:02 PM UTC 24
Peak memory 219776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041422428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3041422428
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/20.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/20.hmac_wipe_secret.1393638265
Short name T98
Test name
Test status
Simulation time 7416528553 ps
CPU time 105.99 seconds
Started Sep 09 07:29:06 PM UTC 24
Finished Sep 09 07:30:54 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393638265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1393638265
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/20.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/21.hmac_alert_test.3785057334
Short name T257
Test name
Test status
Simulation time 34884448 ps
CPU time 0.82 seconds
Started Sep 09 07:29:35 PM UTC 24
Finished Sep 09 07:29:37 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785057334 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3785057334
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/21.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/21.hmac_back_pressure.1778437763
Short name T265
Test name
Test status
Simulation time 1786408838 ps
CPU time 66.22 seconds
Started Sep 09 07:29:23 PM UTC 24
Finished Sep 09 07:30:31 PM UTC 24
Peak memory 207424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778437763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1778437763
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/21.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/21.hmac_burst_wr.3497427293
Short name T152
Test name
Test status
Simulation time 1762066844 ps
CPU time 44.72 seconds
Started Sep 09 07:29:26 PM UTC 24
Finished Sep 09 07:30:13 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497427293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3497427293
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/21.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/21.hmac_datapath_stress.376559086
Short name T42
Test name
Test status
Simulation time 32335023006 ps
CPU time 1959.68 seconds
Started Sep 09 07:29:26 PM UTC 24
Finished Sep 09 08:02:27 PM UTC 24
Peak memory 790752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376559086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.376559086
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/21.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/21.hmac_error.3402780644
Short name T260
Test name
Test status
Simulation time 1588320880 ps
CPU time 32.19 seconds
Started Sep 09 07:29:29 PM UTC 24
Finished Sep 09 07:30:03 PM UTC 24
Peak memory 207056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402780644 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3402780644
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/21.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/21.hmac_long_msg.3943312544
Short name T276
Test name
Test status
Simulation time 3728168166 ps
CPU time 125.62 seconds
Started Sep 09 07:29:19 PM UTC 24
Finished Sep 09 07:31:27 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943312544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3943312544
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/21.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/21.hmac_smoke.1331343602
Short name T256
Test name
Test status
Simulation time 948942156 ps
CPU time 9.42 seconds
Started Sep 09 07:29:18 PM UTC 24
Finished Sep 09 07:29:29 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331343602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1331343602
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/21.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/21.hmac_stress_all.544378534
Short name T352
Test name
Test status
Simulation time 181572756831 ps
CPU time 458.47 seconds
Started Sep 09 07:29:31 PM UTC 24
Finished Sep 09 07:37:16 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544378534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.544378534
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/21.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/21.hmac_wipe_secret.3913824776
Short name T99
Test name
Test status
Simulation time 6666060112 ps
CPU time 105.09 seconds
Started Sep 09 07:29:29 PM UTC 24
Finished Sep 09 07:31:17 PM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913824776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3913824776
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/21.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/22.hmac_alert_test.3679273647
Short name T264
Test name
Test status
Simulation time 15157521 ps
CPU time 0.89 seconds
Started Sep 09 07:30:22 PM UTC 24
Finished Sep 09 07:30:24 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679273647 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3679273647
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/22.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/22.hmac_back_pressure.3256964383
Short name T275
Test name
Test status
Simulation time 1417468056 ps
CPU time 92.15 seconds
Started Sep 09 07:29:47 PM UTC 24
Finished Sep 09 07:31:22 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256964383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3256964383
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/22.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/22.hmac_burst_wr.3487511273
Short name T268
Test name
Test status
Simulation time 2107017190 ps
CPU time 37.04 seconds
Started Sep 09 07:30:04 PM UTC 24
Finished Sep 09 07:30:43 PM UTC 24
Peak memory 207400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487511273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3487511273
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/22.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/22.hmac_datapath_stress.1667145756
Short name T289
Test name
Test status
Simulation time 803788867 ps
CPU time 138.98 seconds
Started Sep 09 07:29:52 PM UTC 24
Finished Sep 09 07:32:13 PM UTC 24
Peak memory 633312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667145756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1667145756
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/22.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/22.hmac_error.3954986926
Short name T306
Test name
Test status
Simulation time 119940360161 ps
CPU time 205.68 seconds
Started Sep 09 07:30:06 PM UTC 24
Finished Sep 09 07:33:35 PM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954986926 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3954986926
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/22.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/22.hmac_long_msg.3370796175
Short name T273
Test name
Test status
Simulation time 9867710458 ps
CPU time 76.14 seconds
Started Sep 09 07:29:46 PM UTC 24
Finished Sep 09 07:31:05 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370796175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3370796175
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/22.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/22.hmac_smoke.267248384
Short name T259
Test name
Test status
Simulation time 578451961 ps
CPU time 7.82 seconds
Started Sep 09 07:29:37 PM UTC 24
Finished Sep 09 07:29:46 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267248384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.267248384
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/22.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/22.hmac_stress_all.58342317
Short name T441
Test name
Test status
Simulation time 29002834958 ps
CPU time 867.8 seconds
Started Sep 09 07:30:14 PM UTC 24
Finished Sep 09 07:44:52 PM UTC 24
Peak memory 686368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58342317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.58342317
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/22.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/22.hmac_wipe_secret.2817814725
Short name T263
Test name
Test status
Simulation time 3427865595 ps
CPU time 7.01 seconds
Started Sep 09 07:30:13 PM UTC 24
Finished Sep 09 07:30:21 PM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817814725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2817814725
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/22.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/23.hmac_alert_test.4268608386
Short name T271
Test name
Test status
Simulation time 11157657 ps
CPU time 0.85 seconds
Started Sep 09 07:30:57 PM UTC 24
Finished Sep 09 07:30:59 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268608386 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.4268608386
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/23.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/23.hmac_back_pressure.1943668771
Short name T269
Test name
Test status
Simulation time 892395684 ps
CPU time 17.37 seconds
Started Sep 09 07:30:33 PM UTC 24
Finished Sep 09 07:30:51 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943668771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1943668771
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/23.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/23.hmac_burst_wr.1660459210
Short name T272
Test name
Test status
Simulation time 353666926 ps
CPU time 18.91 seconds
Started Sep 09 07:30:40 PM UTC 24
Finished Sep 09 07:31:00 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660459210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1660459210
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/23.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/23.hmac_datapath_stress.2409867394
Short name T461
Test name
Test status
Simulation time 9329490166 ps
CPU time 943.52 seconds
Started Sep 09 07:30:40 PM UTC 24
Finished Sep 09 07:46:34 PM UTC 24
Peak memory 668108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409867394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2409867394
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/23.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/23.hmac_error.3409006427
Short name T292
Test name
Test status
Simulation time 6722360553 ps
CPU time 99.39 seconds
Started Sep 09 07:30:43 PM UTC 24
Finished Sep 09 07:32:25 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409006427 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3409006427
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/23.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/23.hmac_long_msg.3848465786
Short name T300
Test name
Test status
Simulation time 6282176356 ps
CPU time 139.01 seconds
Started Sep 09 07:30:27 PM UTC 24
Finished Sep 09 07:32:49 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848465786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3848465786
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/23.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/23.hmac_smoke.2347541528
Short name T267
Test name
Test status
Simulation time 2229918722 ps
CPU time 11.22 seconds
Started Sep 09 07:30:27 PM UTC 24
Finished Sep 09 07:30:39 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347541528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2347541528
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/23.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/23.hmac_stress_all.4267529735
Short name T527
Test name
Test status
Simulation time 378806217378 ps
CPU time 2935.23 seconds
Started Sep 09 07:30:55 PM UTC 24
Finished Sep 09 08:20:18 PM UTC 24
Peak memory 794800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267529735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.4267529735
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/23.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/23.hmac_wipe_secret.3004168396
Short name T100
Test name
Test status
Simulation time 3668874711 ps
CPU time 62.7 seconds
Started Sep 09 07:30:52 PM UTC 24
Finished Sep 09 07:31:57 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004168396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3004168396
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/23.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/24.hmac_alert_test.4155557231
Short name T279
Test name
Test status
Simulation time 13014660 ps
CPU time 0.92 seconds
Started Sep 09 07:31:32 PM UTC 24
Finished Sep 09 07:31:34 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155557231 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.4155557231
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/24.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/24.hmac_back_pressure.4068336684
Short name T294
Test name
Test status
Simulation time 2582219559 ps
CPU time 88.46 seconds
Started Sep 09 07:31:01 PM UTC 24
Finished Sep 09 07:32:31 PM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068336684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.4068336684
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/24.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/24.hmac_burst_wr.3523564660
Short name T155
Test name
Test status
Simulation time 2274172701 ps
CPU time 37.34 seconds
Started Sep 09 07:31:15 PM UTC 24
Finished Sep 09 07:31:55 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523564660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3523564660
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/24.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/24.hmac_datapath_stress.3724802831
Short name T479
Test name
Test status
Simulation time 5574324930 ps
CPU time 986.69 seconds
Started Sep 09 07:31:05 PM UTC 24
Finished Sep 09 07:47:42 PM UTC 24
Peak memory 704812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724802831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3724802831
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/24.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/24.hmac_error.1703618062
Short name T283
Test name
Test status
Simulation time 3340767485 ps
CPU time 40.86 seconds
Started Sep 09 07:31:18 PM UTC 24
Finished Sep 09 07:32:01 PM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703618062 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1703618062
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/24.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/24.hmac_long_msg.18211600
Short name T278
Test name
Test status
Simulation time 5150973138 ps
CPU time 29.85 seconds
Started Sep 09 07:31:01 PM UTC 24
Finished Sep 09 07:31:32 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18211600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.18211600
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/24.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/24.hmac_smoke.3440483200
Short name T274
Test name
Test status
Simulation time 7589963407 ps
CPU time 13.05 seconds
Started Sep 09 07:31:01 PM UTC 24
Finished Sep 09 07:31:15 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440483200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3440483200
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/24.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/24.hmac_stress_all.4208594317
Short name T520
Test name
Test status
Simulation time 38111693270 ps
CPU time 2109.11 seconds
Started Sep 09 07:31:29 PM UTC 24
Finished Sep 09 08:07:01 PM UTC 24
Peak memory 768296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208594317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.4208594317
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/24.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/24.hmac_wipe_secret.3956297600
Short name T288
Test name
Test status
Simulation time 7145224818 ps
CPU time 44.64 seconds
Started Sep 09 07:31:23 PM UTC 24
Finished Sep 09 07:32:09 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956297600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3956297600
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/24.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/25.hmac_alert_test.3808467842
Short name T285
Test name
Test status
Simulation time 43883256 ps
CPU time 0.83 seconds
Started Sep 09 07:32:02 PM UTC 24
Finished Sep 09 07:32:04 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808467842 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3808467842
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/25.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/25.hmac_back_pressure.937600795
Short name T308
Test name
Test status
Simulation time 1570421694 ps
CPU time 118.48 seconds
Started Sep 09 07:31:50 PM UTC 24
Finished Sep 09 07:33:51 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937600795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.937600795
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/25.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/25.hmac_burst_wr.355447744
Short name T296
Test name
Test status
Simulation time 9249902074 ps
CPU time 35.29 seconds
Started Sep 09 07:31:56 PM UTC 24
Finished Sep 09 07:32:32 PM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355447744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.355447744
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/25.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/25.hmac_datapath_stress.2097769375
Short name T495
Test name
Test status
Simulation time 22008854484 ps
CPU time 1122.7 seconds
Started Sep 09 07:31:52 PM UTC 24
Finished Sep 09 07:50:48 PM UTC 24
Peak memory 747792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097769375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2097769375
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/25.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/25.hmac_error.3073746783
Short name T313
Test name
Test status
Simulation time 6509080344 ps
CPU time 131.53 seconds
Started Sep 09 07:31:58 PM UTC 24
Finished Sep 09 07:34:12 PM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073746783 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3073746783
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/25.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/25.hmac_long_msg.1983962947
Short name T297
Test name
Test status
Simulation time 2924793349 ps
CPU time 59.82 seconds
Started Sep 09 07:31:35 PM UTC 24
Finished Sep 09 07:32:37 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983962947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1983962947
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/25.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/25.hmac_smoke.3761768816
Short name T281
Test name
Test status
Simulation time 697723999 ps
CPU time 16.91 seconds
Started Sep 09 07:31:33 PM UTC 24
Finished Sep 09 07:31:52 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761768816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3761768816
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/25.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/25.hmac_stress_all.507983921
Short name T505
Test name
Test status
Simulation time 307562059614 ps
CPU time 1457.36 seconds
Started Sep 09 07:32:02 PM UTC 24
Finished Sep 09 07:56:36 PM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507983921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.507983921
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/25.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/25.hmac_wipe_secret.2035443462
Short name T101
Test name
Test status
Simulation time 4931653775 ps
CPU time 100.89 seconds
Started Sep 09 07:31:58 PM UTC 24
Finished Sep 09 07:33:41 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035443462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2035443462
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/25.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/26.hmac_alert_test.1464896112
Short name T293
Test name
Test status
Simulation time 34883322 ps
CPU time 0.85 seconds
Started Sep 09 07:32:26 PM UTC 24
Finished Sep 09 07:32:27 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464896112 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1464896112
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/26.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/26.hmac_back_pressure.2295228162
Short name T303
Test name
Test status
Simulation time 1300421132 ps
CPU time 49.12 seconds
Started Sep 09 07:32:08 PM UTC 24
Finished Sep 09 07:32:59 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295228162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2295228162
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/26.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/26.hmac_burst_wr.4043031109
Short name T291
Test name
Test status
Simulation time 451751287 ps
CPU time 7.81 seconds
Started Sep 09 07:32:13 PM UTC 24
Finished Sep 09 07:32:21 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043031109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.4043031109
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/26.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/26.hmac_datapath_stress.1042017769
Short name T423
Test name
Test status
Simulation time 11457853821 ps
CPU time 630.23 seconds
Started Sep 09 07:32:13 PM UTC 24
Finished Sep 09 07:42:49 PM UTC 24
Peak memory 753872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042017769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1042017769
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/26.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/26.hmac_error.1075500258
Short name T322
Test name
Test status
Simulation time 11297421374 ps
CPU time 172.62 seconds
Started Sep 09 07:32:15 PM UTC 24
Finished Sep 09 07:35:10 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075500258 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1075500258
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/26.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/26.hmac_long_msg.1117121125
Short name T290
Test name
Test status
Simulation time 571844286 ps
CPU time 10.94 seconds
Started Sep 09 07:32:04 PM UTC 24
Finished Sep 09 07:32:16 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117121125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1117121125
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/26.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/26.hmac_smoke.1401979061
Short name T286
Test name
Test status
Simulation time 469464639 ps
CPU time 3.66 seconds
Started Sep 09 07:32:03 PM UTC 24
Finished Sep 09 07:32:08 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401979061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1401979061
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/26.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/26.hmac_stress_all.3792401850
Short name T372
Test name
Test status
Simulation time 79472456054 ps
CPU time 389.49 seconds
Started Sep 09 07:32:22 PM UTC 24
Finished Sep 09 07:38:57 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792401850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3792401850
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/26.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/26.hmac_wipe_secret.2934686315
Short name T301
Test name
Test status
Simulation time 663537822 ps
CPU time 39.66 seconds
Started Sep 09 07:32:17 PM UTC 24
Finished Sep 09 07:32:58 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934686315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2934686315
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/26.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/27.hmac_alert_test.4116834533
Short name T304
Test name
Test status
Simulation time 25384986 ps
CPU time 0.93 seconds
Started Sep 09 07:32:59 PM UTC 24
Finished Sep 09 07:33:01 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116834533 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.4116834533
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/27.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/27.hmac_back_pressure.3334733672
Short name T315
Test name
Test status
Simulation time 1455496745 ps
CPU time 98.38 seconds
Started Sep 09 07:32:35 PM UTC 24
Finished Sep 09 07:34:16 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334733672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3334733672
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/27.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/27.hmac_burst_wr.1299149219
Short name T153
Test name
Test status
Simulation time 1276787197 ps
CPU time 33.72 seconds
Started Sep 09 07:32:38 PM UTC 24
Finished Sep 09 07:33:13 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299149219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1299149219
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/27.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/27.hmac_datapath_stress.1784395285
Short name T492
Test name
Test status
Simulation time 6198781556 ps
CPU time 1055.79 seconds
Started Sep 09 07:32:35 PM UTC 24
Finished Sep 09 07:50:22 PM UTC 24
Peak memory 678172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784395285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1784395285
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/27.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/27.hmac_error.966096362
Short name T336
Test name
Test status
Simulation time 15972420703 ps
CPU time 200.09 seconds
Started Sep 09 07:32:40 PM UTC 24
Finished Sep 09 07:36:03 PM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966096362 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.966096362
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/27.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/27.hmac_long_msg.1902799435
Short name T326
Test name
Test status
Simulation time 13521327500 ps
CPU time 189.74 seconds
Started Sep 09 07:32:35 PM UTC 24
Finished Sep 09 07:35:48 PM UTC 24
Peak memory 215960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902799435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1902799435
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/27.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/27.hmac_smoke.131956275
Short name T298
Test name
Test status
Simulation time 2878831604 ps
CPU time 9.3 seconds
Started Sep 09 07:32:29 PM UTC 24
Finished Sep 09 07:32:39 PM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131956275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.131956275
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/27.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/27.hmac_stress_all.909181705
Short name T87
Test name
Test status
Simulation time 124346595076 ps
CPU time 528.33 seconds
Started Sep 09 07:32:51 PM UTC 24
Finished Sep 09 07:41:47 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909181705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.909181705
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/27.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/27.hmac_wipe_secret.1013671954
Short name T307
Test name
Test status
Simulation time 985705044 ps
CPU time 57.18 seconds
Started Sep 09 07:32:43 PM UTC 24
Finished Sep 09 07:33:42 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013671954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1013671954
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/27.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/28.hmac_alert_test.1436984837
Short name T310
Test name
Test status
Simulation time 29501828 ps
CPU time 0.82 seconds
Started Sep 09 07:33:53 PM UTC 24
Finished Sep 09 07:33:54 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436984837 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1436984837
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/28.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/28.hmac_back_pressure.2372390687
Short name T312
Test name
Test status
Simulation time 9671835822 ps
CPU time 65.22 seconds
Started Sep 09 07:33:02 PM UTC 24
Finished Sep 09 07:34:09 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372390687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2372390687
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/28.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/28.hmac_burst_wr.3385394868
Short name T154
Test name
Test status
Simulation time 7306427257 ps
CPU time 44.03 seconds
Started Sep 09 07:33:19 PM UTC 24
Finished Sep 09 07:34:04 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385394868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3385394868
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/28.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/28.hmac_datapath_stress.1406794222
Short name T497
Test name
Test status
Simulation time 10457370133 ps
CPU time 1190.4 seconds
Started Sep 09 07:33:13 PM UTC 24
Finished Sep 09 07:53:18 PM UTC 24
Peak memory 719136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406794222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1406794222
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/28.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/28.hmac_error.769759509
Short name T314
Test name
Test status
Simulation time 9023797297 ps
CPU time 36.56 seconds
Started Sep 09 07:33:37 PM UTC 24
Finished Sep 09 07:34:15 PM UTC 24
Peak memory 207176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769759509 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.769759509
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/28.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/28.hmac_long_msg.4193508655
Short name T329
Test name
Test status
Simulation time 17046567435 ps
CPU time 167.22 seconds
Started Sep 09 07:33:02 PM UTC 24
Finished Sep 09 07:35:53 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193508655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.4193508655
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/28.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/28.hmac_smoke.383618264
Short name T305
Test name
Test status
Simulation time 887463963 ps
CPU time 13.42 seconds
Started Sep 09 07:33:02 PM UTC 24
Finished Sep 09 07:33:17 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383618264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.383618264
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/28.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/28.hmac_stress_all.650574687
Short name T517
Test name
Test status
Simulation time 364326641322 ps
CPU time 1949.13 seconds
Started Sep 09 07:33:43 PM UTC 24
Finished Sep 09 08:06:33 PM UTC 24
Peak memory 747952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650574687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.650574687
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/28.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/28.hmac_wipe_secret.4070010288
Short name T309
Test name
Test status
Simulation time 3516118188 ps
CPU time 7.9 seconds
Started Sep 09 07:33:43 PM UTC 24
Finished Sep 09 07:33:53 PM UTC 24
Peak memory 207120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070010288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.4070010288
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/28.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/29.hmac_alert_test.1794024204
Short name T316
Test name
Test status
Simulation time 32284005 ps
CPU time 0.85 seconds
Started Sep 09 07:34:20 PM UTC 24
Finished Sep 09 07:34:21 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794024204 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1794024204
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/29.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/29.hmac_back_pressure.2891989690
Short name T327
Test name
Test status
Simulation time 1758186455 ps
CPU time 102.17 seconds
Started Sep 09 07:34:06 PM UTC 24
Finished Sep 09 07:35:50 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891989690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2891989690
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/29.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/29.hmac_burst_wr.2704377364
Short name T319
Test name
Test status
Simulation time 5319353017 ps
CPU time 32.94 seconds
Started Sep 09 07:34:11 PM UTC 24
Finished Sep 09 07:34:45 PM UTC 24
Peak memory 215752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704377364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2704377364
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/29.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/29.hmac_datapath_stress.2660865675
Short name T502
Test name
Test status
Simulation time 7636994906 ps
CPU time 1293.81 seconds
Started Sep 09 07:34:06 PM UTC 24
Finished Sep 09 07:55:54 PM UTC 24
Peak memory 760032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660865675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2660865675
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/29.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/29.hmac_error.3439833922
Short name T356
Test name
Test status
Simulation time 55104901188 ps
CPU time 202.93 seconds
Started Sep 09 07:34:13 PM UTC 24
Finished Sep 09 07:37:40 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439833922 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3439833922
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/29.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/29.hmac_long_msg.1729259160
Short name T330
Test name
Test status
Simulation time 15700174220 ps
CPU time 114.84 seconds
Started Sep 09 07:33:56 PM UTC 24
Finished Sep 09 07:35:53 PM UTC 24
Peak memory 207556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729259160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1729259160
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/29.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/29.hmac_smoke.14685970
Short name T311
Test name
Test status
Simulation time 1702799823 ps
CPU time 8.61 seconds
Started Sep 09 07:33:55 PM UTC 24
Finished Sep 09 07:34:04 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14685970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 29.hmac_smoke.14685970
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/29.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/29.hmac_stress_all.1267322415
Short name T325
Test name
Test status
Simulation time 35088093238 ps
CPU time 78.11 seconds
Started Sep 09 07:34:19 PM UTC 24
Finished Sep 09 07:35:40 PM UTC 24
Peak memory 215692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267322415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1267322415
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/29.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/29.hmac_wipe_secret.2794708511
Short name T321
Test name
Test status
Simulation time 724512530 ps
CPU time 49.81 seconds
Started Sep 09 07:34:16 PM UTC 24
Finished Sep 09 07:35:07 PM UTC 24
Peak memory 207440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794708511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2794708511
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/29.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/3.hmac_alert_test.1624650335
Short name T91
Test name
Test status
Simulation time 38687926 ps
CPU time 0.83 seconds
Started Sep 09 07:20:35 PM UTC 24
Finished Sep 09 07:20:36 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624650335 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1624650335
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/3.hmac_back_pressure.4283332345
Short name T20
Test name
Test status
Simulation time 25004804623 ps
CPU time 106.37 seconds
Started Sep 09 07:20:12 PM UTC 24
Finished Sep 09 07:22:00 PM UTC 24
Peak memory 216012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283332345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.4283332345
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/3.hmac_datapath_stress.3237552389
Short name T82
Test name
Test status
Simulation time 2748489982 ps
CPU time 92.11 seconds
Started Sep 09 07:20:13 PM UTC 24
Finished Sep 09 07:21:47 PM UTC 24
Peak memory 626532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237552389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3237552389
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/3.hmac_error.3809137879
Short name T59
Test name
Test status
Simulation time 5018950593 ps
CPU time 89.25 seconds
Started Sep 09 07:20:13 PM UTC 24
Finished Sep 09 07:21:44 PM UTC 24
Peak memory 207432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809137879 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3809137879
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/3.hmac_long_msg.2430039880
Short name T149
Test name
Test status
Simulation time 21621657851 ps
CPU time 99.58 seconds
Started Sep 09 07:20:12 PM UTC 24
Finished Sep 09 07:21:53 PM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430039880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2430039880
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/3.hmac_sec_cm.2748896473
Short name T66
Test name
Test status
Simulation time 101764449 ps
CPU time 1.2 seconds
Started Sep 09 07:20:31 PM UTC 24
Finished Sep 09 07:20:34 PM UTC 24
Peak memory 235564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748896473 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2748896473
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/3.hmac_smoke.490140160
Short name T18
Test name
Test status
Simulation time 1264633171 ps
CPU time 6.29 seconds
Started Sep 09 07:20:11 PM UTC 24
Finished Sep 09 07:20:18 PM UTC 24
Peak memory 207164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490140160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.490140160
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/3.hmac_stress_all.1190610285
Short name T158
Test name
Test status
Simulation time 78472877546 ps
CPU time 853.38 seconds
Started Sep 09 07:20:30 PM UTC 24
Finished Sep 09 07:34:54 PM UTC 24
Peak memory 743972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190610285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1190610285
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/3.hmac_stress_all_with_rand_reset.1864391748
Short name T11
Test name
Test status
Simulation time 10049750033 ps
CPU time 76.54 seconds
Started Sep 09 07:20:30 PM UTC 24
Finished Sep 09 07:21:49 PM UTC 24
Peak memory 215816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18643917
48 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1864391748
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/3.hmac_test_hmac256_vectors.1264871595
Short name T165
Test name
Test status
Simulation time 8925509462 ps
CPU time 56.01 seconds
Started Sep 09 07:20:18 PM UTC 24
Finished Sep 09 07:21:16 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264871595 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.1264871595
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/3.hmac_test_hmac384_vectors.2692519795
Short name T168
Test name
Test status
Simulation time 2252924383 ps
CPU time 93.91 seconds
Started Sep 09 07:20:19 PM UTC 24
Finished Sep 09 07:21:55 PM UTC 24
Peak memory 207592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692519795 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.2692519795
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/3.hmac_test_hmac512_vectors.1043289681
Short name T81
Test name
Test status
Simulation time 3876671314 ps
CPU time 75.53 seconds
Started Sep 09 07:20:28 PM UTC 24
Finished Sep 09 07:21:45 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043289681 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.1043289681
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/3.hmac_test_sha256_vectors.1683066698
Short name T295
Test name
Test status
Simulation time 44000399971 ps
CPU time 727.39 seconds
Started Sep 09 07:20:15 PM UTC 24
Finished Sep 09 07:32:31 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683066698 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.1683066698
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/3.hmac_test_sha384_vectors.4082479008
Short name T507
Test name
Test status
Simulation time 39714371181 ps
CPU time 2217.96 seconds
Started Sep 09 07:20:15 PM UTC 24
Finished Sep 09 07:57:38 PM UTC 24
Peak memory 223628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082479008 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.4082479008
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/3.hmac_test_sha512_vectors.3838574554
Short name T39
Test name
Test status
Simulation time 581756505071 ps
CPU time 2386.44 seconds
Started Sep 09 07:20:16 PM UTC 24
Finished Sep 09 08:00:28 PM UTC 24
Peak memory 223600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838574554 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.3838574554
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/3.hmac_wipe_secret.927182503
Short name T23
Test name
Test status
Simulation time 3688375917 ps
CPU time 90.82 seconds
Started Sep 09 07:20:15 PM UTC 24
Finished Sep 09 07:21:47 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927182503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.927182503
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/3.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/30.hmac_alert_test.2126881889
Short name T323
Test name
Test status
Simulation time 34276719 ps
CPU time 0.85 seconds
Started Sep 09 07:35:12 PM UTC 24
Finished Sep 09 07:35:14 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126881889 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2126881889
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/30.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/30.hmac_back_pressure.3171109633
Short name T328
Test name
Test status
Simulation time 6560471917 ps
CPU time 66.6 seconds
Started Sep 09 07:34:42 PM UTC 24
Finished Sep 09 07:35:50 PM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171109633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3171109633
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/30.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/30.hmac_burst_wr.371661777
Short name T320
Test name
Test status
Simulation time 3802326690 ps
CPU time 18.63 seconds
Started Sep 09 07:34:47 PM UTC 24
Finished Sep 09 07:35:07 PM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371661777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.371661777
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/30.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/30.hmac_datapath_stress.2509156692
Short name T374
Test name
Test status
Simulation time 1420054566 ps
CPU time 258.38 seconds
Started Sep 09 07:34:46 PM UTC 24
Finished Sep 09 07:39:08 PM UTC 24
Peak memory 647584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509156692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2509156692
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/30.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/30.hmac_error.1931178504
Short name T340
Test name
Test status
Simulation time 2179726633 ps
CPU time 84.3 seconds
Started Sep 09 07:34:58 PM UTC 24
Finished Sep 09 07:36:25 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931178504 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1931178504
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/30.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/30.hmac_long_msg.2165891416
Short name T346
Test name
Test status
Simulation time 14414078510 ps
CPU time 130.98 seconds
Started Sep 09 07:34:41 PM UTC 24
Finished Sep 09 07:36:54 PM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165891416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2165891416
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/30.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/30.hmac_smoke.3449750920
Short name T317
Test name
Test status
Simulation time 2416769065 ps
CPU time 15.93 seconds
Started Sep 09 07:34:24 PM UTC 24
Finished Sep 09 07:34:41 PM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449750920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3449750920
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/30.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/30.hmac_stress_all.2750792314
Short name T530
Test name
Test status
Simulation time 240937747982 ps
CPU time 3516.44 seconds
Started Sep 09 07:35:09 PM UTC 24
Finished Sep 09 08:34:23 PM UTC 24
Peak memory 829632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750792314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2750792314
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/30.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/30.hmac_wipe_secret.988662536
Short name T333
Test name
Test status
Simulation time 22924532267 ps
CPU time 48.44 seconds
Started Sep 09 07:35:07 PM UTC 24
Finished Sep 09 07:35:57 PM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988662536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.988662536
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/30.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/31.hmac_alert_test.2953991298
Short name T331
Test name
Test status
Simulation time 23487435 ps
CPU time 0.81 seconds
Started Sep 09 07:35:54 PM UTC 24
Finished Sep 09 07:35:56 PM UTC 24
Peak memory 203560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953991298 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2953991298
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/31.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/31.hmac_back_pressure.2782610652
Short name T332
Test name
Test status
Simulation time 920254519 ps
CPU time 36.47 seconds
Started Sep 09 07:35:19 PM UTC 24
Finished Sep 09 07:35:56 PM UTC 24
Peak memory 215892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782610652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2782610652
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/31.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/31.hmac_burst_wr.1827784248
Short name T345
Test name
Test status
Simulation time 5330842492 ps
CPU time 67.61 seconds
Started Sep 09 07:35:41 PM UTC 24
Finished Sep 09 07:36:50 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827784248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1827784248
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/31.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/31.hmac_datapath_stress.1456751474
Short name T496
Test name
Test status
Simulation time 19984851592 ps
CPU time 994.41 seconds
Started Sep 09 07:35:22 PM UTC 24
Finished Sep 09 07:52:08 PM UTC 24
Peak memory 741656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456751474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1456751474
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/31.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/31.hmac_error.1323180713
Short name T338
Test name
Test status
Simulation time 1620029982 ps
CPU time 25.15 seconds
Started Sep 09 07:35:50 PM UTC 24
Finished Sep 09 07:36:17 PM UTC 24
Peak memory 207176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323180713 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1323180713
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/31.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/31.hmac_long_msg.1197075387
Short name T360
Test name
Test status
Simulation time 4868170532 ps
CPU time 159.3 seconds
Started Sep 09 07:35:19 PM UTC 24
Finished Sep 09 07:38:00 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197075387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1197075387
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/31.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/31.hmac_smoke.785860381
Short name T324
Test name
Test status
Simulation time 69822443 ps
CPU time 1.54 seconds
Started Sep 09 07:35:15 PM UTC 24
Finished Sep 09 07:35:17 PM UTC 24
Peak memory 206228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785860381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.785860381
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/31.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/31.hmac_stress_all.1731592411
Short name T157
Test name
Test status
Simulation time 4960718713 ps
CPU time 130.97 seconds
Started Sep 09 07:35:54 PM UTC 24
Finished Sep 09 07:38:07 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731592411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1731592411
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/31.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/31.hmac_wipe_secret.488600748
Short name T102
Test name
Test status
Simulation time 5150370219 ps
CPU time 126.8 seconds
Started Sep 09 07:35:54 PM UTC 24
Finished Sep 09 07:38:03 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488600748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.488600748
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/31.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/32.hmac_alert_test.117002482
Short name T339
Test name
Test status
Simulation time 27006926 ps
CPU time 0.83 seconds
Started Sep 09 07:36:16 PM UTC 24
Finished Sep 09 07:36:18 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117002482 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.117002482
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/32.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/32.hmac_back_pressure.2022348181
Short name T353
Test name
Test status
Simulation time 4167760363 ps
CPU time 81.51 seconds
Started Sep 09 07:35:57 PM UTC 24
Finished Sep 09 07:37:21 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022348181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2022348181
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/32.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/32.hmac_burst_wr.3044227951
Short name T337
Test name
Test status
Simulation time 800714929 ps
CPU time 15.25 seconds
Started Sep 09 07:35:59 PM UTC 24
Finished Sep 09 07:36:15 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044227951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3044227951
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/32.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/32.hmac_datapath_stress.1387796447
Short name T466
Test name
Test status
Simulation time 74709620107 ps
CPU time 655.62 seconds
Started Sep 09 07:35:57 PM UTC 24
Finished Sep 09 07:46:59 PM UTC 24
Peak memory 678164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387796447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1387796447
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/32.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/32.hmac_error.3026454110
Short name T369
Test name
Test status
Simulation time 39318384859 ps
CPU time 164.07 seconds
Started Sep 09 07:36:02 PM UTC 24
Finished Sep 09 07:38:48 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026454110 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3026454110
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/32.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/32.hmac_long_msg.826926110
Short name T334
Test name
Test status
Simulation time 418830890 ps
CPU time 2.11 seconds
Started Sep 09 07:35:57 PM UTC 24
Finished Sep 09 07:36:01 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826926110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.826926110
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/32.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/32.hmac_smoke.1356361227
Short name T335
Test name
Test status
Simulation time 204924853 ps
CPU time 3.63 seconds
Started Sep 09 07:35:57 PM UTC 24
Finished Sep 09 07:36:02 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356361227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1356361227
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/32.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/32.hmac_stress_all.2567047928
Short name T532
Test name
Test status
Simulation time 517358876805 ps
CPU time 6085.01 seconds
Started Sep 09 07:36:05 PM UTC 24
Finished Sep 09 09:18:28 PM UTC 24
Peak memory 926020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567047928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2567047928
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/32.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/32.hmac_wipe_secret.399656756
Short name T349
Test name
Test status
Simulation time 9035163947 ps
CPU time 60.02 seconds
Started Sep 09 07:36:03 PM UTC 24
Finished Sep 09 07:37:04 PM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399656756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.399656756
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/32.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/33.hmac_alert_test.3422142308
Short name T348
Test name
Test status
Simulation time 22218504 ps
CPU time 0.86 seconds
Started Sep 09 07:36:56 PM UTC 24
Finished Sep 09 07:36:58 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422142308 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3422142308
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/33.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/33.hmac_back_pressure.1787959502
Short name T344
Test name
Test status
Simulation time 424576092 ps
CPU time 17.7 seconds
Started Sep 09 07:36:26 PM UTC 24
Finished Sep 09 07:36:44 PM UTC 24
Peak memory 207176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787959502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1787959502
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/33.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/33.hmac_burst_wr.2697219696
Short name T343
Test name
Test status
Simulation time 486636084 ps
CPU time 4.07 seconds
Started Sep 09 07:36:29 PM UTC 24
Finished Sep 09 07:36:34 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697219696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2697219696
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/33.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/33.hmac_datapath_stress.205513262
Short name T342
Test name
Test status
Simulation time 21457900 ps
CPU time 1.1 seconds
Started Sep 09 07:36:26 PM UTC 24
Finished Sep 09 07:36:28 PM UTC 24
Peak memory 205632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205513262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.205513262
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/33.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/33.hmac_error.2185142580
Short name T363
Test name
Test status
Simulation time 9523283143 ps
CPU time 97.9 seconds
Started Sep 09 07:36:35 PM UTC 24
Finished Sep 09 07:38:15 PM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185142580 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2185142580
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/33.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/33.hmac_long_msg.1056332702
Short name T347
Test name
Test status
Simulation time 6609853153 ps
CPU time 35.77 seconds
Started Sep 09 07:36:18 PM UTC 24
Finished Sep 09 07:36:55 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056332702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1056332702
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/33.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/33.hmac_smoke.1001727190
Short name T341
Test name
Test status
Simulation time 209784159 ps
CPU time 6.06 seconds
Started Sep 09 07:36:18 PM UTC 24
Finished Sep 09 07:36:25 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001727190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1001727190
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/33.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/33.hmac_stress_all.3470909464
Short name T105
Test name
Test status
Simulation time 4982633863 ps
CPU time 305.44 seconds
Started Sep 09 07:36:51 PM UTC 24
Finished Sep 09 07:42:02 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470909464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3470909464
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/33.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/33.hmac_wipe_secret.2523350121
Short name T103
Test name
Test status
Simulation time 8826746860 ps
CPU time 110.38 seconds
Started Sep 09 07:36:45 PM UTC 24
Finished Sep 09 07:38:38 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523350121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2523350121
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/33.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/34.hmac_alert_test.3756450692
Short name T355
Test name
Test status
Simulation time 14129625 ps
CPU time 0.92 seconds
Started Sep 09 07:37:32 PM UTC 24
Finished Sep 09 07:37:34 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756450692 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3756450692
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/34.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/34.hmac_back_pressure.570841331
Short name T381
Test name
Test status
Simulation time 2622480156 ps
CPU time 133.75 seconds
Started Sep 09 07:37:07 PM UTC 24
Finished Sep 09 07:39:24 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570841331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.570841331
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/34.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/34.hmac_burst_wr.1285847464
Short name T156
Test name
Test status
Simulation time 615059171 ps
CPU time 46.06 seconds
Started Sep 09 07:37:13 PM UTC 24
Finished Sep 09 07:38:00 PM UTC 24
Peak memory 215672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285847464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1285847464
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/34.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/34.hmac_datapath_stress.2794861649
Short name T396
Test name
Test status
Simulation time 11188141744 ps
CPU time 219.77 seconds
Started Sep 09 07:37:08 PM UTC 24
Finished Sep 09 07:40:52 PM UTC 24
Peak memory 483608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794861649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2794861649
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/34.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/34.hmac_error.2181023356
Short name T393
Test name
Test status
Simulation time 6399352369 ps
CPU time 188.34 seconds
Started Sep 09 07:37:14 PM UTC 24
Finished Sep 09 07:40:25 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181023356 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2181023356
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/34.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/34.hmac_long_msg.2079943757
Short name T351
Test name
Test status
Simulation time 2108795503 ps
CPU time 12.25 seconds
Started Sep 09 07:36:59 PM UTC 24
Finished Sep 09 07:37:13 PM UTC 24
Peak memory 207200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079943757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2079943757
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/34.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/34.hmac_smoke.1282210871
Short name T350
Test name
Test status
Simulation time 7569714979 ps
CPU time 14.07 seconds
Started Sep 09 07:36:56 PM UTC 24
Finished Sep 09 07:37:12 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282210871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1282210871
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/34.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/34.hmac_stress_all.1810150326
Short name T415
Test name
Test status
Simulation time 7986136815 ps
CPU time 273.84 seconds
Started Sep 09 07:37:22 PM UTC 24
Finished Sep 09 07:42:00 PM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810150326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1810150326
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/34.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/34.hmac_wipe_secret.4291976633
Short name T371
Test name
Test status
Simulation time 18466520921 ps
CPU time 90.72 seconds
Started Sep 09 07:37:19 PM UTC 24
Finished Sep 09 07:38:52 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291976633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.4291976633
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/34.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/35.hmac_alert_test.2701115143
Short name T362
Test name
Test status
Simulation time 64382083 ps
CPU time 0.9 seconds
Started Sep 09 07:38:09 PM UTC 24
Finished Sep 09 07:38:11 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701115143 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2701115143
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/35.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/35.hmac_back_pressure.3976533521
Short name T361
Test name
Test status
Simulation time 970886296 ps
CPU time 26.72 seconds
Started Sep 09 07:37:42 PM UTC 24
Finished Sep 09 07:38:10 PM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976533521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3976533521
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/35.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/35.hmac_burst_wr.314491051
Short name T367
Test name
Test status
Simulation time 659441868 ps
CPU time 36.68 seconds
Started Sep 09 07:38:00 PM UTC 24
Finished Sep 09 07:38:39 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314491051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.314491051
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/35.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/35.hmac_datapath_stress.1563075441
Short name T498
Test name
Test status
Simulation time 25175866586 ps
CPU time 976.46 seconds
Started Sep 09 07:37:56 PM UTC 24
Finished Sep 09 07:54:23 PM UTC 24
Peak memory 762336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563075441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1563075441
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/35.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/35.hmac_error.2564831343
Short name T383
Test name
Test status
Simulation time 15687932476 ps
CPU time 85.51 seconds
Started Sep 09 07:38:02 PM UTC 24
Finished Sep 09 07:39:30 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564831343 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2564831343
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/35.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/35.hmac_long_msg.3744651475
Short name T376
Test name
Test status
Simulation time 17235053338 ps
CPU time 86.42 seconds
Started Sep 09 07:37:42 PM UTC 24
Finished Sep 09 07:39:10 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744651475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3744651475
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/35.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/35.hmac_smoke.313084964
Short name T357
Test name
Test status
Simulation time 865413393 ps
CPU time 4.33 seconds
Started Sep 09 07:37:35 PM UTC 24
Finished Sep 09 07:37:40 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313084964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.313084964
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/35.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/35.hmac_stress_all.2730819057
Short name T89
Test name
Test status
Simulation time 163197513286 ps
CPU time 642.85 seconds
Started Sep 09 07:38:05 PM UTC 24
Finished Sep 09 07:48:56 PM UTC 24
Peak memory 246128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730819057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2730819057
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/35.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/35.hmac_wipe_secret.2177762482
Short name T385
Test name
Test status
Simulation time 13704325249 ps
CPU time 117.53 seconds
Started Sep 09 07:38:02 PM UTC 24
Finished Sep 09 07:40:02 PM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177762482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2177762482
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/35.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/36.hmac_alert_test.1024565089
Short name T370
Test name
Test status
Simulation time 33607436 ps
CPU time 0.87 seconds
Started Sep 09 07:38:48 PM UTC 24
Finished Sep 09 07:38:50 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024565089 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1024565089
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/36.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/36.hmac_back_pressure.1389090157
Short name T392
Test name
Test status
Simulation time 10934358446 ps
CPU time 126.41 seconds
Started Sep 09 07:38:16 PM UTC 24
Finished Sep 09 07:40:25 PM UTC 24
Peak memory 215752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389090157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1389090157
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/36.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/36.hmac_burst_wr.1674314030
Short name T368
Test name
Test status
Simulation time 7738097459 ps
CPU time 22.4 seconds
Started Sep 09 07:38:22 PM UTC 24
Finished Sep 09 07:38:47 PM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674314030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1674314030
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/36.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/36.hmac_datapath_stress.1206046310
Short name T444
Test name
Test status
Simulation time 11937340189 ps
CPU time 400.36 seconds
Started Sep 09 07:38:20 PM UTC 24
Finished Sep 09 07:45:05 PM UTC 24
Peak memory 536864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206046310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1206046310
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/36.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/36.hmac_error.200519541
Short name T379
Test name
Test status
Simulation time 8106249614 ps
CPU time 47.54 seconds
Started Sep 09 07:38:29 PM UTC 24
Finished Sep 09 07:39:19 PM UTC 24
Peak memory 207120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200519541 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.200519541
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/36.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/36.hmac_long_msg.3039373751
Short name T365
Test name
Test status
Simulation time 3162387963 ps
CPU time 8.93 seconds
Started Sep 09 07:38:12 PM UTC 24
Finished Sep 09 07:38:21 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039373751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3039373751
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/36.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/36.hmac_smoke.2403359188
Short name T366
Test name
Test status
Simulation time 1238269101 ps
CPU time 17.24 seconds
Started Sep 09 07:38:10 PM UTC 24
Finished Sep 09 07:38:29 PM UTC 24
Peak memory 207200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403359188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2403359188
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/36.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/36.hmac_stress_all.3146217535
Short name T386
Test name
Test status
Simulation time 4244659508 ps
CPU time 85.14 seconds
Started Sep 09 07:38:40 PM UTC 24
Finished Sep 09 07:40:08 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146217535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3146217535
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/36.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/36.hmac_wipe_secret.589169486
Short name T389
Test name
Test status
Simulation time 17421270756 ps
CPU time 94.34 seconds
Started Sep 09 07:38:39 PM UTC 24
Finished Sep 09 07:40:16 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589169486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.589169486
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/36.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/37.hmac_alert_test.1394045720
Short name T378
Test name
Test status
Simulation time 13475536 ps
CPU time 0.88 seconds
Started Sep 09 07:39:11 PM UTC 24
Finished Sep 09 07:39:13 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394045720 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1394045720
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/37.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/37.hmac_back_pressure.1438987973
Short name T377
Test name
Test status
Simulation time 208008411 ps
CPU time 15.54 seconds
Started Sep 09 07:38:54 PM UTC 24
Finished Sep 09 07:39:10 PM UTC 24
Peak memory 207160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438987973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1438987973
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/37.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/37.hmac_burst_wr.3995469933
Short name T375
Test name
Test status
Simulation time 1822447385 ps
CPU time 5.45 seconds
Started Sep 09 07:39:03 PM UTC 24
Finished Sep 09 07:39:09 PM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995469933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3995469933
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/37.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/37.hmac_datapath_stress.449853626
Short name T451
Test name
Test status
Simulation time 21226786400 ps
CPU time 406.48 seconds
Started Sep 09 07:39:00 PM UTC 24
Finished Sep 09 07:45:51 PM UTC 24
Peak memory 704784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449853626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.449853626
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/37.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/37.hmac_error.4294907546
Short name T410
Test name
Test status
Simulation time 3988254995 ps
CPU time 143 seconds
Started Sep 09 07:39:09 PM UTC 24
Finished Sep 09 07:41:34 PM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294907546 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.4294907546
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/37.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/37.hmac_long_msg.1386161628
Short name T426
Test name
Test status
Simulation time 96394750579 ps
CPU time 251.85 seconds
Started Sep 09 07:38:51 PM UTC 24
Finished Sep 09 07:43:07 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386161628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1386161628
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/37.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/37.hmac_smoke.1311384303
Short name T373
Test name
Test status
Simulation time 428685042 ps
CPU time 10.53 seconds
Started Sep 09 07:38:50 PM UTC 24
Finished Sep 09 07:39:02 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311384303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1311384303
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/37.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/37.hmac_stress_all.4199566498
Short name T522
Test name
Test status
Simulation time 22697755895 ps
CPU time 1826.72 seconds
Started Sep 09 07:39:11 PM UTC 24
Finished Sep 09 08:09:58 PM UTC 24
Peak memory 749800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199566498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.4199566498
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/37.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/37.hmac_wipe_secret.2772760928
Short name T382
Test name
Test status
Simulation time 189812617 ps
CPU time 14.76 seconds
Started Sep 09 07:39:11 PM UTC 24
Finished Sep 09 07:39:27 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772760928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2772760928
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/37.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/38.hmac_alert_test.320822958
Short name T387
Test name
Test status
Simulation time 32756833 ps
CPU time 0.81 seconds
Started Sep 09 07:40:09 PM UTC 24
Finished Sep 09 07:40:11 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320822958 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.320822958
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/38.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/38.hmac_back_pressure.794696766
Short name T391
Test name
Test status
Simulation time 1894926785 ps
CPU time 58.21 seconds
Started Sep 09 07:39:22 PM UTC 24
Finished Sep 09 07:40:22 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794696766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.794696766
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/38.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/38.hmac_burst_wr.889858167
Short name T401
Test name
Test status
Simulation time 1208638816 ps
CPU time 93.81 seconds
Started Sep 09 07:39:28 PM UTC 24
Finished Sep 09 07:41:04 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889858167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.889858167
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/38.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/38.hmac_datapath_stress.2653896833
Short name T459
Test name
Test status
Simulation time 9039787738 ps
CPU time 415.33 seconds
Started Sep 09 07:39:26 PM UTC 24
Finished Sep 09 07:46:27 PM UTC 24
Peak memory 721120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653896833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2653896833
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/38.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/38.hmac_error.3207224890
Short name T416
Test name
Test status
Simulation time 202404994559 ps
CPU time 147.28 seconds
Started Sep 09 07:39:31 PM UTC 24
Finished Sep 09 07:42:01 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207224890 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3207224890
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/38.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/38.hmac_long_msg.2659687967
Short name T384
Test name
Test status
Simulation time 603827352 ps
CPU time 23.74 seconds
Started Sep 09 07:39:20 PM UTC 24
Finished Sep 09 07:39:45 PM UTC 24
Peak memory 207136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659687967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2659687967
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/38.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/38.hmac_smoke.2226593825
Short name T380
Test name
Test status
Simulation time 836976967 ps
CPU time 5.33 seconds
Started Sep 09 07:39:14 PM UTC 24
Finished Sep 09 07:39:21 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226593825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2226593825
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/38.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/38.hmac_stress_all.1023232325
Short name T500
Test name
Test status
Simulation time 40722785224 ps
CPU time 867.12 seconds
Started Sep 09 07:40:03 PM UTC 24
Finished Sep 09 07:54:42 PM UTC 24
Peak memory 688432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023232325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1023232325
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/38.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/38.hmac_wipe_secret.932374305
Short name T399
Test name
Test status
Simulation time 17219707921 ps
CPU time 72.06 seconds
Started Sep 09 07:39:46 PM UTC 24
Finished Sep 09 07:41:00 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932374305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.932374305
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/38.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/39.hmac_alert_test.1000831220
Short name T397
Test name
Test status
Simulation time 32160302 ps
CPU time 0.9 seconds
Started Sep 09 07:40:50 PM UTC 24
Finished Sep 09 07:40:52 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000831220 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1000831220
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/39.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/39.hmac_back_pressure.571207470
Short name T411
Test name
Test status
Simulation time 2134879302 ps
CPU time 78.85 seconds
Started Sep 09 07:40:17 PM UTC 24
Finished Sep 09 07:41:38 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571207470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.571207470
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/39.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/39.hmac_burst_wr.3949149693
Short name T394
Test name
Test status
Simulation time 1671225204 ps
CPU time 18.65 seconds
Started Sep 09 07:40:26 PM UTC 24
Finished Sep 09 07:40:46 PM UTC 24
Peak memory 206692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949149693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3949149693
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/39.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/39.hmac_datapath_stress.3196021129
Short name T499
Test name
Test status
Simulation time 17364177213 ps
CPU time 838.97 seconds
Started Sep 09 07:40:26 PM UTC 24
Finished Sep 09 07:54:35 PM UTC 24
Peak memory 712220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196021129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3196021129
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/39.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/39.hmac_error.3061374188
Short name T395
Test name
Test status
Simulation time 294130104 ps
CPU time 20.85 seconds
Started Sep 09 07:40:29 PM UTC 24
Finished Sep 09 07:40:51 PM UTC 24
Peak memory 207072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061374188 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3061374188
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/39.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/39.hmac_long_msg.674024443
Short name T398
Test name
Test status
Simulation time 13427375406 ps
CPU time 41.04 seconds
Started Sep 09 07:40:15 PM UTC 24
Finished Sep 09 07:40:57 PM UTC 24
Peak memory 215688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674024443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.674024443
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/39.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/39.hmac_smoke.4198063391
Short name T388
Test name
Test status
Simulation time 39248341 ps
CPU time 1.53 seconds
Started Sep 09 07:40:12 PM UTC 24
Finished Sep 09 07:40:14 PM UTC 24
Peak memory 206344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198063391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.4198063391
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/39.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/39.hmac_stress_all.4069423892
Short name T88
Test name
Test status
Simulation time 19066749094 ps
CPU time 313.53 seconds
Started Sep 09 07:40:47 PM UTC 24
Finished Sep 09 07:46:05 PM UTC 24
Peak memory 217808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069423892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.4069423892
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/39.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/39.hmac_wipe_secret.4181817518
Short name T104
Test name
Test status
Simulation time 931663903 ps
CPU time 19.23 seconds
Started Sep 09 07:40:29 PM UTC 24
Finished Sep 09 07:40:49 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181817518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.4181817518
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/39.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/4.hmac_alert_test.1414721691
Short name T166
Test name
Test status
Simulation time 21281220 ps
CPU time 0.91 seconds
Started Sep 09 07:21:15 PM UTC 24
Finished Sep 09 07:21:17 PM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414721691 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1414721691
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/4.hmac_back_pressure.839802940
Short name T150
Test name
Test status
Simulation time 7206268777 ps
CPU time 100.61 seconds
Started Sep 09 07:20:37 PM UTC 24
Finished Sep 09 07:22:20 PM UTC 24
Peak memory 215668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839802940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.839802940
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/4.hmac_burst_wr.3609649712
Short name T27
Test name
Test status
Simulation time 828533210 ps
CPU time 13.19 seconds
Started Sep 09 07:20:39 PM UTC 24
Finished Sep 09 07:20:54 PM UTC 24
Peak memory 207160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609649712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3609649712
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/4.hmac_datapath_stress.1716715545
Short name T390
Test name
Test status
Simulation time 25641701460 ps
CPU time 1169.07 seconds
Started Sep 09 07:20:39 PM UTC 24
Finished Sep 09 07:40:21 PM UTC 24
Peak memory 698668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716715545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1716715545
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/4.hmac_error.2766399490
Short name T188
Test name
Test status
Simulation time 161085509403 ps
CPU time 238 seconds
Started Sep 09 07:20:41 PM UTC 24
Finished Sep 09 07:24:42 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766399490 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2766399490
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/4.hmac_long_msg.3794781982
Short name T45
Test name
Test status
Simulation time 52293683044 ps
CPU time 122.84 seconds
Started Sep 09 07:20:37 PM UTC 24
Finished Sep 09 07:22:42 PM UTC 24
Peak memory 217868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794781982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3794781982
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/4.hmac_sec_cm.522745882
Short name T67
Test name
Test status
Simulation time 120069021 ps
CPU time 1.41 seconds
Started Sep 09 07:21:15 PM UTC 24
Finished Sep 09 07:21:18 PM UTC 24
Peak memory 235568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522745882 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.522745882
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/4.hmac_smoke.1060940545
Short name T53
Test name
Test status
Simulation time 1841335421 ps
CPU time 12.2 seconds
Started Sep 09 07:20:37 PM UTC 24
Finished Sep 09 07:20:50 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060940545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1060940545
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/4.hmac_stress_all.1569262704
Short name T354
Test name
Test status
Simulation time 123538602495 ps
CPU time 965.24 seconds
Started Sep 09 07:21:09 PM UTC 24
Finished Sep 09 07:37:26 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569262704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1569262704
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/4.hmac_test_hmac256_vectors.765189769
Short name T79
Test name
Test status
Simulation time 3353947154 ps
CPU time 43.51 seconds
Started Sep 09 07:20:54 PM UTC 24
Finished Sep 09 07:21:39 PM UTC 24
Peak memory 207340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765189769 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.765189769
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/4.hmac_test_hmac384_vectors.85684354
Short name T44
Test name
Test status
Simulation time 13347038564 ps
CPU time 99.48 seconds
Started Sep 09 07:20:58 PM UTC 24
Finished Sep 09 07:22:40 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85684354 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.85684354
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/4.hmac_test_hmac512_vectors.2294847812
Short name T170
Test name
Test status
Simulation time 2171742653 ps
CPU time 76.12 seconds
Started Sep 09 07:21:01 PM UTC 24
Finished Sep 09 07:22:19 PM UTC 24
Peak memory 207344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294847812 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.2294847812
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/4.hmac_test_sha256_vectors.1396868465
Short name T148
Test name
Test status
Simulation time 32308114748 ps
CPU time 565.49 seconds
Started Sep 09 07:20:51 PM UTC 24
Finished Sep 09 07:30:23 PM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396868465 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1396868465
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/4.hmac_test_sha384_vectors.443926701
Short name T513
Test name
Test status
Simulation time 262891155012 ps
CPU time 2566.89 seconds
Started Sep 09 07:20:51 PM UTC 24
Finished Sep 09 08:04:07 PM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443926701 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.443926701
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/4.hmac_test_sha512_vectors.480056442
Short name T525
Test name
Test status
Simulation time 915580079030 ps
CPU time 3116.55 seconds
Started Sep 09 07:20:52 PM UTC 24
Finished Sep 09 08:13:25 PM UTC 24
Peak memory 221244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480056442 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.480056442
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/4.hmac_wipe_secret.2193885859
Short name T52
Test name
Test status
Simulation time 31926091982 ps
CPU time 30.76 seconds
Started Sep 09 07:20:45 PM UTC 24
Finished Sep 09 07:21:18 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193885859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2193885859
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/40.hmac_alert_test.2212341789
Short name T404
Test name
Test status
Simulation time 13881675 ps
CPU time 0.88 seconds
Started Sep 09 07:41:08 PM UTC 24
Finished Sep 09 07:41:10 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212341789 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2212341789
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/40.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/40.hmac_back_pressure.3705158335
Short name T413
Test name
Test status
Simulation time 1112799688 ps
CPU time 55.37 seconds
Started Sep 09 07:40:53 PM UTC 24
Finished Sep 09 07:41:50 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705158335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3705158335
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/40.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/40.hmac_burst_wr.3297546115
Short name T408
Test name
Test status
Simulation time 5851423827 ps
CPU time 27.91 seconds
Started Sep 09 07:41:02 PM UTC 24
Finished Sep 09 07:41:31 PM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297546115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3297546115
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/40.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/40.hmac_datapath_stress.2388382859
Short name T400
Test name
Test status
Simulation time 176444363 ps
CPU time 1.03 seconds
Started Sep 09 07:40:58 PM UTC 24
Finished Sep 09 07:41:00 PM UTC 24
Peak memory 205860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388382859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2388382859
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/40.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/40.hmac_error.284746809
Short name T409
Test name
Test status
Simulation time 1803680965 ps
CPU time 30.7 seconds
Started Sep 09 07:41:02 PM UTC 24
Finished Sep 09 07:41:34 PM UTC 24
Peak memory 207176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284746809 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.284746809
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/40.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/40.hmac_long_msg.3248035133
Short name T402
Test name
Test status
Simulation time 1289865279 ps
CPU time 13.06 seconds
Started Sep 09 07:40:53 PM UTC 24
Finished Sep 09 07:41:07 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248035133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3248035133
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/40.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/40.hmac_smoke.2320313792
Short name T403
Test name
Test status
Simulation time 826701215 ps
CPU time 13.17 seconds
Started Sep 09 07:40:53 PM UTC 24
Finished Sep 09 07:41:07 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320313792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2320313792
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/40.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/40.hmac_stress_all.2292416960
Short name T510
Test name
Test status
Simulation time 104387455236 ps
CPU time 1274.66 seconds
Started Sep 09 07:41:08 PM UTC 24
Finished Sep 09 08:02:39 PM UTC 24
Peak memory 485860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292416960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2292416960
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/40.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/40.hmac_wipe_secret.1779984431
Short name T405
Test name
Test status
Simulation time 638644507 ps
CPU time 4.95 seconds
Started Sep 09 07:41:05 PM UTC 24
Finished Sep 09 07:41:11 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779984431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1779984431
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/40.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/41.hmac_alert_test.2878695060
Short name T414
Test name
Test status
Simulation time 13832824 ps
CPU time 0.81 seconds
Started Sep 09 07:41:50 PM UTC 24
Finished Sep 09 07:41:52 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878695060 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2878695060
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/41.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/41.hmac_back_pressure.1300659367
Short name T412
Test name
Test status
Simulation time 545254657 ps
CPU time 20.81 seconds
Started Sep 09 07:41:26 PM UTC 24
Finished Sep 09 07:41:49 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300659367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1300659367
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/41.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/41.hmac_burst_wr.1290062825
Short name T419
Test name
Test status
Simulation time 3673414592 ps
CPU time 46.29 seconds
Started Sep 09 07:41:32 PM UTC 24
Finished Sep 09 07:42:19 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290062825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1290062825
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/41.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/41.hmac_datapath_stress.4272614206
Short name T511
Test name
Test status
Simulation time 5882733097 ps
CPU time 1314.21 seconds
Started Sep 09 07:41:30 PM UTC 24
Finished Sep 09 08:03:39 PM UTC 24
Peak memory 727340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272614206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.4272614206
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/41.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/41.hmac_error.1447775748
Short name T428
Test name
Test status
Simulation time 5196073065 ps
CPU time 99.77 seconds
Started Sep 09 07:41:36 PM UTC 24
Finished Sep 09 07:43:18 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447775748 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1447775748
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/41.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/41.hmac_long_msg.2572917353
Short name T443
Test name
Test status
Simulation time 13817293197 ps
CPU time 222.86 seconds
Started Sep 09 07:41:12 PM UTC 24
Finished Sep 09 07:44:59 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572917353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2572917353
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/41.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/41.hmac_smoke.3768484107
Short name T407
Test name
Test status
Simulation time 1631774708 ps
CPU time 16.04 seconds
Started Sep 09 07:41:11 PM UTC 24
Finished Sep 09 07:41:28 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768484107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3768484107
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/41.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/41.hmac_stress_all.1708406409
Short name T514
Test name
Test status
Simulation time 18813117880 ps
CPU time 1335.13 seconds
Started Sep 09 07:41:39 PM UTC 24
Finished Sep 09 08:04:11 PM UTC 24
Peak memory 674076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708406409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1708406409
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/41.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/41.hmac_wipe_secret.2353006192
Short name T442
Test name
Test status
Simulation time 20332122288 ps
CPU time 193.94 seconds
Started Sep 09 07:41:36 PM UTC 24
Finished Sep 09 07:44:53 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353006192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2353006192
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/41.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/42.hmac_alert_test.18024581
Short name T420
Test name
Test status
Simulation time 25914971 ps
CPU time 0.9 seconds
Started Sep 09 07:42:20 PM UTC 24
Finished Sep 09 07:42:22 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18024581 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.18024581
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/42.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/42.hmac_back_pressure.1269704345
Short name T424
Test name
Test status
Simulation time 752311454 ps
CPU time 55.3 seconds
Started Sep 09 07:41:53 PM UTC 24
Finished Sep 09 07:42:50 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269704345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1269704345
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/42.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/42.hmac_burst_wr.3175865341
Short name T422
Test name
Test status
Simulation time 531815095 ps
CPU time 36.43 seconds
Started Sep 09 07:42:03 PM UTC 24
Finished Sep 09 07:42:41 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175865341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3175865341
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/42.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/42.hmac_datapath_stress.47157465
Short name T490
Test name
Test status
Simulation time 2671014007 ps
CPU time 453.03 seconds
Started Sep 09 07:42:03 PM UTC 24
Finished Sep 09 07:49:42 PM UTC 24
Peak memory 498148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47157465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.47157465
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/42.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/42.hmac_error.3398587268
Short name T431
Test name
Test status
Simulation time 17956069582 ps
CPU time 86.17 seconds
Started Sep 09 07:42:06 PM UTC 24
Finished Sep 09 07:43:34 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398587268 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3398587268
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/42.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/42.hmac_long_msg.2349471917
Short name T434
Test name
Test status
Simulation time 22148017265 ps
CPU time 125.93 seconds
Started Sep 09 07:41:52 PM UTC 24
Finished Sep 09 07:44:00 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349471917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2349471917
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/42.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/42.hmac_smoke.981231699
Short name T418
Test name
Test status
Simulation time 1154473293 ps
CPU time 19.47 seconds
Started Sep 09 07:41:50 PM UTC 24
Finished Sep 09 07:42:11 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981231699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.981231699
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/42.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/42.hmac_stress_all.3135391753
Short name T529
Test name
Test status
Simulation time 246149534190 ps
CPU time 2759.16 seconds
Started Sep 09 07:42:15 PM UTC 24
Finished Sep 09 08:28:42 PM UTC 24
Peak memory 811300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135391753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3135391753
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/42.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/42.hmac_wipe_secret.2937699658
Short name T433
Test name
Test status
Simulation time 2967558031 ps
CPU time 101.42 seconds
Started Sep 09 07:42:14 PM UTC 24
Finished Sep 09 07:43:57 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937699658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2937699658
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/42.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/43.hmac_alert_test.837607826
Short name T429
Test name
Test status
Simulation time 15793425 ps
CPU time 0.9 seconds
Started Sep 09 07:43:19 PM UTC 24
Finished Sep 09 07:43:20 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837607826 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.837607826
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/43.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/43.hmac_back_pressure.3420743757
Short name T427
Test name
Test status
Simulation time 1647893962 ps
CPU time 24.48 seconds
Started Sep 09 07:42:42 PM UTC 24
Finished Sep 09 07:43:08 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420743757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3420743757
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/43.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/43.hmac_burst_wr.1668854413
Short name T425
Test name
Test status
Simulation time 325299326 ps
CPU time 2.21 seconds
Started Sep 09 07:42:52 PM UTC 24
Finished Sep 09 07:42:56 PM UTC 24
Peak memory 207136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668854413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1668854413
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/43.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/43.hmac_datapath_stress.2524396475
Short name T435
Test name
Test status
Simulation time 513144357 ps
CPU time 71.85 seconds
Started Sep 09 07:42:52 PM UTC 24
Finished Sep 09 07:44:06 PM UTC 24
Peak memory 350360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524396475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2524396475
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/43.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/43.hmac_error.2060455438
Short name T448
Test name
Test status
Simulation time 2074351333 ps
CPU time 153.16 seconds
Started Sep 09 07:42:56 PM UTC 24
Finished Sep 09 07:45:32 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060455438 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2060455438
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/43.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/43.hmac_long_msg.204122035
Short name T445
Test name
Test status
Simulation time 4804447710 ps
CPU time 164.62 seconds
Started Sep 09 07:42:31 PM UTC 24
Finished Sep 09 07:45:19 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204122035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.204122035
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/43.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/43.hmac_smoke.2915541992
Short name T421
Test name
Test status
Simulation time 306454535 ps
CPU time 6.15 seconds
Started Sep 09 07:42:23 PM UTC 24
Finished Sep 09 07:42:30 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915541992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2915541992
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/43.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/43.hmac_stress_all.1171294292
Short name T90
Test name
Test status
Simulation time 341467230143 ps
CPU time 384.05 seconds
Started Sep 09 07:43:09 PM UTC 24
Finished Sep 09 07:49:39 PM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171294292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1171294292
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/43.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/43.hmac_wipe_secret.2471349922
Short name T432
Test name
Test status
Simulation time 1328579586 ps
CPU time 25.41 seconds
Started Sep 09 07:43:09 PM UTC 24
Finished Sep 09 07:43:36 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471349922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2471349922
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/43.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/44.hmac_alert_test.1685428492
Short name T438
Test name
Test status
Simulation time 37769301 ps
CPU time 0.92 seconds
Started Sep 09 07:44:36 PM UTC 24
Finished Sep 09 07:44:38 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685428492 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1685428492
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/44.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/44.hmac_back_pressure.3925270836
Short name T440
Test name
Test status
Simulation time 3840363840 ps
CPU time 72.3 seconds
Started Sep 09 07:43:35 PM UTC 24
Finished Sep 09 07:44:49 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925270836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3925270836
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/44.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/44.hmac_burst_wr.1585764342
Short name T446
Test name
Test status
Simulation time 4284427985 ps
CPU time 78.34 seconds
Started Sep 09 07:43:59 PM UTC 24
Finished Sep 09 07:45:19 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585764342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1585764342
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/44.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/44.hmac_datapath_stress.2523877590
Short name T37
Test name
Test status
Simulation time 4781547886 ps
CPU time 965.86 seconds
Started Sep 09 07:43:37 PM UTC 24
Finished Sep 09 07:59:53 PM UTC 24
Peak memory 733544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523877590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2523877590
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/44.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/44.hmac_error.243930987
Short name T462
Test name
Test status
Simulation time 114484950345 ps
CPU time 162.11 seconds
Started Sep 09 07:44:02 PM UTC 24
Finished Sep 09 07:46:47 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243930987 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.243930987
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/44.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/44.hmac_long_msg.2235465965
Short name T437
Test name
Test status
Simulation time 5683168218 ps
CPU time 62.85 seconds
Started Sep 09 07:43:30 PM UTC 24
Finished Sep 09 07:44:34 PM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235465965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2235465965
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/44.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/44.hmac_smoke.2399558532
Short name T430
Test name
Test status
Simulation time 544510353 ps
CPU time 6.65 seconds
Started Sep 09 07:43:22 PM UTC 24
Finished Sep 09 07:43:29 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399558532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2399558532
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/44.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/44.hmac_stress_all.1922450775
Short name T503
Test name
Test status
Simulation time 46649149092 ps
CPU time 695.75 seconds
Started Sep 09 07:44:18 PM UTC 24
Finished Sep 09 07:56:03 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922450775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1922450775
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/44.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/44.hmac_wipe_secret.2947279317
Short name T454
Test name
Test status
Simulation time 11119846473 ps
CPU time 112.18 seconds
Started Sep 09 07:44:07 PM UTC 24
Finished Sep 09 07:46:01 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947279317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2947279317
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/44.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/45.hmac_alert_test.2230911631
Short name T447
Test name
Test status
Simulation time 18760707 ps
CPU time 0.82 seconds
Started Sep 09 07:45:21 PM UTC 24
Finished Sep 09 07:45:23 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230911631 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2230911631
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/45.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/45.hmac_back_pressure.2296638259
Short name T460
Test name
Test status
Simulation time 1501182452 ps
CPU time 96.3 seconds
Started Sep 09 07:44:51 PM UTC 24
Finished Sep 09 07:46:29 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296638259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2296638259
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/45.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/45.hmac_burst_wr.1883072688
Short name T455
Test name
Test status
Simulation time 4850057416 ps
CPU time 59.56 seconds
Started Sep 09 07:45:01 PM UTC 24
Finished Sep 09 07:46:03 PM UTC 24
Peak memory 207200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883072688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1883072688
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/45.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/45.hmac_datapath_stress.732018692
Short name T519
Test name
Test status
Simulation time 28238902959 ps
CPU time 1304.72 seconds
Started Sep 09 07:44:57 PM UTC 24
Finished Sep 09 08:06:56 PM UTC 24
Peak memory 784608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732018692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.732018692
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/45.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/45.hmac_error.1351115569
Short name T469
Test name
Test status
Simulation time 44992985038 ps
CPU time 122.08 seconds
Started Sep 09 07:45:01 PM UTC 24
Finished Sep 09 07:47:06 PM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351115569 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1351115569
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/45.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/45.hmac_long_msg.3082224650
Short name T450
Test name
Test status
Simulation time 4472424177 ps
CPU time 59.6 seconds
Started Sep 09 07:44:48 PM UTC 24
Finished Sep 09 07:45:50 PM UTC 24
Peak memory 207580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082224650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3082224650
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/45.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/45.hmac_smoke.1748286109
Short name T439
Test name
Test status
Simulation time 511079877 ps
CPU time 5.07 seconds
Started Sep 09 07:44:40 PM UTC 24
Finished Sep 09 07:44:46 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748286109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1748286109
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/45.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/45.hmac_stress_all.2715895264
Short name T523
Test name
Test status
Simulation time 465263511830 ps
CPU time 1518.45 seconds
Started Sep 09 07:45:21 PM UTC 24
Finished Sep 09 08:10:57 PM UTC 24
Peak memory 378200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715895264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2715895264
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/45.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/45.hmac_wipe_secret.2009622187
Short name T452
Test name
Test status
Simulation time 6571750651 ps
CPU time 44.77 seconds
Started Sep 09 07:45:08 PM UTC 24
Finished Sep 09 07:45:54 PM UTC 24
Peak memory 207280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009622187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2009622187
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/45.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/46.hmac_alert_test.345625712
Short name T456
Test name
Test status
Simulation time 14476965 ps
CPU time 0.83 seconds
Started Sep 09 07:46:02 PM UTC 24
Finished Sep 09 07:46:05 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345625712 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.345625712
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/46.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/46.hmac_back_pressure.2037495435
Short name T453
Test name
Test status
Simulation time 337865190 ps
CPU time 13.59 seconds
Started Sep 09 07:45:41 PM UTC 24
Finished Sep 09 07:45:56 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037495435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2037495435
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/46.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/46.hmac_burst_wr.4263222882
Short name T464
Test name
Test status
Simulation time 5727992693 ps
CPU time 61.18 seconds
Started Sep 09 07:45:50 PM UTC 24
Finished Sep 09 07:46:53 PM UTC 24
Peak memory 215960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263222882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.4263222882
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/46.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/46.hmac_datapath_stress.803849255
Short name T508
Test name
Test status
Simulation time 7634126358 ps
CPU time 707.04 seconds
Started Sep 09 07:45:46 PM UTC 24
Finished Sep 09 07:57:42 PM UTC 24
Peak memory 715160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803849255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.803849255
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/46.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/46.hmac_error.1421204778
Short name T467
Test name
Test status
Simulation time 17064073341 ps
CPU time 65.31 seconds
Started Sep 09 07:45:53 PM UTC 24
Finished Sep 09 07:47:00 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421204778 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1421204778
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/46.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/46.hmac_long_msg.1328618903
Short name T486
Test name
Test status
Simulation time 2823392788 ps
CPU time 177.2 seconds
Started Sep 09 07:45:34 PM UTC 24
Finished Sep 09 07:48:34 PM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328618903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1328618903
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/46.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/46.hmac_smoke.4293467489
Short name T449
Test name
Test status
Simulation time 472658900 ps
CPU time 14.05 seconds
Started Sep 09 07:45:25 PM UTC 24
Finished Sep 09 07:45:40 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293467489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.4293467489
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/46.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/46.hmac_stress_all.1425102099
Short name T526
Test name
Test status
Simulation time 41075318401 ps
CPU time 1818.7 seconds
Started Sep 09 07:45:57 PM UTC 24
Finished Sep 09 08:16:36 PM UTC 24
Peak memory 793044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425102099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1425102099
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/46.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/46.hmac_wipe_secret.2405380514
Short name T477
Test name
Test status
Simulation time 35654511022 ps
CPU time 99.85 seconds
Started Sep 09 07:45:55 PM UTC 24
Finished Sep 09 07:47:37 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405380514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2405380514
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/46.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/47.hmac_alert_test.1148765044
Short name T463
Test name
Test status
Simulation time 21105424 ps
CPU time 0.87 seconds
Started Sep 09 07:46:48 PM UTC 24
Finished Sep 09 07:46:50 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148765044 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1148765044
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/47.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/47.hmac_back_pressure.1791704944
Short name T484
Test name
Test status
Simulation time 14095940490 ps
CPU time 139.48 seconds
Started Sep 09 07:46:07 PM UTC 24
Finished Sep 09 07:48:29 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791704944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1791704944
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/47.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/47.hmac_burst_wr.1054317533
Short name T471
Test name
Test status
Simulation time 5220755323 ps
CPU time 58.7 seconds
Started Sep 09 07:46:15 PM UTC 24
Finished Sep 09 07:47:15 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054317533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1054317533
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/47.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/47.hmac_datapath_stress.220244845
Short name T40
Test name
Test status
Simulation time 5351265700 ps
CPU time 931.65 seconds
Started Sep 09 07:46:08 PM UTC 24
Finished Sep 09 08:01:49 PM UTC 24
Peak memory 649768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220244845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.220244845
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/47.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/47.hmac_error.903571175
Short name T473
Test name
Test status
Simulation time 14977283703 ps
CPU time 46.05 seconds
Started Sep 09 07:46:29 PM UTC 24
Finished Sep 09 07:47:17 PM UTC 24
Peak memory 207360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903571175 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.903571175
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/47.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/47.hmac_long_msg.1655741221
Short name T485
Test name
Test status
Simulation time 7256431552 ps
CPU time 143.08 seconds
Started Sep 09 07:46:07 PM UTC 24
Finished Sep 09 07:48:33 PM UTC 24
Peak memory 223716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655741221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1655741221
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/47.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/47.hmac_smoke.256435582
Short name T457
Test name
Test status
Simulation time 42544029 ps
CPU time 2.75 seconds
Started Sep 09 07:46:04 PM UTC 24
Finished Sep 09 07:46:08 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256435582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.256435582
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/47.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/47.hmac_stress_all.2896003864
Short name T504
Test name
Test status
Simulation time 15337659288 ps
CPU time 564.6 seconds
Started Sep 09 07:46:37 PM UTC 24
Finished Sep 09 07:56:08 PM UTC 24
Peak memory 725304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896003864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2896003864
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/47.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/47.hmac_wipe_secret.4238392530
Short name T470
Test name
Test status
Simulation time 717319177 ps
CPU time 39.67 seconds
Started Sep 09 07:46:31 PM UTC 24
Finished Sep 09 07:47:12 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238392530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.4238392530
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/47.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/48.hmac_alert_test.1381496991
Short name T474
Test name
Test status
Simulation time 80609164 ps
CPU time 0.69 seconds
Started Sep 09 07:47:17 PM UTC 24
Finished Sep 09 07:47:19 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381496991 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1381496991
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/48.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/48.hmac_back_pressure.2424710826
Short name T472
Test name
Test status
Simulation time 826510025 ps
CPU time 16.99 seconds
Started Sep 09 07:46:57 PM UTC 24
Finished Sep 09 07:47:16 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424710826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2424710826
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/48.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/48.hmac_burst_wr.866123048
Short name T480
Test name
Test status
Simulation time 1453115374 ps
CPU time 69.69 seconds
Started Sep 09 07:47:02 PM UTC 24
Finished Sep 09 07:48:14 PM UTC 24
Peak memory 206860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866123048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.866123048
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/48.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/48.hmac_datapath_stress.1515119168
Short name T493
Test name
Test status
Simulation time 854059650 ps
CPU time 199.26 seconds
Started Sep 09 07:47:02 PM UTC 24
Finished Sep 09 07:50:25 PM UTC 24
Peak memory 708288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515119168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1515119168
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/48.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/48.hmac_error.2332832886
Short name T475
Test name
Test status
Simulation time 786201289 ps
CPU time 13.54 seconds
Started Sep 09 07:47:11 PM UTC 24
Finished Sep 09 07:47:26 PM UTC 24
Peak memory 207064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332832886 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2332832886
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/48.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/48.hmac_long_msg.1625651986
Short name T488
Test name
Test status
Simulation time 6895401686 ps
CPU time 134.23 seconds
Started Sep 09 07:46:54 PM UTC 24
Finished Sep 09 07:49:11 PM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625651986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1625651986
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/48.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/48.hmac_smoke.4069560532
Short name T465
Test name
Test status
Simulation time 407185752 ps
CPU time 4.57 seconds
Started Sep 09 07:46:51 PM UTC 24
Finished Sep 09 07:46:57 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069560532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.4069560532
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/48.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/48.hmac_stress_all.2375468833
Short name T506
Test name
Test status
Simulation time 41182610935 ps
CPU time 567.86 seconds
Started Sep 09 07:47:13 PM UTC 24
Finished Sep 09 07:56:49 PM UTC 24
Peak memory 217808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375468833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2375468833
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/48.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/48.hmac_wipe_secret.450094004
Short name T489
Test name
Test status
Simulation time 6452281287 ps
CPU time 118.7 seconds
Started Sep 09 07:47:11 PM UTC 24
Finished Sep 09 07:49:12 PM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450094004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.450094004
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/48.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/49.hmac_alert_test.3831986274
Short name T481
Test name
Test status
Simulation time 40303439 ps
CPU time 0.79 seconds
Started Sep 09 07:48:15 PM UTC 24
Finished Sep 09 07:48:17 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831986274 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3831986274
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/49.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/49.hmac_back_pressure.3901531339
Short name T487
Test name
Test status
Simulation time 25172892358 ps
CPU time 93.91 seconds
Started Sep 09 07:47:19 PM UTC 24
Finished Sep 09 07:48:55 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901531339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3901531339
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/49.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/49.hmac_burst_wr.245764827
Short name T478
Test name
Test status
Simulation time 425396827 ps
CPU time 9.16 seconds
Started Sep 09 07:47:30 PM UTC 24
Finished Sep 09 07:47:41 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245764827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.245764827
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/49.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/49.hmac_datapath_stress.2699931925
Short name T512
Test name
Test status
Simulation time 4724963316 ps
CPU time 966.62 seconds
Started Sep 09 07:47:26 PM UTC 24
Finished Sep 09 08:03:45 PM UTC 24
Peak memory 711132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699931925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2699931925
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/49.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/49.hmac_error.1985288497
Short name T483
Test name
Test status
Simulation time 3390381229 ps
CPU time 46.65 seconds
Started Sep 09 07:47:38 PM UTC 24
Finished Sep 09 07:48:26 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985288497 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1985288497
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/49.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/49.hmac_long_msg.2884999266
Short name T494
Test name
Test status
Simulation time 15029827994 ps
CPU time 191.16 seconds
Started Sep 09 07:47:18 PM UTC 24
Finished Sep 09 07:50:32 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884999266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2884999266
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/49.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/49.hmac_smoke.1781002634
Short name T476
Test name
Test status
Simulation time 1197814210 ps
CPU time 11.79 seconds
Started Sep 09 07:47:17 PM UTC 24
Finished Sep 09 07:47:30 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781002634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1781002634
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/49.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/49.hmac_stress_all.2530453984
Short name T521
Test name
Test status
Simulation time 90186921990 ps
CPU time 1143.94 seconds
Started Sep 09 07:47:46 PM UTC 24
Finished Sep 09 08:07:02 PM UTC 24
Peak memory 713108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530453984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2530453984
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/49.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/49.hmac_wipe_secret.392628018
Short name T491
Test name
Test status
Simulation time 6780015875 ps
CPU time 149 seconds
Started Sep 09 07:47:42 PM UTC 24
Finished Sep 09 07:50:14 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392628018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.392628018
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/49.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/5.hmac_alert_test.1241981217
Short name T80
Test name
Test status
Simulation time 63551376 ps
CPU time 0.84 seconds
Started Sep 09 07:21:41 PM UTC 24
Finished Sep 09 07:21:43 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241981217 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1241981217
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/5.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/5.hmac_back_pressure.3240419349
Short name T21
Test name
Test status
Simulation time 1250778479 ps
CPU time 66.78 seconds
Started Sep 09 07:21:19 PM UTC 24
Finished Sep 09 07:22:27 PM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240419349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3240419349
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/5.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/5.hmac_burst_wr.4152608494
Short name T28
Test name
Test status
Simulation time 3040326775 ps
CPU time 46.93 seconds
Started Sep 09 07:21:23 PM UTC 24
Finished Sep 09 07:22:11 PM UTC 24
Peak memory 215964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152608494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.4152608494
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/5.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/5.hmac_datapath_stress.3644143049
Short name T243
Test name
Test status
Simulation time 46844838137 ps
CPU time 440.84 seconds
Started Sep 09 07:21:19 PM UTC 24
Finished Sep 09 07:28:45 PM UTC 24
Peak memory 698592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644143049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3644143049
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/5.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/5.hmac_error.2937890063
Short name T195
Test name
Test status
Simulation time 13758580189 ps
CPU time 210.98 seconds
Started Sep 09 07:21:31 PM UTC 24
Finished Sep 09 07:25:05 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937890063 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2937890063
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/5.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/5.hmac_long_msg.955591508
Short name T160
Test name
Test status
Simulation time 12791306035 ps
CPU time 138.88 seconds
Started Sep 09 07:21:19 PM UTC 24
Finished Sep 09 07:23:40 PM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955591508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.955591508
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/5.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/5.hmac_smoke.597779164
Short name T78
Test name
Test status
Simulation time 628788513 ps
CPU time 14.76 seconds
Started Sep 09 07:21:17 PM UTC 24
Finished Sep 09 07:21:33 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597779164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.597779164
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/5.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/5.hmac_stress_all_with_rand_reset.2721846486
Short name T74
Test name
Test status
Simulation time 16141080813 ps
CPU time 610.9 seconds
Started Sep 09 07:21:40 PM UTC 24
Finished Sep 09 07:32:00 PM UTC 24
Peak memory 737696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27218464
86 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.2721846486
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/6.hmac_alert_test.710970055
Short name T169
Test name
Test status
Simulation time 27295661 ps
CPU time 0.84 seconds
Started Sep 09 07:21:58 PM UTC 24
Finished Sep 09 07:21:59 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710970055 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.710970055
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/6.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/6.hmac_burst_wr.2842261940
Short name T29
Test name
Test status
Simulation time 653551997 ps
CPU time 33.24 seconds
Started Sep 09 07:21:48 PM UTC 24
Finished Sep 09 07:22:23 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842261940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2842261940
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/6.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/6.hmac_datapath_stress.229323610
Short name T266
Test name
Test status
Simulation time 46158448737 ps
CPU time 524.07 seconds
Started Sep 09 07:21:48 PM UTC 24
Finished Sep 09 07:30:38 PM UTC 24
Peak memory 729316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229323610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.229323610
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/6.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/6.hmac_error.23897029
Short name T62
Test name
Test status
Simulation time 1246295255 ps
CPU time 78.8 seconds
Started Sep 09 07:21:50 PM UTC 24
Finished Sep 09 07:23:11 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23897029 -assert nopostproc +UVM_TESTNAME=hmac
_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.23897029
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/6.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/6.hmac_long_msg.2729357456
Short name T179
Test name
Test status
Simulation time 7192980120 ps
CPU time 131.52 seconds
Started Sep 09 07:21:46 PM UTC 24
Finished Sep 09 07:24:00 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729357456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2729357456
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/6.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/6.hmac_smoke.748988790
Short name T142
Test name
Test status
Simulation time 1122274292 ps
CPU time 13.28 seconds
Started Sep 09 07:21:43 PM UTC 24
Finished Sep 09 07:21:58 PM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748988790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.748988790
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/6.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/6.hmac_wipe_secret.3141861135
Short name T50
Test name
Test status
Simulation time 40615238717 ps
CPU time 60.74 seconds
Started Sep 09 07:21:55 PM UTC 24
Finished Sep 09 07:22:57 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141861135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3141861135
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/6.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/7.hmac_alert_test.1379624749
Short name T171
Test name
Test status
Simulation time 50393126 ps
CPU time 0.78 seconds
Started Sep 09 07:22:24 PM UTC 24
Finished Sep 09 07:22:26 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379624749 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1379624749
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/7.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/7.hmac_back_pressure.3240708293
Short name T55
Test name
Test status
Simulation time 1817510112 ps
CPU time 64.2 seconds
Started Sep 09 07:22:00 PM UTC 24
Finished Sep 09 07:23:06 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240708293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3240708293
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/7.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/7.hmac_burst_wr.1833830719
Short name T22
Test name
Test status
Simulation time 1240303026 ps
CPU time 21.13 seconds
Started Sep 09 07:22:06 PM UTC 24
Finished Sep 09 07:22:28 PM UTC 24
Peak memory 207428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833830719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1833830719
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/7.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/7.hmac_datapath_stress.2895420213
Short name T186
Test name
Test status
Simulation time 3811166237 ps
CPU time 152.94 seconds
Started Sep 09 07:22:02 PM UTC 24
Finished Sep 09 07:24:38 PM UTC 24
Peak memory 452964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895420213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2895420213
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/7.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/7.hmac_error.200327841
Short name T63
Test name
Test status
Simulation time 13205926471 ps
CPU time 81.74 seconds
Started Sep 09 07:22:12 PM UTC 24
Finished Sep 09 07:23:36 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200327841 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.200327841
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/7.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/7.hmac_long_msg.626962193
Short name T47
Test name
Test status
Simulation time 3517360801 ps
CPU time 49.09 seconds
Started Sep 09 07:21:59 PM UTC 24
Finished Sep 09 07:22:49 PM UTC 24
Peak memory 207336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626962193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.626962193
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/7.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/7.hmac_smoke.883487144
Short name T146
Test name
Test status
Simulation time 415903579 ps
CPU time 6.89 seconds
Started Sep 09 07:21:58 PM UTC 24
Finished Sep 09 07:22:06 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883487144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.883487144
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/7.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/7.hmac_stress_all.1062567204
Short name T528
Test name
Test status
Simulation time 100276485031 ps
CPU time 3755.59 seconds
Started Sep 09 07:22:20 PM UTC 24
Finished Sep 09 08:25:35 PM UTC 24
Peak memory 795068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062567204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1062567204
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/7.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/7.hmac_stress_all_with_rand_reset.1328960554
Short name T12
Test name
Test status
Simulation time 2271181642 ps
CPU time 74.63 seconds
Started Sep 09 07:22:22 PM UTC 24
Finished Sep 09 07:23:39 PM UTC 24
Peak memory 366672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13289605
54 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.1328960554
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/7.hmac_wipe_secret.54047026
Short name T96
Test name
Test status
Simulation time 27931748161 ps
CPU time 48.67 seconds
Started Sep 09 07:22:15 PM UTC 24
Finished Sep 09 07:23:05 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54047026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.54047026
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/7.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/8.hmac_alert_test.1316529260
Short name T49
Test name
Test status
Simulation time 35539808 ps
CPU time 0.92 seconds
Started Sep 09 07:22:54 PM UTC 24
Finished Sep 09 07:22:56 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316529260 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1316529260
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/8.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/8.hmac_back_pressure.3054672202
Short name T172
Test name
Test status
Simulation time 894768834 ps
CPU time 34.75 seconds
Started Sep 09 07:22:29 PM UTC 24
Finished Sep 09 07:23:06 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054672202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3054672202
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/8.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/8.hmac_burst_wr.980779414
Short name T56
Test name
Test status
Simulation time 469607133 ps
CPU time 25.22 seconds
Started Sep 09 07:22:41 PM UTC 24
Finished Sep 09 07:23:08 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980779414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.980779414
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/8.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/8.hmac_datapath_stress.1574884981
Short name T196
Test name
Test status
Simulation time 1356628526 ps
CPU time 147.71 seconds
Started Sep 09 07:22:35 PM UTC 24
Finished Sep 09 07:25:06 PM UTC 24
Peak memory 653672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574884981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1574884981
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/8.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/8.hmac_error.3024675351
Short name T209
Test name
Test status
Simulation time 16800700500 ps
CPU time 185.59 seconds
Started Sep 09 07:22:44 PM UTC 24
Finished Sep 09 07:25:52 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024675351 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3024675351
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/8.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/8.hmac_long_msg.1513945310
Short name T173
Test name
Test status
Simulation time 2575199198 ps
CPU time 36.79 seconds
Started Sep 09 07:22:29 PM UTC 24
Finished Sep 09 07:23:08 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513945310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1513945310
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/8.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/8.hmac_smoke.90891412
Short name T43
Test name
Test status
Simulation time 1417548708 ps
CPU time 6.21 seconds
Started Sep 09 07:22:27 PM UTC 24
Finished Sep 09 07:22:35 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90891412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 8.hmac_smoke.90891412
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/8.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/8.hmac_stress_all.799454852
Short name T94
Test name
Test status
Simulation time 317910272 ps
CPU time 9.63 seconds
Started Sep 09 07:22:51 PM UTC 24
Finished Sep 09 07:23:01 PM UTC 24
Peak memory 207400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799454852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.799454852
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/8.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/8.hmac_stress_all_with_rand_reset.2696880220
Short name T25
Test name
Test status
Simulation time 49480033765 ps
CPU time 480.28 seconds
Started Sep 09 07:22:52 PM UTC 24
Finished Sep 09 07:30:58 PM UTC 24
Peak memory 647568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26968802
20 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.2696880220
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/8.hmac_wipe_secret.2193988003
Short name T191
Test name
Test status
Simulation time 32634922773 ps
CPU time 120.94 seconds
Started Sep 09 07:22:47 PM UTC 24
Finished Sep 09 07:24:51 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193988003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2193988003
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/8.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/9.hmac_alert_test.1843008760
Short name T174
Test name
Test status
Simulation time 12874389 ps
CPU time 0.83 seconds
Started Sep 09 07:23:09 PM UTC 24
Finished Sep 09 07:23:11 PM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843008760 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1843008760
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/9.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/9.hmac_back_pressure.531752951
Short name T185
Test name
Test status
Simulation time 5963550589 ps
CPU time 90.1 seconds
Started Sep 09 07:23:01 PM UTC 24
Finished Sep 09 07:24:33 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531752951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.531752951
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/9.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/9.hmac_burst_wr.2992914113
Short name T178
Test name
Test status
Simulation time 40780617266 ps
CPU time 44.52 seconds
Started Sep 09 07:23:05 PM UTC 24
Finished Sep 09 07:23:51 PM UTC 24
Peak memory 217752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992914113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2992914113
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/9.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/9.hmac_datapath_stress.2194157628
Short name T302
Test name
Test status
Simulation time 12099541821 ps
CPU time 590 seconds
Started Sep 09 07:23:02 PM UTC 24
Finished Sep 09 07:32:59 PM UTC 24
Peak memory 719172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194157628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2194157628
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/9.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/9.hmac_error.3362033289
Short name T216
Test name
Test status
Simulation time 25777432855 ps
CPU time 178.56 seconds
Started Sep 09 07:23:08 PM UTC 24
Finished Sep 09 07:26:09 PM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362033289 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3362033289
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/9.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/9.hmac_long_msg.2490313928
Short name T163
Test name
Test status
Simulation time 1040278237 ps
CPU time 29.32 seconds
Started Sep 09 07:22:59 PM UTC 24
Finished Sep 09 07:23:29 PM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490313928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2490313928
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/9.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/9.hmac_smoke.282064444
Short name T145
Test name
Test status
Simulation time 2755227984 ps
CPU time 22.74 seconds
Started Sep 09 07:22:57 PM UTC 24
Finished Sep 09 07:23:21 PM UTC 24
Peak memory 207488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282064444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.282064444
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/9.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/9.hmac_stress_all.1853286958
Short name T85
Test name
Test status
Simulation time 178881738085 ps
CPU time 723.09 seconds
Started Sep 09 07:23:08 PM UTC 24
Finished Sep 09 07:35:19 PM UTC 24
Peak memory 649708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853286958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1853286958
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/9.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/default/9.hmac_wipe_secret.2976151737
Short name T130
Test name
Test status
Simulation time 1112103358 ps
CPU time 36.92 seconds
Started Sep 09 07:23:08 PM UTC 24
Finished Sep 09 07:23:46 PM UTC 24
Peak memory 207168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976151737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2976151737
Directory /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/9.hmac_wipe_secret/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%