Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

36765706

1

T1

1757

T2

11777

T3

1

full_word

33764075

1

T1

1845

T2

18410

T21

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	70529431	1			T1	3602		T2	30187		T3	1
auto[TlIntgErrCmd]	115	1			T66	10		T67	4		T68	1
auto[TlIntgErrData]	121	1			T66	13		T67	3		T68	6
auto[TlIntgErrBoth]	114	1			T66	7		T67	3		T68	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33153975

1

T1

1865

T2

12443

T3

1

auto[1]

37375806

1

T1

1737

T2

17744

T21

19

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17009676	1			T1	1004		T2	6274		T3	1
auto[TlIntgErrNone]	partial	auto[1]	19755705	1			T1	753		T2	5503		T21	17
auto[TlIntgErrNone]	full_word	auto[0]	16144159	1			T1	861		T2	6169		T21	1
auto[TlIntgErrNone]	full_word	auto[1]	17619891	1			T1	984		T2	12241		T21	2
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T66	6		T67	2		T151	1
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T66	3		T67	2		T68	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T148	1		T147	1		T152	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T66	1		T150	1		T153	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T66	6		T67	2		T68	3
auto[TlIntgErrData]	partial	auto[1]	61	1			T66	7		T67	1		T68	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T68	1		T148	1		T154	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T147	2		T155	2		-	-
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T66	3		T67	3		T68	1
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T66	4		T68	2		T151	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T151	1		T148	2		T150	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T147	1		T153	1		-	-