Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	401754953	1011650	0	0
intr_enable_rd_A	401754953	4802	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401754953	1011650	0	0
T18	143315	0	0	0
T19	0	9107	0	0
T20	471246	7430	0	0
T63	0	15	0	0
T66	0	5	0	0
T67	0	1	0	0
T70	0	5	0	0
T71	0	12	0	0
T72	0	15	0	0
T77	0	267	0	0
T80	0	208	0	0
T81	29968	0	0	0
T82	44216	0	0	0
T83	65122	0	0	0
T84	152445	0	0	0
T85	1422	0	0	0
T86	106686	0	0	0
T87	46297	0	0	0
T88	193843	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401754953	4802	0	0
T89	380892	9	0	0
T90	0	79	0	0
T91	0	51	0	0
T92	0	5	0	0
T93	0	63	0	0
T94	0	25	0	0
T95	0	2	0	0
T96	0	1	0	0
T97	0	49	0	0
T98	0	14	0	0
T99	178852	0	0	0
T100	389857	0	0	0
T101	168133	0	0	0
T102	1532	0	0	0
T103	2975	0	0	0
T104	113301	0	0	0
T105	138569	0	0	0
T106	158766	0	0	0
T107	207710	0	0	0