Unified Coverage Report :: Module :: prim_sha2

Module : prim_sha2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.96	98.58	95.17		90.00	92.11

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode	99.12	100.00	97.87		100.00	98.59

---

Module Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.12	100.00	97.87		100.00	98.59

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.07	98.13	96.42		90.00	95.74

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.39	100.00	98.18			100.00		u_prim_sha2_512

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_pad	91.43	96.12	94.93		81.82	92.86

Line Coverage for Module : prim_sha2

	Line No.	Total	Covered	Percent
TOTAL		141	139	98.58
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	92	14	14	100.00
ALWAYS	117	4	4	100.00
ALWAYS	123	10	10	100.00
ALWAYS	140	3	3	100.00
ALWAYS	146	19	19	100.00
ALWAYS	174	3	3	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	271	7	7	100.00
ALWAYS	288	3	3	100.00
CONT_ASSIGN	293	1	1	100.00
ALWAYS	298	3	3	100.00
CONT_ASSIGN	303	1	1	100.00
ALWAYS	306	3	3	100.00
CONT_ASSIGN	312	1	1	100.00
ALWAYS	315	3	3	100.00
ALWAYS	320	26	26	100.00
ALWAYS	371	3	3	100.00
ALWAYS	385	3	3	100.00
ALWAYS	392	3	3	100.00
CONT_ASSIGN	396	1	1	100.00
ALWAYS	399	23	21	91.30
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	480	1	1	100.00
CONT_ASSIGN	483	1	1	100.00

77                        // to hash.
78         1/1            assign hash_go = hash_start_i | hash_continue_i;
           Tests:       T1 T2 T3 
79                      
80         1/1            assign digest_mode_flag_d = hash_go     ? digest_mode_i   :    // latch in configured mode
           Tests:       T1 T2 T3 
81                                                    hash_done_o ? SHA2_None       :    // clear
82                                                                  digest_mode_flag_q;  // keep
83                      
84                        if (MultimodeEn) begin : gen_multimode
85                          // datapath signal definitions for multi-mode
86                          sha_word64_t [7:0]  hash_d, hash_q; // a,b,c,d,e,f,g,h
87                          sha_word64_t [15:0] w_d, w_q;
88                          sha_word64_t [7:0]  digest_d, digest_q;
89                      
90                          // compute w
91                          always_comb begin : compute_w_multimode
92         1/1                w_d = w_q;
           Tests:       T1 T2 T3 
93         1/1                if (wipe_secret_i) begin
           Tests:       T1 T2 T3 
94         1/1                  w_d = {32{wipe_v_i}};
           Tests:       T31 T33 T34 
95         1/1                end else if (!sha_en_i || hash_go) begin
           Tests:       T1 T2 T3 
96         1/1                  w_d = '0;
           Tests:       T1 T2 T3 
97         1/1                end else if (!run_hash && update_w_from_fifo) begin
           Tests:       T1 T2 T4 
98                              // this logic runs at the first stage of SHA: hash not running yet,
99                              // still filling in first 16 words
100        1/1                  w_d = {shaf_rdata, w_q[15:1]};
           Tests:       T1 T2 T4 
101        1/1                end else if (calculate_next_w) begin // message scheduling/derivation for last 48/64 rounds
           Tests:       T1 T2 T4 
102        1/1                  if (digest_mode_flag_q == SHA2_256) begin
           Tests:       T1 T2 T4 
103                               // this computes the next w[16] and shifts out w[0] into compression below
104        1/1                    w_d = {{32'b0, calc_w_256(w_q[0][31:0], w_q[1][31:0], w_q[9][31:0],
           Tests:       T1 T2 T4 
105                                     w_q[14][31:0])}, w_q[15:1]};
106        1/1                  end else if ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) begin
           Tests:       T1 T2 T4 
107        1/1                    w_d = {calc_w_512(w_q[0], w_q[1], w_q[9], w_q[14]), w_q[15:1]};
           Tests:       T1 T2 T4 
108                             end
                   ==>  MISSING_ELSE
109        1/1                end else if (run_hash) begin
           Tests:       T1 T2 T4 
110                             // just shift-out the words as they get consumed. There's no incoming data.
111        1/1                  w_d = {ZeroWord, w_q[15:1]};
           Tests:       T1 T2 T4 
112                           end
                        MISSING_ELSE
113                         end : compute_w_multimode
114                     
115                         // update w
116                         always_ff @(posedge clk_i or negedge rst_ni) begin : update_w_multimode
117        2/2                if (!rst_ni)            w_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
118        2/2                else if (MultimodeEn)   w_q <= w_d;
           Tests:       T1 T2 T3  | T1 T2 T3 
                   ==>  MISSING_ELSE
119                         end : update_w_multimode
120                     
121                         // compute hash
122                         always_comb begin : compression_multimode
123        1/1                hash_d = hash_q;
           Tests:       T1 T2 T3 
124        1/1                if (wipe_secret_i) begin
           Tests:       T1 T2 T3 
125        1/1                  hash_d = {16{wipe_v_i}};
           Tests:       T31 T33 T34 
126        1/1                end else if (init_hash) begin
           Tests:       T1 T2 T3 
127        1/1                  hash_d = digest_q;
           Tests:       T1 T2 T4 
128        1/1                end else if (run_hash) begin
           Tests:       T1 T2 T3 
129        1/1                  if (digest_mode_flag_q == SHA2_256) begin
           Tests:       T1 T2 T4 
130        1/1                    hash_d = compress_multi_256(w_q[0][31:0],
           Tests:       T1 T2 T4 
131                                        CubicRootPrime256[round_q[RndWidth256-1:0]], hash_q);
132        1/1                  end else if ((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384)) begin
           Tests:       T1 T2 T4 
133        1/1                    hash_d = compress_512(w_q[0], CubicRootPrime512[round_q], hash_q);
           Tests:       T1 T2 T4 
134                             end
                   ==>  MISSING_ELSE
135                           end
                        MISSING_ELSE
136                         end : compression_multimode
137                     
138                         // update hash
139                         always_ff @(posedge clk_i or negedge rst_ni) begin : update_hash_multimode
140        2/2                if (!rst_ni)  hash_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
141        1/1                else          hash_q <= hash_d;
           Tests:       T1 T2 T3 
142                         end : update_hash_multimode
143                     
144                         // compute digest
145                         always_comb begin : compute_digest_multimode
146        1/1                digest_d = digest_q;
           Tests:       T1 T2 T3 
147        1/1                if (wipe_secret_i) begin
           Tests:       T1 T2 T3 
148        1/1                  digest_d = {16{wipe_v_i}};
           Tests:       T31 T33 T34 
149        1/1                end else if (hash_start_i) begin
           Tests:       T1 T2 T3 
150        1/1                  for (int i = 0 ; i < 8 ; i++) begin
           Tests:       T1 T2 T4 
151        1/1                    if (digest_mode_i == SHA2_256) begin
           Tests:       T1 T2 T4 
152        1/1                      digest_d[i] = {32'b0, InitHash_256[i]};
           Tests:       T1 T2 T4 
153        1/1                    end else if (digest_mode_i == SHA2_384) begin
           Tests:       T1 T2 T4 
154        1/1                      digest_d[i] = InitHash_384[i];
           Tests:       T2 T4 T5 
155        1/1                    end else if (digest_mode_i == SHA2_512) begin
           Tests:       T1 T2 T4 
156        1/1                      digest_d[i] = InitHash_512[i];
           Tests:       T1 T2 T4 
157                               end
                   ==>  MISSING_ELSE
158                             end
159        1/1                end else if (clear_digest) begin
           Tests:       T1 T2 T3 
160        1/1                  digest_d = '0;
           Tests:       T2 T4 T5 
161        1/1                end else if (!sha_en_i) begin
           Tests:       T1 T2 T3 
162        1/1                  for (int i = 0; i < 8; i++) begin
           Tests:       T1 T2 T3 
163        1/1                    digest_d[i] = digest_we_i[i] ? digest_i[i] : digest_q[i];
           Tests:       T1 T2 T3 
164                             end
165        1/1                end else if (update_digest) begin
           Tests:       T1 T2 T4 
166        1/1                  for (int i = 0 ; i < 8 ; i++) begin
           Tests:       T1 T2 T4 
167        1/1                    digest_d[i] = digest_q[i] + hash_q[i];
           Tests:       T1 T2 T4 
168                             end
169                           end
                        MISSING_ELSE
170                         end : compute_digest_multimode
171                     
172                         // update digest
173                         always_ff @(posedge clk_i or negedge rst_ni) begin
174        2/2                if (!rst_ni)  digest_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
175        1/1                else          digest_q <= digest_d;
           Tests:       T1 T2 T3 
176                         end
177                     
178                         // assign digest to output
179        1/1              assign digest_o = digest_q;
           Tests:       T1 T2 T3 
180                     
181                       end else begin : gen_256 // MultimodeEn = 0
182                         // datapath signal definitions for SHA-2 256 only
183                         sha_word32_t        shaf_rdata256;
184                         sha_word32_t [7:0]  hash256_d, hash256_q; // a,b,c,d,e,f,g,h
185                         sha_word32_t [15:0] w256_d, w256_q;
186                         sha_word32_t [7:0]  digest256_d, digest256_q;
187                     
188                         assign shaf_rdata256 = shaf_rdata[31:0];
189                     
190                         always_comb begin : compute_w_256
191                           // ~MultimodeEn
192                           w256_d = w256_q;
193                           if (wipe_secret_i) begin
194                             w256_d = {16{wipe_v_i}};
195                           end else if (!sha_en_i || hash_go) begin
196                             w256_d = '0;
197                           end else if (!run_hash && update_w_from_fifo) begin
198                             // this logic runs at the first stage of SHA: hash not running yet,
199                             // still filling in first 16 words
200                             w256_d = {shaf_rdata256, w256_q[15:1]};
201                           end else if (calculate_next_w) begin // message scheduling/derivation for last 48/64 rounds
202                             w256_d = {calc_w_256(w256_q[0][31:0], w256_q[1][31:0], w256_q[9][31:0],
203                                      w256_q[14][31:0]), w256_q[15:1]};
204                           end else if (run_hash) begin
205                             // just shift-out the words as they get consumed. There's no incoming data.
206                             w256_d = {ZeroWord[31:0], w256_q[15:1]};
207                           end
208                         end : compute_w_256
209                     
210                         // update w_256
211                         always_ff @(posedge clk_i or negedge rst_ni) begin : update_w_256
212                           if (!rst_ni)            w256_q <= '0;
213                           else if (!MultimodeEn)  w256_q <= w256_d;
214                         end : update_w_256
215                     
216                         // compute hash_256
217                         always_comb begin : compression_256
218                           hash256_d = hash256_q;
219                           if (wipe_secret_i) begin
220                             hash256_d = {8{wipe_v_i}};
221                           end else if (init_hash) begin
222                             hash256_d = digest256_q;
223                           end else if (run_hash) begin
224                             hash256_d = compress_256(w256_q[0], CubicRootPrime256[round_q[RndWidth256-1:0]], hash256_q);
225                           end
226                         end : compression_256
227                     
228                         // update hash_256
229                         always_ff @(posedge clk_i or negedge rst_ni) begin : update_hash256
230                           if (!rst_ni) hash256_q <= '0;
231                           else         hash256_q <= hash256_d;
232                         end : update_hash256
233                     
234                         // compute digest_256
235                         always_comb begin : compute_digest_256
236                           digest256_d = digest256_q;
237                           if (wipe_secret_i) begin
238                             digest256_d = {8{wipe_v_i}};
239                           end else if (hash_start_i) begin
240                             for (int i = 0 ; i < 8 ; i++) begin
241                                 digest256_d[i] = InitHash_256[i];
242                             end
243                           end else if (clear_digest) begin
244                             digest256_d = '0;
245                           end else if (!sha_en_i) begin
246                             for (int i = 0; i < 8; i++) begin
247                               digest256_d[i] = digest_we_i[i] ? digest_i[i][31:0] : digest256_q[i];
248                             end
249                           end else if (update_digest) begin
250                             for (int i = 0 ; i < 8 ; i++) begin
251                               digest256_d[i] = digest256_q[i] + hash256_q[i];
252                             end
253                           end
254                         end : compute_digest_256
255                     
256                         // update digest_256
257                         always_ff @(posedge clk_i or negedge rst_ni) begin
258                           if (!rst_ni)  digest256_q <= '0;
259                           else          digest256_q <= digest256_d;
260                         end
261                     
262                         // assign digest to output
263                         for (genvar i = 0; i < 8; i++) begin  : gen_assign_digest_256
264                           assign digest_o[i][31:0]  = digest256_q[i];
265                           assign digest_o[i][63:32] = 32'b0;
266                         end
267                       end
268                     
269                       // compute round counter (shared)
270                       always_comb begin : round_counter
271        1/1              round_d = round_q;
           Tests:       T1 T2 T3 
272        1/1              if (!sha_en_i || hash_go) begin
           Tests:       T1 T2 T3 
273        1/1                round_d = '0;
           Tests:       T1 T2 T3 
274        1/1              end else if (run_hash) begin
           Tests:       T1 T2 T4 
275        1/1                if (((round_q[RndWidth256-1:0] == RndWidth256'(unsigned'(NumRound256-1))) &&
           Tests:       T1 T2 T4 
276                              (digest_mode_flag_q == SHA2_256 || !MultimodeEn)) ||
277                              ((round_q == RndWidth512'(unsigned'(NumRound512-1))) &&
278                              ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))) begin
279        1/1                  round_d = '0;
           Tests:       T1 T2 T4 
280                           end else begin
281        1/1                  round_d = round_q + 1;
           Tests:       T1 T2 T4 
282                           end
283                         end
                        MISSING_ELSE
284                       end
285                     
286                       // update round counter (shared)
287                       always_ff @(posedge clk_i or negedge rst_ni) begin
288        2/2              if (!rst_ni) round_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
289        1/1              else         round_q <= round_d;
           Tests:       T1 T2 T3 
290                       end
291                     
292                       // compute w_index (shared)
293        1/1            assign w_index_d = (~sha_en_i || hash_go) ? '0            :  // clear
           Tests:       T1 T2 T3 
294                                          update_w_from_fifo     ? w_index_q + 1 :  // increment
295                                                                   w_index_q;       // keep
296                       // update w_index (shared)
297                       always_ff @(posedge clk_i or negedge rst_ni) begin
298        2/2              if (!rst_ni) w_index_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
299        1/1              else         w_index_q <= w_index_d;
           Tests:       T1 T2 T3 
300                       end
301                     
302                       // ready for a word from the padding buffer in sha2_pad
303        1/1            assign shaf_rready = update_w_from_fifo;
           Tests:       T1 T2 T3 
304                     
305                       always_ff @(posedge clk_i or negedge rst_ni) begin
306        2/2              if (!rst_ni) hash_done_o <= 1'b0;
           Tests:       T1 T2 T3  | T1 T2 T3 
307        1/1              else         hash_done_o <= hash_done_next;
           Tests:       T1 T2 T3 
308                       end
309                     
310                       fifoctl_state_e fifo_st_q, fifo_st_d;
311                     
312        1/1            assign fifo_st_o = fifo_st_q;
           Tests:       T1 T2 T3 
313                     
314                       always_ff @(posedge clk_i or negedge rst_ni) begin
315        2/2              if (!rst_ni) fifo_st_q <= FifoIdle;
           Tests:       T1 T2 T3  | T1 T2 T3 
316        1/1              else         fifo_st_q <= fifo_st_d;
           Tests:       T1 T2 T3 
317                       end
318                     
319                       always_comb begin
320        1/1              fifo_st_d          = FifoIdle;
           Tests:       T1 T2 T3 
321        1/1              update_w_from_fifo = 1'b0;
           Tests:       T1 T2 T3 
322        1/1              hash_done_next     = 1'b0;
           Tests:       T1 T2 T3 
323                     
324        1/1              unique case (fifo_st_q)
           Tests:       T1 T2 T3 
325                           FifoIdle: begin
326        2/2                  if (hash_go) fifo_st_d = FifoLoadFromFifo;
           Tests:       T1 T2 T3  | T1 T2 T4 
327        1/1                  else         fifo_st_d = FifoIdle;
           Tests:       T1 T2 T3 
328                           end
329                     
330                           FifoLoadFromFifo: begin
331        1/1                  if (!shaf_rvalid) begin
           Tests:       T1 T2 T4 
332                               // Wait until it is filled
333        1/1                    fifo_st_d          = FifoLoadFromFifo;
           Tests:       T1 T2 T4 
334        1/1                    update_w_from_fifo = 1'b0;
           Tests:       T1 T2 T4 
335        1/1                  end else if (w_index_q == 4'd 15) begin
           Tests:       T1 T2 T4 
336        1/1                    fifo_st_d = FifoWait;
           Tests:       T1 T2 T4 
337                               // To increment w_index and it rolls over to 0
338        1/1                    update_w_from_fifo = 1'b1;
           Tests:       T1 T2 T4 
339                             end else begin
340        1/1                    fifo_st_d          = FifoLoadFromFifo;
           Tests:       T1 T2 T4 
341        1/1                    update_w_from_fifo = 1'b1;
           Tests:       T1 T2 T4 
342                             end
343                           end
344                     
345                           FifoWait: begin
346        1/1                  if (msg_feed_complete && one_chunk_done) begin
           Tests:       T1 T2 T4 
347        1/1                    fifo_st_d      = FifoIdle;
           Tests:       T1 T2 T4 
348                               // hashing the full message is done
349        1/1                    hash_done_next = 1'b1;
           Tests:       T1 T2 T4 
350        1/1                  end else if (one_chunk_done) begin
           Tests:       T1 T2 T4 
351        1/1                    fifo_st_d      = FifoLoadFromFifo;
           Tests:       T1 T2 T4 
352                             end else begin
353        1/1                    fifo_st_d      = FifoWait;
           Tests:       T1 T2 T4 
354                             end
355                           end
356                     
357                           default: begin
358                             fifo_st_d = FifoIdle;
359                           end
360                         endcase
361                     
362        1/1              if (!sha_en_i)  begin
           Tests:       T1 T2 T3 
363        1/1                fifo_st_d          = FifoIdle;
           Tests:       T1 T2 T3 
364        1/1                update_w_from_fifo = 1'b0;
           Tests:       T1 T2 T3 
365        1/1              end else if (hash_go) begin
           Tests:       T1 T2 T4 
366        1/1                fifo_st_d          = FifoLoadFromFifo;
           Tests:       T1 T2 T4 
367                         end
                        MISSING_ELSE
368                       end
369                     
370                       always_ff @(posedge clk_i or negedge rst_ni) begin
371        2/2              if (!rst_ni) digest_mode_flag_q <= SHA2_None;
           Tests:       T1 T2 T3  | T1 T2 T3 
372        1/1              else         digest_mode_flag_q <= digest_mode_flag_d;
           Tests:       T1 T2 T3 
373                       end
374                     
375                       // SHA control (shared)
376                       typedef enum logic [1:0] {
377                         ShaIdle,
378                         ShaCompress,
379                         ShaUpdateDigest
380                       } sha_st_t;
381                     
382                       sha_st_t sha_st_q, sha_st_d;
383                     
384                       always_ff @(posedge clk_i or negedge rst_ni) begin
385        2/2              if (!rst_ni) sha_st_q <= ShaIdle;
           Tests:       T1 T2 T3  | T1 T2 T3 
386        1/1              else         sha_st_q <= sha_st_d;
           Tests:       T1 T2 T3 
387                       end
388                     
389                       logic sha_en_q;
390                     
391                       always_ff @(posedge clk_i or negedge rst_ni) begin
392        2/2              if (!rst_ni) sha_en_q <= 1'b0;
           Tests:       T1 T2 T3  | T1 T2 T3 
393        1/1              else         sha_en_q <= sha_en_i;
           Tests:       T1 T2 T3 
394                       end
395                     
396        1/1            assign clear_digest = hash_start_i | (~sha_en_i & sha_en_q);
           Tests:       T1 T2 T3 
397                     
398                       always_comb begin
399        1/1              update_digest    = 1'b0;
           Tests:       T1 T2 T3 
400        1/1              calculate_next_w = 1'b0;
           Tests:       T1 T2 T3 
401        1/1              init_hash        = 1'b0;
           Tests:       T1 T2 T3 
402        1/1              run_hash         = 1'b0;
           Tests:       T1 T2 T3 
403        1/1              sha_st_d         = sha_st_q;
           Tests:       T1 T2 T3 
404                     
405        1/1              unique case (sha_st_q)
           Tests:       T1 T2 T3 
406                           ShaIdle: begin
407        1/1                  if (fifo_st_q == FifoWait) begin
           Tests:       T1 T2 T3 
408        1/1                    init_hash = 1'b1;
           Tests:       T1 T2 T4 
409        1/1                    sha_st_d  = ShaCompress;
           Tests:       T1 T2 T4 
410                             end else begin
411        1/1                    sha_st_d  = ShaIdle;
           Tests:       T1 T2 T3 
412                             end
413                           end
414                     
415                           ShaCompress: begin
416        1/1                  run_hash = 1'b1;
           Tests:       T1 T2 T4 
417        1/1                  if (((digest_mode_flag_q == SHA2_256 || ~MultimodeEn) && round_q < 48) ||
           Tests:       T1 T2 T4 
418                                (((digest_mode_flag_q == SHA2_384) ||
419                                (digest_mode_flag_q == SHA2_512)) && round_q < 64)) begin
420        1/1                    calculate_next_w = 1'b1;
           Tests:       T1 T2 T4 
421        1/1                  end else if (one_chunk_done) begin
           Tests:       T1 T2 T4 
422        1/1                    sha_st_d = ShaUpdateDigest;
           Tests:       T1 T2 T4 
423                             end else begin
424        1/1                    sha_st_d = ShaCompress;
           Tests:       T1 T2 T4 
425                             end
426                           end
427                     
428                           ShaUpdateDigest: begin
429        1/1                  update_digest = 1'b1;
           Tests:       T1 T2 T4 
430        1/1                  if (fifo_st_q == FifoWait) begin
           Tests:       T1 T2 T4 
431        0/1     ==>            init_hash = 1'b1;
432        0/1     ==>            sha_st_d  = ShaCompress;
433                             end else begin
434        1/1                    sha_st_d  = ShaIdle;
           Tests:       T1 T2 T4 
435                             end
436                           end
437                     
438                           default: begin
439                             sha_st_d = ShaIdle;
440                           end
441                         endcase
442                     
443        2/2              if (!sha_en_i || hash_go) sha_st_d  = ShaIdle;
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
444                       end
445                     
446                       // Determine whether a digest is being computed for a complete block: when `update_digest` is set,
447                       // this module is not waiting for more data from the FIFO, and `message_length_i` is zero modulo a
448                       // complete block (512 bit for SHA2_256 and 1024 bit for SHA2_384 and SHA2_512).
449        1/1            assign digest_on_blk_o = update_digest && (fifo_st_q == FifoIdle) && (
           Tests:       T1 T2 T3 
450                           (digest_mode_flag_q == SHA2_256                 && message_length_i[8:0] == '0) ||
451                           (digest_mode_flag_q inside {SHA2_384, SHA2_512} && message_length_i[9:0] == '0));
452                     
453        1/1            assign one_chunk_done = ((digest_mode_flag_q == SHA2_256 || ~MultimodeEn)
           Tests:       T1 T2 T3 
454                                               && (round_q == 7'd63)) ? 1'b1 :
455                                               (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
456                                               && (round_q == 7'd79)) ? 1'b1 : 1'b0;
457                     
458                       prim_sha2_pad #(
459                           .MultimodeEn(MultimodeEn)
460                         ) u_pad (
461                         .clk_i,
462                         .rst_ni,
463                         .fifo_rvalid_i,
464                         .fifo_rdata_i,
465                         .fifo_rready_o,
466                         .shaf_rvalid_o (shaf_rvalid), // is set when the 512-bit chunk is ready in the padding buffer
467                         .shaf_rdata_o  (shaf_rdata),
468                         .shaf_rready_i (shaf_rready), // indicates that w is ready for more words from padding buffer
469                         .sha_en_i,
470                         .hash_start_i,
471                         .hash_stop_i,
472                         .hash_continue_i,
473                         .digest_mode_i,
474                         .hash_process_i,
475                         .hash_done_i (hash_done_o),
476                         .message_length_i ({64'b0, message_length_i}), // 128-bit message length per NIST-FIPS-180-4
477                         .msg_feed_complete_o (msg_feed_complete)
478                       );
479                     
480        1/1            assign hash_running_o = init_hash | run_hash | update_digest;
           Tests:       T1 T2 T3 
481                     
482                       // Idle
483        1/1            assign idle_o = (fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && !hash_go;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_sha2

	Total	Covered	Percent
Conditions	145	138	95.17
Logical	145	138	95.17
Non-Logical	0	0
Event	0	0

 LINE       78
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T4

 LINE       80
 EXPRESSION (hash_go ? digest_mode_i : (hash_done_o ? SHA2_None : digest_mode_flag_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       80
 SUB-EXPRESSION (hash_done_o ? SHA2_None : digest_mode_flag_q)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       95
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (((!run_hash)) && update_w_from_fifo)
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       102
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       106
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5

 LINE       106
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T5

 LINE       106
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T4

 LINE       129
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION ((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T4

 LINE       132
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T4

 LINE       132
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T5

 LINE       151
 EXPRESSION (digest_mode_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION (digest_mode_i == SHA2_384)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T5

 LINE       155
 EXPRESSION (digest_mode_i == SHA2_512)
            -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T4

 LINE       163
 EXPRESSION (digest_we_i[i] ? digest_i[i] : gen_multimode.digest_q[i])
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       272
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       293
 EXPRESSION ((((~sha_en_i)) || hash_go) ? '0 : (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q))
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       293
 SUB-EXPRESSION (((~sha_en_i)) || hash_go)
                 ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       293
 SUB-EXPRESSION (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       335
 EXPRESSION (w_index_q == 4'd15)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       346
 EXPRESSION (msg_feed_complete && one_chunk_done)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       396
 EXPRESSION (hash_start_i | (((~sha_en_i)) & sha_en_q))
             ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T4

 LINE       396
 SUB-EXPRESSION (((~sha_en_i)) & sha_en_q)
                 ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       407
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       417
 EXPRESSION 
 Number  Term
      1  (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q < 7'h30)) || 
      2  (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40)))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       417
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q < 7'h30))
                 ---------------------------1--------------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       417
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T4
1	-	Covered	T1,T2,T4

 LINE       417
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       417
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))
                 -----------------------------------1----------------------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       417
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5

 LINE       417
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T5

 LINE       417
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       430
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Not Covered

 LINE       443
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       449
 EXPRESSION 
 Number  Term
      1  update_digest && 
      2  (fifo_st_q == FifoIdle) && 
      3  (((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0)) || ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0))))

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T4

 LINE       449
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       449
 SUB-EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0)) || 
      2  ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0)))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       449
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0))
                 ----------------1---------------    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       449
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       449
 SUB-EXPRESSION (message_length_i[8:0] == '0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       449
 SUB-EXPRESSION ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0))
                 ------------------------1-----------------------    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       449
 SUB-EXPRESSION (message_length_i[9:0] == '0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       453
 EXPRESSION 
 Number  Term
      1  (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q == 7'd63)) ? 1'b1 : ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       453
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q == 7'd63))
                 ---------------------------1--------------------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       453
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T4

 LINE       453
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       453
 SUB-EXPRESSION (round_q == 7'd63)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       453
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0)
                 -----------------------------------------------1----------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       453
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))
                 -----------------------------------1----------------------------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       453
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5

 LINE       453
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       453
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       453
 SUB-EXPRESSION (round_q == 7'd79)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       480
 EXPRESSION (init_hash | run_hash | update_digest)
             ----1----   ----2---   ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	1	0	Covered	T1,T2,T4
1	0	0	Covered	T1,T2,T4

 LINE       483
 EXPRESSION ((fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && ((!hash_go)))
             -----------1-----------    ----------2----------    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T3

 LINE       483
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       483
 SUB-EXPRESSION (sha_st_q == ShaIdle)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : prim_sha2

Summary for FSM :: fifo_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	5	5	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fifo_st_q

---

states	Line No.	Covered	Tests
FifoIdle	320	Covered	T1,T2,T3
FifoLoadFromFifo	326	Covered	T1,T2,T4
FifoWait	336	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
FifoIdle->FifoLoadFromFifo	326	Covered	T1,T2,T4
FifoLoadFromFifo->FifoIdle	320	Covered	T19
FifoLoadFromFifo->FifoWait	336	Covered	T1,T2,T4
FifoWait->FifoIdle	320	Covered	T1,T2,T4
FifoWait->FifoLoadFromFifo	351	Covered	T1,T2,T4

Summary for FSM :: sha_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	5	4	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: sha_st_q

---

states	Line No.	Covered	Tests
ShaCompress	409	Covered	T1,T2,T4
ShaIdle	411	Covered	T1,T2,T3
ShaUpdateDigest	422	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
ShaCompress->ShaIdle	443	Covered	T20,T19
ShaCompress->ShaUpdateDigest	422	Covered	T1,T2,T4
ShaIdle->ShaCompress	409	Covered	T1,T2,T4
ShaUpdateDigest->ShaCompress	432	Not Covered
ShaUpdateDigest->ShaIdle	434	Covered	T1,T2,T4

---

Branch Coverage for Module : prim_sha2

	Line No.	Total	Covered	Percent
Branches		76	70	92.11
TERNARY	80	3	3	100.00
TERNARY	293	3	3	100.00
TERNARY	453	3	3	100.00
IF	272	4	4	100.00
IF	288	2	2	100.00
IF	298	2	2	100.00
IF	306	2	2	100.00
IF	315	2	2	100.00
CASE	324	9	8	88.89
IF	362	3	3	100.00
IF	371	2	2	100.00
IF	385	2	2	100.00
IF	392	2	2	100.00
CASE	405	8	6	75.00
IF	443	2	2	100.00
IF	93	8	7	87.50
IF	117	3	2	66.67
IF	124	6	5	83.33
IF	140	2	2	100.00
IF	147	6	6	100.00
IF	174	2	2	100.00

80           assign digest_mode_flag_d = hash_go     ? digest_mode_i   :    // latch in configured mode
                                                     -1-  
                                                     ==>  
81                                       hash_done_o ? SHA2_None       :    // clear
                                                     -2-  
                                                     ==>  
                                                     ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

293          assign w_index_d = (~sha_en_i || hash_go) ? '0            :  // clear
                                                       -1-  
                                                       ==>  
294                             update_w_from_fifo     ? w_index_q + 1 :  // increment
                                                       -2-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T4

453          assign one_chunk_done = ((digest_mode_flag_q == SHA2_256 || ~MultimodeEn)
                                                                                      
454                                  && (round_q == 7'd63)) ? 1'b1 :
                                                            -1-  
                                                            ==>  
455                                  (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                                                                                                            
456                                  && (round_q == 7'd79)) ? 1'b1 : 1'b0;
                                                            -2-  
                                                            ==>  
                                                            ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

272            if (!sha_en_i || hash_go) begin
               -1-  
273              round_d = '0;
                 ==>
274            end else if (run_hash) begin
                        -2-  
275              if (((round_q[RndWidth256-1:0] == RndWidth256'(unsigned'(NumRound256-1))) &&
                 -3-  
276                 (digest_mode_flag_q == SHA2_256 || !MultimodeEn)) ||
277                 ((round_q == RndWidth512'(unsigned'(NumRound512-1))) &&
278                 ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))) begin
279                round_d = '0;
                   ==>
280              end else begin
281                round_d = round_q + 1;
                   ==>
282              end
283            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T1,T2,T4
0	1	0	Covered	T1,T2,T4
0	0	-	Covered	T1,T2,T4

288            if (!rst_ni) round_q <= '0;
               -1-  
               ==>
289            else         round_q <= round_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

298            if (!rst_ni) w_index_q <= '0;
               -1-  
               ==>
299            else         w_index_q <= w_index_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

306            if (!rst_ni) hash_done_o <= 1'b0;
               -1-  
               ==>
307            else         hash_done_o <= hash_done_next;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

315            if (!rst_ni) fifo_st_q <= FifoIdle;
               -1-                           
               ==>
316            else         fifo_st_q <= fifo_st_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

324            unique case (fifo_st_q)
                      -1-  
325              FifoIdle: begin
326                if (hash_go) fifo_st_d = FifoLoadFromFifo;
                   -2-                                      
                   ==>
327                else         fifo_st_d = FifoIdle;
                   ==>
328              end
329        
330              FifoLoadFromFifo: begin
331                if (!shaf_rvalid) begin
                   -3-  
332                  // Wait until it is filled
333                  fifo_st_d          = FifoLoadFromFifo;
                     ==>
334                  update_w_from_fifo = 1'b0;
335                end else if (w_index_q == 4'd 15) begin
                            -4-  
336                  fifo_st_d = FifoWait;
                     ==>
337                  // To increment w_index and it rolls over to 0
338                  update_w_from_fifo = 1'b1;
339                end else begin
340                  fifo_st_d          = FifoLoadFromFifo;
                     ==>
341                  update_w_from_fifo = 1'b1;
342                end
343              end
344        
345              FifoWait: begin
346                if (msg_feed_complete && one_chunk_done) begin
                   -5-  
347                  fifo_st_d      = FifoIdle;
                     ==>
348                  // hashing the full message is done
349                  hash_done_next = 1'b1;
350                end else if (one_chunk_done) begin
                            -6-  
351                  fifo_st_d      = FifoLoadFromFifo;
                     ==>
352                end else begin
353                  fifo_st_d      = FifoWait;
                     ==>
354                end
355              end
356        
357              default: begin
358                fifo_st_d = FifoIdle;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
FifoIdle	1	-	-	-	-	Covered	T1,T2,T4
FifoIdle	0	-	-	-	-	Covered	T1,T2,T3
FifoLoadFromFifo	-	1	-	-	-	Covered	T1,T2,T4
FifoLoadFromFifo	-	0	1	-	-	Covered	T1,T2,T4
FifoLoadFromFifo	-	0	0	-	-	Covered	T1,T2,T4
FifoWait	-	-	-	1	-	Covered	T1,T2,T4
FifoWait	-	-	-	0	1	Covered	T1,T2,T4
FifoWait	-	-	-	0	0	Covered	T1,T2,T4
default	-	-	-	-	-	Not Covered

362            if (!sha_en_i)  begin
               -1-  
363              fifo_st_d          = FifoIdle;
                 ==>
364              update_w_from_fifo = 1'b0;
365            end else if (hash_go) begin
                        -2-  
366              fifo_st_d          = FifoLoadFromFifo;
                 ==>
367            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T4

371            if (!rst_ni) digest_mode_flag_q <= SHA2_None;
               -1-  
               ==>
372            else         digest_mode_flag_q <= digest_mode_flag_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

385            if (!rst_ni) sha_st_q <= ShaIdle;
               -1-  
               ==>
386            else         sha_st_q <= sha_st_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

392            if (!rst_ni) sha_en_q <= 1'b0;
               -1-  
               ==>
393            else         sha_en_q <= sha_en_i;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

405            unique case (sha_st_q)
                      -1-  
406              ShaIdle: begin
407                if (fifo_st_q == FifoWait) begin
                   -2-                  
408                  init_hash = 1'b1;
                     ==>
409                  sha_st_d  = ShaCompress;
410                end else begin
411                  sha_st_d  = ShaIdle;
                     ==>
412                end
413              end
414        
415              ShaCompress: begin
416                run_hash = 1'b1;
417                if (((digest_mode_flag_q == SHA2_256 || ~MultimodeEn) && round_q < 48) ||
                   -3-  
418                   (((digest_mode_flag_q == SHA2_384) ||
419                   (digest_mode_flag_q == SHA2_512)) && round_q < 64)) begin
420                  calculate_next_w = 1'b1;
                     ==>
421                end else if (one_chunk_done) begin
                            -4-  
422                  sha_st_d = ShaUpdateDigest;
                     ==>
423                end else begin
424                  sha_st_d = ShaCompress;
                     ==>
425                end
426              end
427        
428              ShaUpdateDigest: begin
429                update_digest = 1'b1;
430                if (fifo_st_q == FifoWait) begin
                   -5-                  
431                  init_hash = 1'b1;
                     ==>
432                  sha_st_d  = ShaCompress;
433                end else begin
434                  sha_st_d  = ShaIdle;
                     ==>
435                end
436              end
437        
438              default: begin
439                sha_st_d = ShaIdle;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
ShaIdle	1	-	-	-	Covered	T1,T2,T4
ShaIdle	0	-	-	-	Covered	T1,T2,T3
ShaCompress	-	1	-	-	Covered	T1,T2,T4
ShaCompress	-	0	1	-	Covered	T1,T2,T4
ShaCompress	-	0	0	-	Covered	T1,T2,T4
ShaUpdateDigest	-	-	-	1	Not Covered
ShaUpdateDigest	-	-	-	0	Covered	T1,T2,T4
default	-	-	-	-	Not Covered

443            if (!sha_en_i || hash_go) sha_st_d  = ShaIdle;
               -1-  
               ==>
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

93               if (wipe_secret_i) begin
                 -1-  
94                 w_d = {32{wipe_v_i}};
                   ==>
95               end else if (!sha_en_i || hash_go) begin
                          -2-  
96                 w_d = '0;
                   ==>
97               end else if (!run_hash && update_w_from_fifo) begin
                          -3-                                
98                 // this logic runs at the first stage of SHA: hash not running yet,
99                 // still filling in first 16 words
100                w_d = {shaf_rdata, w_q[15:1]};
                   ==>
101              end else if (calculate_next_w) begin // message scheduling/derivation for last 48/64 rounds
                          -4-  
102                if (digest_mode_flag_q == SHA2_256) begin
                   -5-  
103                  // this computes the next w[16] and shifts out w[0] into compression below
104                  w_d = {{32'b0, calc_w_256(w_q[0][31:0], w_q[1][31:0], w_q[9][31:0],
                     ==>
105                        w_q[14][31:0])}, w_q[15:1]};
106                end else if ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) begin
                            -6-  
107                  w_d = {calc_w_512(w_q[0], w_q[1], w_q[9], w_q[14]), w_q[15:1]};
                     ==>
108                end
                   MISSING_ELSE
                   ==>
109              end else if (run_hash) begin
                          -7-  
110                // just shift-out the words as they get consumed. There's no incoming data.
111                w_d = {ZeroWord, w_q[15:1]};
                   ==>
112              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
1	-	-	-	-	-	-	Covered	T31,T33,T34
0	1	-	-	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	-	-	Covered	T1,T2,T4
0	0	0	1	1	-	-	Covered	T1,T2,T4
0	0	0	1	0	1	-	Covered	T1,T2,T4
0	0	0	1	0	0	-	Not Covered
0	0	0	0	-	-	1	Covered	T1,T2,T4
0	0	0	0	-	-	0	Covered	T1,T2,T4

117              if (!rst_ni)            w_q <= '0;
                 -1-  
                 ==>
118              else if (MultimodeEn)   w_q <= w_d;
                      -2-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

124              if (wipe_secret_i) begin
                 -1-  
125                hash_d = {16{wipe_v_i}};
                   ==>
126              end else if (init_hash) begin
                          -2-  
127                hash_d = digest_q;
                   ==>
128              end else if (run_hash) begin
                          -3-  
129                if (digest_mode_flag_q == SHA2_256) begin
                   -4-  
130                  hash_d = compress_multi_256(w_q[0][31:0],
                     ==>
131                           CubicRootPrime256[round_q[RndWidth256-1:0]], hash_q);
132                end else if ((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384)) begin
                            -5-  
133                  hash_d = compress_512(w_q[0], CubicRootPrime512[round_q], hash_q);
                     ==>
134                end
                   MISSING_ELSE
                   ==>
135              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T31,T33,T34
0	1	-	-	-	Covered	T1,T2,T4
0	0	1	1	-	Covered	T1,T2,T4
0	0	1	0	1	Covered	T1,T2,T4
0	0	1	0	0	Not Covered
0	0	0	-	-	Covered	T1,T2,T3

140              if (!rst_ni)  hash_q <= '0;
                 -1-  
                 ==>
141              else          hash_q <= hash_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

147              if (wipe_secret_i) begin
                 -1-  
148                digest_d = {16{wipe_v_i}};
                   ==>
149              end else if (hash_start_i) begin
                          -2-  
150                for (int i = 0 ; i < 8 ; i++) begin
                   ==>
151                  if (digest_mode_i == SHA2_256) begin
152                    digest_d[i] = {32'b0, InitHash_256[i]};
153                  end else if (digest_mode_i == SHA2_384) begin
154                    digest_d[i] = InitHash_384[i];
155                  end else if (digest_mode_i == SHA2_512) begin
156                    digest_d[i] = InitHash_512[i];
157                  end
158                end
159              end else if (clear_digest) begin
                          -3-  
160                digest_d = '0;
                   ==>
161              end else if (!sha_en_i) begin
                          -4-  
162                for (int i = 0; i < 8; i++) begin
                   ==>
163                  digest_d[i] = digest_we_i[i] ? digest_i[i] : digest_q[i];
164                end
165              end else if (update_digest) begin
                          -5-  
166                for (int i = 0 ; i < 8 ; i++) begin
                   ==>
167                  digest_d[i] = digest_q[i] + hash_q[i];
168                end
169              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T31,T33,T34
0	1	-	-	-	Covered	T1,T2,T4
0	0	1	-	-	Covered	T2,T4,T5
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T4
0	0	0	0	0	Covered	T1,T2,T4

174              if (!rst_ni)  digest_q <= '0;
                 -1-  
                 ==>
175              else          digest_q <= digest_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode

	Line No.	Total	Covered	Percent
TOTAL		139	139	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	92	14	14	100.00
ALWAYS	117	4	4	100.00
ALWAYS	123	10	10	100.00
ALWAYS	140	3	3	100.00
ALWAYS	146	19	19	100.00
ALWAYS	174	3	3	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	271	7	7	100.00
ALWAYS	288	3	3	100.00
CONT_ASSIGN	293	1	1	100.00
ALWAYS	298	3	3	100.00
CONT_ASSIGN	303	1	1	100.00
ALWAYS	306	3	3	100.00
CONT_ASSIGN	312	1	1	100.00
ALWAYS	315	3	3	100.00
ALWAYS	320	26	26	100.00
ALWAYS	371	3	3	100.00
ALWAYS	385	3	3	100.00
ALWAYS	392	3	3	100.00
CONT_ASSIGN	396	1	1	100.00
ALWAYS	399	21	21	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	480	1	1	100.00
CONT_ASSIGN	483	1	1	100.00

77                        // to hash.
78         1/1            assign hash_go = hash_start_i | hash_continue_i;
           Tests:       T1 T2 T3 
79                      
80         1/1            assign digest_mode_flag_d = hash_go     ? digest_mode_i   :    // latch in configured mode
           Tests:       T1 T2 T3 
81                                                    hash_done_o ? SHA2_None       :    // clear
82                                                                  digest_mode_flag_q;  // keep
83                      
84                        if (MultimodeEn) begin : gen_multimode
85                          // datapath signal definitions for multi-mode
86                          sha_word64_t [7:0]  hash_d, hash_q; // a,b,c,d,e,f,g,h
87                          sha_word64_t [15:0] w_d, w_q;
88                          sha_word64_t [7:0]  digest_d, digest_q;
89                      
90                          // compute w
91                          always_comb begin : compute_w_multimode
92         1/1                w_d = w_q;
           Tests:       T1 T2 T3 
93         1/1                if (wipe_secret_i) begin
           Tests:       T1 T2 T3 
94         1/1                  w_d = {32{wipe_v_i}};
           Tests:       T31 T33 T34 
95         1/1                end else if (!sha_en_i || hash_go) begin
           Tests:       T1 T2 T3 
96         1/1                  w_d = '0;
           Tests:       T1 T2 T3 
97         1/1                end else if (!run_hash && update_w_from_fifo) begin
           Tests:       T1 T2 T4 
98                              // this logic runs at the first stage of SHA: hash not running yet,
99                              // still filling in first 16 words
100        1/1                  w_d = {shaf_rdata, w_q[15:1]};
           Tests:       T1 T2 T4 
101        1/1                end else if (calculate_next_w) begin // message scheduling/derivation for last 48/64 rounds
           Tests:       T1 T2 T4 
102        1/1                  if (digest_mode_flag_q == SHA2_256) begin
           Tests:       T1 T2 T4 
103                               // this computes the next w[16] and shifts out w[0] into compression below
104        1/1                    w_d = {{32'b0, calc_w_256(w_q[0][31:0], w_q[1][31:0], w_q[9][31:0],
           Tests:       T1 T2 T4 
105                                     w_q[14][31:0])}, w_q[15:1]};
106        1/1                  end else if ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) begin
           Tests:       T1 T2 T4 
107        1/1                    w_d = {calc_w_512(w_q[0], w_q[1], w_q[9], w_q[14]), w_q[15:1]};
           Tests:       T1 T2 T4 
108                             end
                   ==>  MISSING_ELSE
109        1/1                end else if (run_hash) begin
           Tests:       T1 T2 T4 
110                             // just shift-out the words as they get consumed. There's no incoming data.
111        1/1                  w_d = {ZeroWord, w_q[15:1]};
           Tests:       T1 T2 T4 
112                           end
                        MISSING_ELSE
113                         end : compute_w_multimode
114                     
115                         // update w
116                         always_ff @(posedge clk_i or negedge rst_ni) begin : update_w_multimode
117        2/2                if (!rst_ni)            w_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
118        2/2                else if (MultimodeEn)   w_q <= w_d;
           Tests:       T1 T2 T3  | T1 T2 T3 
                   ==>  MISSING_ELSE
119                         end : update_w_multimode
120                     
121                         // compute hash
122                         always_comb begin : compression_multimode
123        1/1                hash_d = hash_q;
           Tests:       T1 T2 T3 
124        1/1                if (wipe_secret_i) begin
           Tests:       T1 T2 T3 
125        1/1                  hash_d = {16{wipe_v_i}};
           Tests:       T31 T33 T34 
126        1/1                end else if (init_hash) begin
           Tests:       T1 T2 T3 
127        1/1                  hash_d = digest_q;
           Tests:       T1 T2 T4 
128        1/1                end else if (run_hash) begin
           Tests:       T1 T2 T3 
129        1/1                  if (digest_mode_flag_q == SHA2_256) begin
           Tests:       T1 T2 T4 
130        1/1                    hash_d = compress_multi_256(w_q[0][31:0],
           Tests:       T1 T2 T4 
131                                        CubicRootPrime256[round_q[RndWidth256-1:0]], hash_q);
132        1/1                  end else if ((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384)) begin
           Tests:       T1 T2 T4 
133        1/1                    hash_d = compress_512(w_q[0], CubicRootPrime512[round_q], hash_q);
           Tests:       T1 T2 T4 
134                             end
                   ==>  MISSING_ELSE
135                           end
                        MISSING_ELSE
136                         end : compression_multimode
137                     
138                         // update hash
139                         always_ff @(posedge clk_i or negedge rst_ni) begin : update_hash_multimode
140        2/2                if (!rst_ni)  hash_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
141        1/1                else          hash_q <= hash_d;
           Tests:       T1 T2 T3 
142                         end : update_hash_multimode
143                     
144                         // compute digest
145                         always_comb begin : compute_digest_multimode
146        1/1                digest_d = digest_q;
           Tests:       T1 T2 T3 
147        1/1                if (wipe_secret_i) begin
           Tests:       T1 T2 T3 
148        1/1                  digest_d = {16{wipe_v_i}};
           Tests:       T31 T33 T34 
149        1/1                end else if (hash_start_i) begin
           Tests:       T1 T2 T3 
150        1/1                  for (int i = 0 ; i < 8 ; i++) begin
           Tests:       T1 T2 T4 
151        1/1                    if (digest_mode_i == SHA2_256) begin
           Tests:       T1 T2 T4 
152        1/1                      digest_d[i] = {32'b0, InitHash_256[i]};
           Tests:       T1 T2 T4 
153        1/1                    end else if (digest_mode_i == SHA2_384) begin
           Tests:       T1 T2 T4 
154        1/1                      digest_d[i] = InitHash_384[i];
           Tests:       T2 T4 T5 
155        1/1                    end else if (digest_mode_i == SHA2_512) begin
           Tests:       T1 T2 T4 
156        1/1                      digest_d[i] = InitHash_512[i];
           Tests:       T1 T2 T4 
157                               end
                   ==>  MISSING_ELSE
158                             end
159        1/1                end else if (clear_digest) begin
           Tests:       T1 T2 T3 
160        1/1                  digest_d = '0;
           Tests:       T2 T4 T5 
161        1/1                end else if (!sha_en_i) begin
           Tests:       T1 T2 T3 
162        1/1                  for (int i = 0; i < 8; i++) begin
           Tests:       T1 T2 T3 
163        1/1                    digest_d[i] = digest_we_i[i] ? digest_i[i] : digest_q[i];
           Tests:       T1 T2 T3 
164                             end
165        1/1                end else if (update_digest) begin
           Tests:       T1 T2 T4 
166        1/1                  for (int i = 0 ; i < 8 ; i++) begin
           Tests:       T1 T2 T4 
167        1/1                    digest_d[i] = digest_q[i] + hash_q[i];
           Tests:       T1 T2 T4 
168                             end
169                           end
                        MISSING_ELSE
170                         end : compute_digest_multimode
171                     
172                         // update digest
173                         always_ff @(posedge clk_i or negedge rst_ni) begin
174        2/2                if (!rst_ni)  digest_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
175        1/1                else          digest_q <= digest_d;
           Tests:       T1 T2 T3 
176                         end
177                     
178                         // assign digest to output
179        1/1              assign digest_o = digest_q;
           Tests:       T1 T2 T3 
180                     
181                       end else begin : gen_256 // MultimodeEn = 0
182                         // datapath signal definitions for SHA-2 256 only
183                         sha_word32_t        shaf_rdata256;
184                         sha_word32_t [7:0]  hash256_d, hash256_q; // a,b,c,d,e,f,g,h
185                         sha_word32_t [15:0] w256_d, w256_q;
186                         sha_word32_t [7:0]  digest256_d, digest256_q;
187                     
188                         assign shaf_rdata256 = shaf_rdata[31:0];
189                     
190                         always_comb begin : compute_w_256
191                           // ~MultimodeEn
192                           w256_d = w256_q;
193                           if (wipe_secret_i) begin
194                             w256_d = {16{wipe_v_i}};
195                           end else if (!sha_en_i || hash_go) begin
196                             w256_d = '0;
197                           end else if (!run_hash && update_w_from_fifo) begin
198                             // this logic runs at the first stage of SHA: hash not running yet,
199                             // still filling in first 16 words
200                             w256_d = {shaf_rdata256, w256_q[15:1]};
201                           end else if (calculate_next_w) begin // message scheduling/derivation for last 48/64 rounds
202                             w256_d = {calc_w_256(w256_q[0][31:0], w256_q[1][31:0], w256_q[9][31:0],
203                                      w256_q[14][31:0]), w256_q[15:1]};
204                           end else if (run_hash) begin
205                             // just shift-out the words as they get consumed. There's no incoming data.
206                             w256_d = {ZeroWord[31:0], w256_q[15:1]};
207                           end
208                         end : compute_w_256
209                     
210                         // update w_256
211                         always_ff @(posedge clk_i or negedge rst_ni) begin : update_w_256
212                           if (!rst_ni)            w256_q <= '0;
213                           else if (!MultimodeEn)  w256_q <= w256_d;
214                         end : update_w_256
215                     
216                         // compute hash_256
217                         always_comb begin : compression_256
218                           hash256_d = hash256_q;
219                           if (wipe_secret_i) begin
220                             hash256_d = {8{wipe_v_i}};
221                           end else if (init_hash) begin
222                             hash256_d = digest256_q;
223                           end else if (run_hash) begin
224                             hash256_d = compress_256(w256_q[0], CubicRootPrime256[round_q[RndWidth256-1:0]], hash256_q);
225                           end
226                         end : compression_256
227                     
228                         // update hash_256
229                         always_ff @(posedge clk_i or negedge rst_ni) begin : update_hash256
230                           if (!rst_ni) hash256_q <= '0;
231                           else         hash256_q <= hash256_d;
232                         end : update_hash256
233                     
234                         // compute digest_256
235                         always_comb begin : compute_digest_256
236                           digest256_d = digest256_q;
237                           if (wipe_secret_i) begin
238                             digest256_d = {8{wipe_v_i}};
239                           end else if (hash_start_i) begin
240                             for (int i = 0 ; i < 8 ; i++) begin
241                                 digest256_d[i] = InitHash_256[i];
242                             end
243                           end else if (clear_digest) begin
244                             digest256_d = '0;
245                           end else if (!sha_en_i) begin
246                             for (int i = 0; i < 8; i++) begin
247                               digest256_d[i] = digest_we_i[i] ? digest_i[i][31:0] : digest256_q[i];
248                             end
249                           end else if (update_digest) begin
250                             for (int i = 0 ; i < 8 ; i++) begin
251                               digest256_d[i] = digest256_q[i] + hash256_q[i];
252                             end
253                           end
254                         end : compute_digest_256
255                     
256                         // update digest_256
257                         always_ff @(posedge clk_i or negedge rst_ni) begin
258                           if (!rst_ni)  digest256_q <= '0;
259                           else          digest256_q <= digest256_d;
260                         end
261                     
262                         // assign digest to output
263                         for (genvar i = 0; i < 8; i++) begin  : gen_assign_digest_256
264                           assign digest_o[i][31:0]  = digest256_q[i];
265                           assign digest_o[i][63:32] = 32'b0;
266                         end
267                       end
268                     
269                       // compute round counter (shared)
270                       always_comb begin : round_counter
271        1/1              round_d = round_q;
           Tests:       T1 T2 T3 
272        1/1              if (!sha_en_i || hash_go) begin
           Tests:       T1 T2 T3 
273        1/1                round_d = '0;
           Tests:       T1 T2 T3 
274        1/1              end else if (run_hash) begin
           Tests:       T1 T2 T4 
275        1/1                if (((round_q[RndWidth256-1:0] == RndWidth256'(unsigned'(NumRound256-1))) &&
           Tests:       T1 T2 T4 
276                              (digest_mode_flag_q == SHA2_256 || !MultimodeEn)) ||
277                              ((round_q == RndWidth512'(unsigned'(NumRound512-1))) &&
278                              ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))) begin
279        1/1                  round_d = '0;
           Tests:       T1 T2 T4 
280                           end else begin
281        1/1                  round_d = round_q + 1;
           Tests:       T1 T2 T4 
282                           end
283                         end
                        MISSING_ELSE
284                       end
285                     
286                       // update round counter (shared)
287                       always_ff @(posedge clk_i or negedge rst_ni) begin
288        2/2              if (!rst_ni) round_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
289        1/1              else         round_q <= round_d;
           Tests:       T1 T2 T3 
290                       end
291                     
292                       // compute w_index (shared)
293        1/1            assign w_index_d = (~sha_en_i || hash_go) ? '0            :  // clear
           Tests:       T1 T2 T3 
294                                          update_w_from_fifo     ? w_index_q + 1 :  // increment
295                                                                   w_index_q;       // keep
296                       // update w_index (shared)
297                       always_ff @(posedge clk_i or negedge rst_ni) begin
298        2/2              if (!rst_ni) w_index_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
299        1/1              else         w_index_q <= w_index_d;
           Tests:       T1 T2 T3 
300                       end
301                     
302                       // ready for a word from the padding buffer in sha2_pad
303        1/1            assign shaf_rready = update_w_from_fifo;
           Tests:       T1 T2 T3 
304                     
305                       always_ff @(posedge clk_i or negedge rst_ni) begin
306        2/2              if (!rst_ni) hash_done_o <= 1'b0;
           Tests:       T1 T2 T3  | T1 T2 T3 
307        1/1              else         hash_done_o <= hash_done_next;
           Tests:       T1 T2 T3 
308                       end
309                     
310                       fifoctl_state_e fifo_st_q, fifo_st_d;
311                     
312        1/1            assign fifo_st_o = fifo_st_q;
           Tests:       T1 T2 T3 
313                     
314                       always_ff @(posedge clk_i or negedge rst_ni) begin
315        2/2              if (!rst_ni) fifo_st_q <= FifoIdle;
           Tests:       T1 T2 T3  | T1 T2 T3 
316        1/1              else         fifo_st_q <= fifo_st_d;
           Tests:       T1 T2 T3 
317                       end
318                     
319                       always_comb begin
320        1/1              fifo_st_d          = FifoIdle;
           Tests:       T1 T2 T3 
321        1/1              update_w_from_fifo = 1'b0;
           Tests:       T1 T2 T3 
322        1/1              hash_done_next     = 1'b0;
           Tests:       T1 T2 T3 
323                     
324        1/1              unique case (fifo_st_q)
           Tests:       T1 T2 T3 
325                           FifoIdle: begin
326        2/2                  if (hash_go) fifo_st_d = FifoLoadFromFifo;
           Tests:       T1 T2 T3  | T1 T2 T4 
327        1/1                  else         fifo_st_d = FifoIdle;
           Tests:       T1 T2 T3 
328                           end
329                     
330                           FifoLoadFromFifo: begin
331        1/1                  if (!shaf_rvalid) begin
           Tests:       T1 T2 T4 
332                               // Wait until it is filled
333        1/1                    fifo_st_d          = FifoLoadFromFifo;
           Tests:       T1 T2 T4 
334        1/1                    update_w_from_fifo = 1'b0;
           Tests:       T1 T2 T4 
335        1/1                  end else if (w_index_q == 4'd 15) begin
           Tests:       T1 T2 T4 
336        1/1                    fifo_st_d = FifoWait;
           Tests:       T1 T2 T4 
337                               // To increment w_index and it rolls over to 0
338        1/1                    update_w_from_fifo = 1'b1;
           Tests:       T1 T2 T4 
339                             end else begin
340        1/1                    fifo_st_d          = FifoLoadFromFifo;
           Tests:       T1 T2 T4 
341        1/1                    update_w_from_fifo = 1'b1;
           Tests:       T1 T2 T4 
342                             end
343                           end
344                     
345                           FifoWait: begin
346        1/1                  if (msg_feed_complete && one_chunk_done) begin
           Tests:       T1 T2 T4 
347        1/1                    fifo_st_d      = FifoIdle;
           Tests:       T1 T2 T4 
348                               // hashing the full message is done
349        1/1                    hash_done_next = 1'b1;
           Tests:       T1 T2 T4 
350        1/1                  end else if (one_chunk_done) begin
           Tests:       T1 T2 T4 
351        1/1                    fifo_st_d      = FifoLoadFromFifo;
           Tests:       T1 T2 T4 
352                             end else begin
353        1/1                    fifo_st_d      = FifoWait;
           Tests:       T1 T2 T4 
354                             end
355                           end
356                     
357                           default: begin
358                             fifo_st_d = FifoIdle;
Exclude Annotation: VC_COV_UNR
359                           end
360                         endcase
361                     
362        1/1              if (!sha_en_i)  begin
           Tests:       T1 T2 T3 
363        1/1                fifo_st_d          = FifoIdle;
           Tests:       T1 T2 T3 
364        1/1                update_w_from_fifo = 1'b0;
           Tests:       T1 T2 T3 
365        1/1              end else if (hash_go) begin
           Tests:       T1 T2 T4 
366        1/1                fifo_st_d          = FifoLoadFromFifo;
           Tests:       T1 T2 T4 
367                         end
                        MISSING_ELSE
368                       end
369                     
370                       always_ff @(posedge clk_i or negedge rst_ni) begin
371        2/2              if (!rst_ni) digest_mode_flag_q <= SHA2_None;
           Tests:       T1 T2 T3  | T1 T2 T3 
372        1/1              else         digest_mode_flag_q <= digest_mode_flag_d;
           Tests:       T1 T2 T3 
373                       end
374                     
375                       // SHA control (shared)
376                       typedef enum logic [1:0] {
377                         ShaIdle,
378                         ShaCompress,
379                         ShaUpdateDigest
380                       } sha_st_t;
381                     
382                       sha_st_t sha_st_q, sha_st_d;
383                     
384                       always_ff @(posedge clk_i or negedge rst_ni) begin
385        2/2              if (!rst_ni) sha_st_q <= ShaIdle;
           Tests:       T1 T2 T3  | T1 T2 T3 
386        1/1              else         sha_st_q <= sha_st_d;
           Tests:       T1 T2 T3 
387                       end
388                     
389                       logic sha_en_q;
390                     
391                       always_ff @(posedge clk_i or negedge rst_ni) begin
392        2/2              if (!rst_ni) sha_en_q <= 1'b0;
           Tests:       T1 T2 T3  | T1 T2 T3 
393        1/1              else         sha_en_q <= sha_en_i;
           Tests:       T1 T2 T3 
394                       end
395                     
396        1/1            assign clear_digest = hash_start_i | (~sha_en_i & sha_en_q);
           Tests:       T1 T2 T3 
397                     
398                       always_comb begin
399        1/1              update_digest    = 1'b0;
           Tests:       T1 T2 T3 
400        1/1              calculate_next_w = 1'b0;
           Tests:       T1 T2 T3 
401        1/1              init_hash        = 1'b0;
           Tests:       T1 T2 T3 
402        1/1              run_hash         = 1'b0;
           Tests:       T1 T2 T3 
403        1/1              sha_st_d         = sha_st_q;
           Tests:       T1 T2 T3 
404                     
405        1/1              unique case (sha_st_q)
           Tests:       T1 T2 T3 
406                           ShaIdle: begin
407        1/1                  if (fifo_st_q == FifoWait) begin
           Tests:       T1 T2 T3 
408        1/1                    init_hash = 1'b1;
           Tests:       T1 T2 T4 
409        1/1                    sha_st_d  = ShaCompress;
           Tests:       T1 T2 T4 
410                             end else begin
411        1/1                    sha_st_d  = ShaIdle;
           Tests:       T1 T2 T3 
412                             end
413                           end
414                     
415                           ShaCompress: begin
416        1/1                  run_hash = 1'b1;
           Tests:       T1 T2 T4 
417        1/1                  if (((digest_mode_flag_q == SHA2_256 || ~MultimodeEn) && round_q < 48) ||
           Tests:       T1 T2 T4 
418                                (((digest_mode_flag_q == SHA2_384) ||
419                                (digest_mode_flag_q == SHA2_512)) && round_q < 64)) begin
420        1/1                    calculate_next_w = 1'b1;
           Tests:       T1 T2 T4 
421        1/1                  end else if (one_chunk_done) begin
           Tests:       T1 T2 T4 
422        1/1                    sha_st_d = ShaUpdateDigest;
           Tests:       T1 T2 T4 
423                             end else begin
424        1/1                    sha_st_d = ShaCompress;
           Tests:       T1 T2 T4 
425                             end
426                           end
427                     
428                           ShaUpdateDigest: begin
429        1/1                  update_digest = 1'b1;
           Tests:       T1 T2 T4 
430        1/1                  if (fifo_st_q == FifoWait) begin
           Tests:       T1 T2 T4 
431        excluded               init_hash = 1'b1;
Exclude Annotation: VC_COV_UNR
432        excluded               sha_st_d  = ShaCompress;
Exclude Annotation: VC_COV_UNR
433                             end else begin
434        1/1                    sha_st_d  = ShaIdle;
           Tests:       T1 T2 T4 
435                             end
436                           end
437                     
438                           default: begin
439                             sha_st_d = ShaIdle;
Exclude Annotation: VC_COV_UNR
440                           end
441                         endcase
442                     
443        2/2              if (!sha_en_i || hash_go) sha_st_d  = ShaIdle;
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
444                       end
445                     
446                       // Determine whether a digest is being computed for a complete block: when `update_digest` is set,
447                       // this module is not waiting for more data from the FIFO, and `message_length_i` is zero modulo a
448                       // complete block (512 bit for SHA2_256 and 1024 bit for SHA2_384 and SHA2_512).
449        1/1            assign digest_on_blk_o = update_digest && (fifo_st_q == FifoIdle) && (
           Tests:       T1 T2 T3 
450                           (digest_mode_flag_q == SHA2_256                 && message_length_i[8:0] == '0) ||
451                           (digest_mode_flag_q inside {SHA2_384, SHA2_512} && message_length_i[9:0] == '0));
452                     
453        1/1            assign one_chunk_done = ((digest_mode_flag_q == SHA2_256 || ~MultimodeEn)
           Tests:       T1 T2 T3 
454                                               && (round_q == 7'd63)) ? 1'b1 :
455                                               (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
456                                               && (round_q == 7'd79)) ? 1'b1 : 1'b0;
457                     
458                       prim_sha2_pad #(
459                           .MultimodeEn(MultimodeEn)
460                         ) u_pad (
461                         .clk_i,
462                         .rst_ni,
463                         .fifo_rvalid_i,
464                         .fifo_rdata_i,
465                         .fifo_rready_o,
466                         .shaf_rvalid_o (shaf_rvalid), // is set when the 512-bit chunk is ready in the padding buffer
467                         .shaf_rdata_o  (shaf_rdata),
468                         .shaf_rready_i (shaf_rready), // indicates that w is ready for more words from padding buffer
469                         .sha_en_i,
470                         .hash_start_i,
471                         .hash_stop_i,
472                         .hash_continue_i,
473                         .digest_mode_i,
474                         .hash_process_i,
475                         .hash_done_i (hash_done_o),
476                         .message_length_i ({64'b0, message_length_i}), // 128-bit message length per NIST-FIPS-180-4
477                         .msg_feed_complete_o (msg_feed_complete)
478                       );
479                     
480        1/1            assign hash_running_o = init_hash | run_hash | update_digest;
           Tests:       T1 T2 T3 
481                     
482                       // Idle
483        1/1            assign idle_o = (fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && !hash_go;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode

	Total	Covered	Percent
Conditions	141	138	97.87
Logical	141	138	97.87
Non-Logical	0	0
Event	0	0

 LINE       78
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T4

 LINE       80
 EXPRESSION (hash_go ? digest_mode_i : (hash_done_o ? SHA2_None : digest_mode_flag_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       80
 SUB-EXPRESSION (hash_done_o ? SHA2_None : digest_mode_flag_q)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       95
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (((!run_hash)) && update_w_from_fifo)
             ------1------    ---------2--------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       102
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       106
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Excluded		VC_COV_UNR
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5

 LINE       106
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T5

 LINE       106
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T4

 LINE       129
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION ((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T4

 LINE       132
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T4

 LINE       132
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T5

 LINE       151
 EXPRESSION (digest_mode_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       153
 EXPRESSION (digest_mode_i == SHA2_384)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T5

 LINE       155
 EXPRESSION (digest_mode_i == SHA2_512)
            -------------1-------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T2,T4

 LINE       163
 EXPRESSION (digest_we_i[i] ? digest_i[i] : gen_multimode.digest_q[i])
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       272
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       293
 EXPRESSION ((((~sha_en_i)) || hash_go) ? '0 : (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q))
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       293
 SUB-EXPRESSION (((~sha_en_i)) || hash_go)
                 ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       293
 SUB-EXPRESSION (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       335
 EXPRESSION (w_index_q == 4'd15)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       346
 EXPRESSION (msg_feed_complete && one_chunk_done)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       396
 EXPRESSION (hash_start_i | (((~sha_en_i)) & sha_en_q))
             ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T4

 LINE       396
 SUB-EXPRESSION (((~sha_en_i)) & sha_en_q)
                 ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       407
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       417
 EXPRESSION 
 Number  Term
      1  (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q < 7'h30)) || 
      2  (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40)))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       417
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q < 7'h30))
                 ---------------------------1--------------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       417
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T4
1	-	Covered	T1,T2,T4

 LINE       417
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       417
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))
                 -----------------------------------1----------------------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       417
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5

 LINE       417
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T5

 LINE       417
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       430
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T4
1	Excluded		VC_COV_UNR

 LINE       443
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       449
 EXPRESSION 
 Number  Term
      1  update_digest && 
      2  (fifo_st_q == FifoIdle) && 
      3  (((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0)) || ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0))))

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T4

 LINE       449
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       449
 SUB-EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0)) || 
      2  ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0)))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       449
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0))
                 ----------------1---------------    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       449
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       449
 SUB-EXPRESSION (message_length_i[8:0] == '0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       449
 SUB-EXPRESSION ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0))
                 ------------------------1-----------------------    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       449
 SUB-EXPRESSION (message_length_i[9:0] == '0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       453
 EXPRESSION 
 Number  Term
      1  (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q == 7'd63)) ? 1'b1 : ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       453
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q == 7'd63))
                 ---------------------------1--------------------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       453
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T4

 LINE       453
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       453
 SUB-EXPRESSION (round_q == 7'd63)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       453
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0)
                 -----------------------------------------------1----------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       453
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))
                 -----------------------------------1----------------------------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       453
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5

 LINE       453
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       453
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       453
 SUB-EXPRESSION (round_q == 7'd79)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       480
 EXPRESSION (init_hash | run_hash | update_digest)
             ----1----   ----2---   ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	1	0	Covered	T1,T2,T4
1	0	0	Covered	T1,T2,T4

 LINE       483
 EXPRESSION ((fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && ((!hash_go)))
             -----------1-----------    ----------2----------    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T3

 LINE       483
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       483
 SUB-EXPRESSION (sha_st_q == ShaIdle)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode

Summary for FSM :: fifo_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	5	5	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fifo_st_q

---

states	Line No.	Covered	Tests
FifoIdle	320	Covered	T1,T2,T3
FifoLoadFromFifo	326	Covered	T1,T2,T4
FifoWait	336	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
FifoIdle->FifoLoadFromFifo	326	Covered	T1,T2,T4
FifoLoadFromFifo->FifoIdle	320	Covered	T19
FifoLoadFromFifo->FifoWait	336	Covered	T1,T2,T4
FifoWait->FifoIdle	320	Covered	T1,T2,T4
FifoWait->FifoLoadFromFifo	351	Covered	T1,T2,T4

Summary for FSM :: sha_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: sha_st_q

---

states	Line No.	Covered	Tests
ShaCompress	409	Covered	T1,T2,T4
ShaIdle	411	Covered	T1,T2,T3
ShaUpdateDigest	422	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
ShaCompress->ShaIdle	443	Covered	T20,T19
ShaCompress->ShaUpdateDigest	422	Covered	T1,T2,T4
ShaIdle->ShaCompress	409	Covered	T1,T2,T4
ShaUpdateDigest->ShaCompress	432	Excluded		VC_COV_UNR
ShaUpdateDigest->ShaIdle	434	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode

	Line No.	Total	Covered	Percent
Branches		71	70	98.59
TERNARY	80	3	3	100.00
TERNARY	293	3	3	100.00
TERNARY	453	3	3	100.00
IF	272	4	4	100.00
IF	288	2	2	100.00
IF	298	2	2	100.00
IF	306	2	2	100.00
IF	315	2	2	100.00
CASE	324	8	8	100.00
IF	362	3	3	100.00
IF	371	2	2	100.00
IF	385	2	2	100.00
IF	392	2	2	100.00
CASE	405	6	6	100.00
IF	443	2	2	100.00
IF	93	7	7	100.00
IF	117	2	2	100.00
IF	124	6	5	83.33
IF	140	2	2	100.00
IF	147	6	6	100.00
IF	174	2	2	100.00

80           assign digest_mode_flag_d = hash_go     ? digest_mode_i   :    // latch in configured mode
                                                     -1-  
                                                     ==>  
81                                       hash_done_o ? SHA2_None       :    // clear
                                                     -2-  
                                                     ==>  
                                                     ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

293          assign w_index_d = (~sha_en_i || hash_go) ? '0            :  // clear
                                                       -1-  
                                                       ==>  
294                             update_w_from_fifo     ? w_index_q + 1 :  // increment
                                                       -2-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T4

453          assign one_chunk_done = ((digest_mode_flag_q == SHA2_256 || ~MultimodeEn)
                                                                                      
454                                  && (round_q == 7'd63)) ? 1'b1 :
                                                            -1-  
                                                            ==>  
455                                  (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                                                                                                            
456                                  && (round_q == 7'd79)) ? 1'b1 : 1'b0;
                                                            -2-  
                                                            ==>  
                                                            ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

272            if (!sha_en_i || hash_go) begin
               -1-  
273              round_d = '0;
                 ==>
274            end else if (run_hash) begin
                        -2-  
275              if (((round_q[RndWidth256-1:0] == RndWidth256'(unsigned'(NumRound256-1))) &&
                 -3-  
276                 (digest_mode_flag_q == SHA2_256 || !MultimodeEn)) ||
277                 ((round_q == RndWidth512'(unsigned'(NumRound512-1))) &&
278                 ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))) begin
279                round_d = '0;
                   ==>
280              end else begin
281                round_d = round_q + 1;
                   ==>
282              end
283            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T1,T2,T4
0	1	0	Covered	T1,T2,T4
0	0	-	Covered	T1,T2,T4

288            if (!rst_ni) round_q <= '0;
               -1-  
               ==>
289            else         round_q <= round_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

298            if (!rst_ni) w_index_q <= '0;
               -1-  
               ==>
299            else         w_index_q <= w_index_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

306            if (!rst_ni) hash_done_o <= 1'b0;
               -1-  
               ==>
307            else         hash_done_o <= hash_done_next;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

315            if (!rst_ni) fifo_st_q <= FifoIdle;
               -1-                           
               ==>
316            else         fifo_st_q <= fifo_st_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

324            unique case (fifo_st_q)
                      -1-  
325              FifoIdle: begin
326                if (hash_go) fifo_st_d = FifoLoadFromFifo;
                   -2-                                      
                   ==>
327                else         fifo_st_d = FifoIdle;
                   ==>
328              end
329        
330              FifoLoadFromFifo: begin
331                if (!shaf_rvalid) begin
                   -3-  
332                  // Wait until it is filled
333                  fifo_st_d          = FifoLoadFromFifo;
                     ==>
334                  update_w_from_fifo = 1'b0;
335                end else if (w_index_q == 4'd 15) begin
                            -4-  
336                  fifo_st_d = FifoWait;
                     ==>
337                  // To increment w_index and it rolls over to 0
338                  update_w_from_fifo = 1'b1;
339                end else begin
340                  fifo_st_d          = FifoLoadFromFifo;
                     ==>
341                  update_w_from_fifo = 1'b1;
342                end
343              end
344        
345              FifoWait: begin
346                if (msg_feed_complete && one_chunk_done) begin
                   -5-  
347                  fifo_st_d      = FifoIdle;
                     ==>
348                  // hashing the full message is done
349                  hash_done_next = 1'b1;
350                end else if (one_chunk_done) begin
                            -6-  
351                  fifo_st_d      = FifoLoadFromFifo;
                     ==>
352                end else begin
353                  fifo_st_d      = FifoWait;
                     ==>
354                end
355              end
356        
357              default: begin
358                fifo_st_d = FifoIdle;
                   ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests	Exclude Annotation
FifoIdle	1	-	-	-	-	Covered	T1,T2,T4
FifoIdle	0	-	-	-	-	Covered	T1,T2,T3
FifoLoadFromFifo	-	1	-	-	-	Covered	T1,T2,T4
FifoLoadFromFifo	-	0	1	-	-	Covered	T1,T2,T4
FifoLoadFromFifo	-	0	0	-	-	Covered	T1,T2,T4
FifoWait	-	-	-	1	-	Covered	T1,T2,T4
FifoWait	-	-	-	0	1	Covered	T1,T2,T4
FifoWait	-	-	-	0	0	Covered	T1,T2,T4
default	-	-	-	-	-	Excluded		VC_COV_UNR

362            if (!sha_en_i)  begin
               -1-  
363              fifo_st_d          = FifoIdle;
                 ==>
364              update_w_from_fifo = 1'b0;
365            end else if (hash_go) begin
                        -2-  
366              fifo_st_d          = FifoLoadFromFifo;
                 ==>
367            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T4

371            if (!rst_ni) digest_mode_flag_q <= SHA2_None;
               -1-  
               ==>
372            else         digest_mode_flag_q <= digest_mode_flag_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

385            if (!rst_ni) sha_st_q <= ShaIdle;
               -1-  
               ==>
386            else         sha_st_q <= sha_st_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

392            if (!rst_ni) sha_en_q <= 1'b0;
               -1-  
               ==>
393            else         sha_en_q <= sha_en_i;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

405            unique case (sha_st_q)
                      -1-  
406              ShaIdle: begin
407                if (fifo_st_q == FifoWait) begin
                   -2-                  
408                  init_hash = 1'b1;
                     ==>
409                  sha_st_d  = ShaCompress;
410                end else begin
411                  sha_st_d  = ShaIdle;
                     ==>
412                end
413              end
414        
415              ShaCompress: begin
416                run_hash = 1'b1;
417                if (((digest_mode_flag_q == SHA2_256 || ~MultimodeEn) && round_q < 48) ||
                   -3-  
418                   (((digest_mode_flag_q == SHA2_384) ||
419                   (digest_mode_flag_q == SHA2_512)) && round_q < 64)) begin
420                  calculate_next_w = 1'b1;
                     ==>
421                end else if (one_chunk_done) begin
                            -4-  
422                  sha_st_d = ShaUpdateDigest;
                     ==>
423                end else begin
424                  sha_st_d = ShaCompress;
                     ==>
425                end
426              end
427        
428              ShaUpdateDigest: begin
429                update_digest = 1'b1;
430                if (fifo_st_q == FifoWait) begin
                   -5-                  
431                  init_hash = 1'b1;
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
432                  sha_st_d  = ShaCompress;
433                end else begin
434                  sha_st_d  = ShaIdle;
                     ==>
435                end
436              end
437        
438              default: begin
439                sha_st_d = ShaIdle;
                   ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests	Exclude Annotation
ShaIdle	1	-	-	-	Covered	T1,T2,T4
ShaIdle	0	-	-	-	Covered	T1,T2,T3
ShaCompress	-	1	-	-	Covered	T1,T2,T4
ShaCompress	-	0	1	-	Covered	T1,T2,T4
ShaCompress	-	0	0	-	Covered	T1,T2,T4
ShaUpdateDigest	-	-	-	1	Excluded		VC_COV_UNR
ShaUpdateDigest	-	-	-	0	Covered	T1,T2,T4
default	-	-	-	-	Excluded		VC_COV_UNR

443            if (!sha_en_i || hash_go) sha_st_d  = ShaIdle;
               -1-  
               ==>
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

93               if (wipe_secret_i) begin
                 -1-  
94                 w_d = {32{wipe_v_i}};
                   ==>
95               end else if (!sha_en_i || hash_go) begin
                          -2-  
96                 w_d = '0;
                   ==>
97               end else if (!run_hash && update_w_from_fifo) begin
                          -3-                                
98                 // this logic runs at the first stage of SHA: hash not running yet,
99                 // still filling in first 16 words
100                w_d = {shaf_rdata, w_q[15:1]};
                   ==>
101              end else if (calculate_next_w) begin // message scheduling/derivation for last 48/64 rounds
                          -4-  
102                if (digest_mode_flag_q == SHA2_256) begin
                   -5-  
103                  // this computes the next w[16] and shifts out w[0] into compression below
104                  w_d = {{32'b0, calc_w_256(w_q[0][31:0], w_q[1][31:0], w_q[9][31:0],
                     ==>
105                        w_q[14][31:0])}, w_q[15:1]};
106                end else if ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) begin
                            -6-  
107                  w_d = {calc_w_512(w_q[0], w_q[1], w_q[9], w_q[14]), w_q[15:1]};
                     ==>
108                end
                   MISSING_ELSE
                   ==> (Excluded)
Exclude Annotation: VC_COV_UNR
109              end else if (run_hash) begin
                          -7-  
110                // just shift-out the words as they get consumed. There's no incoming data.
111                w_d = {ZeroWord, w_q[15:1]};
                   ==>
112              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests	Exclude Annotation
1	-	-	-	-	-	-	Covered	T31,T33,T34
0	1	-	-	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	-	-	Covered	T1,T2,T4
0	0	0	1	1	-	-	Covered	T1,T2,T4
0	0	0	1	0	1	-	Covered	T1,T2,T4
0	0	0	1	0	0	-	Excluded		VC_COV_UNR
0	0	0	0	-	-	1	Covered	T1,T2,T4
0	0	0	0	-	-	0	Covered	T1,T2,T4

117              if (!rst_ni)            w_q <= '0;
                 -1-  
                 ==>
118              else if (MultimodeEn)   w_q <= w_d;
                      -2-  
                 ==>
                 MISSING_ELSE
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded		VC_COV_UNR

124              if (wipe_secret_i) begin
                 -1-  
125                hash_d = {16{wipe_v_i}};
                   ==>
126              end else if (init_hash) begin
                          -2-  
127                hash_d = digest_q;
                   ==>
128              end else if (run_hash) begin
                          -3-  
129                if (digest_mode_flag_q == SHA2_256) begin
                   -4-  
130                  hash_d = compress_multi_256(w_q[0][31:0],
                     ==>
131                           CubicRootPrime256[round_q[RndWidth256-1:0]], hash_q);
132                end else if ((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384)) begin
                            -5-  
133                  hash_d = compress_512(w_q[0], CubicRootPrime512[round_q], hash_q);
                     ==>
134                end
                   MISSING_ELSE
                   ==>
135              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T31,T33,T34
0	1	-	-	-	Covered	T1,T2,T4
0	0	1	1	-	Covered	T1,T2,T4
0	0	1	0	1	Covered	T1,T2,T4
0	0	1	0	0	Not Covered
0	0	0	-	-	Covered	T1,T2,T3

140              if (!rst_ni)  hash_q <= '0;
                 -1-  
                 ==>
141              else          hash_q <= hash_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

147              if (wipe_secret_i) begin
                 -1-  
148                digest_d = {16{wipe_v_i}};
                   ==>
149              end else if (hash_start_i) begin
                          -2-  
150                for (int i = 0 ; i < 8 ; i++) begin
                   ==>
151                  if (digest_mode_i == SHA2_256) begin
152                    digest_d[i] = {32'b0, InitHash_256[i]};
153                  end else if (digest_mode_i == SHA2_384) begin
154                    digest_d[i] = InitHash_384[i];
155                  end else if (digest_mode_i == SHA2_512) begin
156                    digest_d[i] = InitHash_512[i];
157                  end
158                end
159              end else if (clear_digest) begin
                          -3-  
160                digest_d = '0;
                   ==>
161              end else if (!sha_en_i) begin
                          -4-  
162                for (int i = 0; i < 8; i++) begin
                   ==>
163                  digest_d[i] = digest_we_i[i] ? digest_i[i] : digest_q[i];
164                end
165              end else if (update_digest) begin
                          -5-  
166                for (int i = 0 ; i < 8 ; i++) begin
                   ==>
167                  digest_d[i] = digest_q[i] + hash_q[i];
168                end
169              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T31,T33,T34
0	1	-	-	-	Covered	T1,T2,T4
0	0	1	-	-	Covered	T2,T4,T5
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T4
0	0	0	0	0	Covered	T1,T2,T4

174              if (!rst_ni)  digest_q <= '0;
                 -1-  
                 ==>
175              else          digest_q <= digest_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3