Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36364571	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

34635376

1

T1

58448

T2

1

T22

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	33732161	1			T1	49186		T2	1		T3	1
values[0x0]	17488452	1			T1	28804		T2	1		T22	12
values[0x1]	19779334	1			T1	30324		T2	1		T22	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27996874	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

43003073

1

T1

69847

T2

1

T22

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	318771	1			T4	9		T23	51		T6	75
valid_sources[0x01]	223325	1			T4	2		T23	63		T6	62
valid_sources[0x02]	225670	1			T4	3		T23	43		T6	39
valid_sources[0x03]	266779	1			T4	5		T23	21		T6	44
valid_sources[0x04]	270085	1			T4	12		T23	38		T6	48
valid_sources[0x05]	226537	1			T4	1		T23	87		T6	37
valid_sources[0x06]	226307	1			T4	5		T23	74		T6	50
valid_sources[0x07]	288621	1			T4	3		T23	42		T6	51
valid_sources[0x08]	301019	1			T23	66		T6	37		T7	2
valid_sources[0x09]	365405	1			T4	4		T23	58		T6	50
valid_sources[0x0a]	225166	1			T4	6		T23	44		T6	63
valid_sources[0x0b]	237426	1			T4	10		T23	68		T6	39
valid_sources[0x0c]	227730	1			T23	49		T6	44		T7	1
valid_sources[0x0d]	224436	1			T4	6		T23	53		T6	50
valid_sources[0x0e]	227712	1			T4	4		T23	51		T6	35
valid_sources[0x0f]	223104	1			T4	7		T23	51		T6	52
valid_sources[0x10]	230327	1			T4	3		T23	72		T6	39
valid_sources[0x11]	366537	1			T4	7		T23	47		T6	43
valid_sources[0x12]	226940	1			T23	36		T6	44		T7	1
valid_sources[0x13]	227863	1			T4	5		T23	47		T6	40
valid_sources[0x14]	291931	1			T4	11		T23	64		T6	51
valid_sources[0x15]	226959	1			T2	1		T4	4		T23	71
valid_sources[0x16]	224566	1			T4	8		T23	62		T6	52
valid_sources[0x17]	238435	1			T4	4		T23	56		T6	57
valid_sources[0x18]	225617	1			T4	1		T23	22		T6	38
valid_sources[0x19]	226712	1			T4	4		T23	36		T6	73
valid_sources[0x1a]	236011	1			T4	1		T23	34		T6	34
valid_sources[0x1b]	226683	1			T4	1		T23	59		T6	56
valid_sources[0x1c]	231464	1			T23	47		T6	43		T7	5
valid_sources[0x1d]	266792	1			T4	3		T23	135		T6	38
valid_sources[0x1e]	263368	1			T22	4		T4	6		T23	62
valid_sources[0x1f]	225320	1			T4	6		T23	52		T6	45
valid_sources[0x20]	225163	1			T4	2		T23	70		T6	27
valid_sources[0x21]	295617	1			T23	32		T6	54		T7	3
valid_sources[0x22]	233975	1			T4	2		T23	51		T6	55
valid_sources[0x23]	225355	1			T4	2		T23	36		T6	38
valid_sources[0x24]	224920	1			T4	3		T23	52		T6	41
valid_sources[0x25]	248864	1			T4	6		T23	82		T6	43
valid_sources[0x26]	232924	1			T4	13		T23	61		T6	38
valid_sources[0x27]	288840	1			T4	4		T23	36		T6	36
valid_sources[0x28]	226190	1			T4	4		T23	44		T6	33
valid_sources[0x29]	227321	1			T4	1		T23	79		T6	39
valid_sources[0x2a]	225381	1			T4	5		T23	28		T6	48
valid_sources[0x2b]	226185	1			T4	5		T23	57		T6	36
valid_sources[0x2c]	223808	1			T2	1		T4	19		T23	36
valid_sources[0x2d]	229743	1			T4	5		T23	70		T6	32
valid_sources[0x2e]	224383	1			T4	2		T23	71		T6	37
valid_sources[0x2f]	235101	1			T4	7		T23	51		T6	52
valid_sources[0x30]	226448	1			T4	4		T23	60		T6	57
valid_sources[0x31]	235086	1			T4	2		T23	47		T6	37
valid_sources[0x32]	420790	1			T4	3		T5	9753		T23	57
valid_sources[0x33]	223370	1			T4	6		T23	45		T6	49
valid_sources[0x34]	225340	1			T4	1		T23	54		T6	48
valid_sources[0x35]	223682	1			T4	13		T23	39		T6	48
valid_sources[0x36]	231772	1			T4	1		T23	48		T6	31
valid_sources[0x37]	384848	1			T23	21		T6	44		T7	4
valid_sources[0x38]	619077	1			T3	1		T23	53		T6	40
valid_sources[0x39]	226642	1			T4	8		T23	46		T6	65
valid_sources[0x3a]	1315850	1			T4	1		T23	67		T6	39
valid_sources[0x3b]	552744	1			T4	2		T23	46		T6	37
valid_sources[0x3c]	235149	1			T4	3		T23	80		T6	47
valid_sources[0x3d]	227870	1			T4	6		T23	58		T6	44
valid_sources[0x3e]	223984	1			T4	10		T23	22		T6	46
valid_sources[0x3f]	224587	1			T23	51		T6	42		T7	3
valid_sources[0x40]	281010	1			T4	7		T23	90		T6	40
valid_sources[0x41]	224835	1			T4	2		T23	38		T6	32
valid_sources[0x42]	231712	1			T4	6		T23	22		T6	53
valid_sources[0x43]	223254	1			T4	7		T23	63		T6	57
valid_sources[0x44]	224364	1			T4	3		T23	40		T6	56
valid_sources[0x45]	294946	1			T4	5		T23	68		T6	55
valid_sources[0x46]	226992	1			T4	3		T23	63		T6	50
valid_sources[0x47]	224834	1			T23	65		T6	52		T7	1
valid_sources[0x48]	224965	1			T4	2		T23	45		T6	46
valid_sources[0x49]	289514	1			T4	1		T23	38		T6	58
valid_sources[0x4a]	226173	1			T4	1		T23	15		T6	31
valid_sources[0x4b]	227460	1			T4	4		T23	32		T6	55
valid_sources[0x4c]	225164	1			T4	3		T23	51		T6	42
valid_sources[0x4d]	226534	1			T4	2		T23	97		T6	34
valid_sources[0x4e]	223958	1			T4	5		T23	67		T6	40
valid_sources[0x4f]	223747	1			T4	6		T23	51		T6	38
valid_sources[0x50]	375470	1			T22	2		T4	5		T23	64
valid_sources[0x51]	224190	1			T4	2		T23	72		T6	55
valid_sources[0x52]	355687	1			T27	1		T4	8		T23	44
valid_sources[0x53]	260791	1			T4	1		T23	44		T6	43
valid_sources[0x54]	510527	1			T4	5		T23	32		T6	39
valid_sources[0x55]	226963	1			T4	7		T23	58		T6	40
valid_sources[0x56]	250118	1			T4	2		T23	40		T6	34
valid_sources[0x57]	226030	1			T4	1		T23	58		T6	48
valid_sources[0x58]	225503	1			T23	86		T6	56		T7	2
valid_sources[0x59]	226708	1			T4	6		T23	38		T6	27
valid_sources[0x5a]	278532	1			T4	1		T23	32		T6	43
valid_sources[0x5b]	225340	1			T4	4		T23	37		T6	35
valid_sources[0x5c]	226145	1			T4	10		T23	48		T6	46
valid_sources[0x5d]	224438	1			T4	1		T23	48		T6	60
valid_sources[0x5e]	224406	1			T4	5		T23	41		T6	56
valid_sources[0x5f]	224900	1			T22	7		T4	3		T23	86
valid_sources[0x60]	247375	1			T4	1		T23	58		T6	50
valid_sources[0x61]	238253	1			T4	9		T23	41		T6	57
valid_sources[0x62]	232294	1			T4	4		T23	89		T6	42
valid_sources[0x63]	285306	1			T23	63		T6	54		T9	66
valid_sources[0x64]	224211	1			T23	34		T6	37		T7	1
valid_sources[0x65]	315951	1			T4	5		T23	71		T6	34
valid_sources[0x66]	274960	1			T4	6		T23	53		T6	57
valid_sources[0x67]	280933	1			T4	1		T23	71		T6	34
valid_sources[0x68]	264147	1			T4	6		T23	33		T6	30
valid_sources[0x69]	272183	1			T4	5		T23	89		T6	47
valid_sources[0x6a]	226310	1			T4	9		T23	80		T6	43
valid_sources[0x6b]	646523	1			T4	1		T23	31		T6	34
valid_sources[0x6c]	226080	1			T4	6		T23	39		T6	50
valid_sources[0x6d]	224063	1			T4	3		T23	47		T6	29
valid_sources[0x6e]	231226	1			T4	9		T23	49		T6	56
valid_sources[0x6f]	501952	1			T4	2		T23	61		T6	44
valid_sources[0x70]	225576	1			T4	4		T23	52		T6	51
valid_sources[0x71]	225467	1			T4	9		T23	41		T6	52
valid_sources[0x72]	226261	1			T4	2		T23	48		T6	53
valid_sources[0x73]	235221	1			T4	2		T23	36		T6	53
valid_sources[0x74]	239949	1			T4	5		T23	40		T6	44
valid_sources[0x75]	224931	1			T4	5		T23	71		T6	41
valid_sources[0x76]	224499	1			T4	8		T23	36		T6	35
valid_sources[0x77]	222845	1			T4	2		T23	74		T6	43
valid_sources[0x78]	227606	1			T4	8		T23	86		T6	47
valid_sources[0x79]	224694	1			T4	8		T23	51		T6	57
valid_sources[0x7a]	568976	1			T4	4		T23	34		T6	54
valid_sources[0x7b]	225918	1			T4	4		T23	33		T6	27
valid_sources[0x7c]	224763	1			T4	2		T23	64		T6	40
valid_sources[0x7d]	225971	1			T4	4		T23	30		T6	38
valid_sources[0x7e]	269411	1			T23	73		T6	53		T7	2
valid_sources[0x7f]	226200	1			T22	1		T4	3		T23	48
valid_sources[0x80]	229120	1			T4	2		T23	35		T6	35

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16693115

1

T1

24494

T4

269

T5

2356

values[0x0]

all_enables

biggest_size

9667670

1

T1

17969

T2

1

T22

1

values[0x1]

all_enables

biggest_size

8274591

1

T1

15985

T22

4

T4

182