Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

38858366

1

T1

49866

T2

2

T3

1

full_word

34796289

1

T1

58448

T2

1

T22

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	73654245	1			T1	108314		T2	3		T3	1
auto[TlIntgErrCmd]	142	1			T57	4		T61	6		T62	8
auto[TlIntgErrData]	139	1			T57	3		T61	7		T62	9
auto[TlIntgErrBoth]	129	1			T57	3		T61	7		T62	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34561950

1

T1

49186

T2

1

T3

1

auto[1]

39092705

1

T1

59128

T2

2

T22

22

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17805280	1			T1	24692		T2	1		T3	1
auto[TlIntgErrNone]	partial	auto[1]	21052717	1			T1	25174		T2	1		T22	17
auto[TlIntgErrNone]	full_word	auto[0]	16756482	1			T1	24494		T4	269		T5	2356
auto[TlIntgErrNone]	full_word	auto[1]	18039766	1			T1	33954		T2	1		T22	5
auto[TlIntgErrCmd]	partial	auto[0]	57	1			T57	2		T61	1		T62	1
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T57	2		T61	2		T62	7
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T61	1		T147	2		T148	2
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T61	2		T149	1		T148	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T57	2		T61	1		T62	2
auto[TlIntgErrData]	partial	auto[1]	72	1			T57	1		T61	5		T62	6
auto[TlIntgErrData]	full_word	auto[0]	5	1			T150	1		T144	2		T151	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T61	1		T62	1		T150	1
auto[TlIntgErrBoth]	partial	auto[0]	63	1			T61	4		T95	5		T147	3
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T57	3		T61	3		T62	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T144	1		T149	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T62	1		T95	1		T149	1