Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	413936610	1431053	0	0
intr_enable_rd_A	413936610	3470	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413936610	1431053	0	0
T20	396140	7090	0	0
T21	0	18509	0	0
T26	748871	0	0	0
T46	66288	0	0	0
T57	0	3	0	0
T60	0	682	0	0
T61	0	2	0	0
T62	0	3	0	0
T67	0	296	0	0
T68	0	20	0	0
T69	0	186	0	0
T70	0	3	0	0
T71	1598	0	0	0
T72	134204	0	0	0
T73	989371	0	0	0
T74	74612	0	0	0
T75	128152	0	0	0
T76	115173	0	0	0
T77	78309	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413936610	3470	0	0
T21	0	96	0	0
T25	37240	0	0	0
T78	204626	24	0	0
T79	0	78	0	0
T80	0	65	0	0
T81	0	34	0	0
T82	0	11	0	0
T83	0	50	0	0
T84	0	30	0	0
T85	0	19	0	0
T86	0	40	0	0
T87	14694	0	0	0
T88	847116	0	0	0
T89	778798	0	0	0
T90	133931	0	0	0
T91	158224	0	0	0
T92	331960	0	0	0
T93	990	0	0	0
T94	1861	0	0	0