Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40340220	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37840150

1

T1

3

T2

1022

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37351273	1			T1	1		T2	1008		T3	1
values[0x0]	19152716	1			T1	10		T2	442		T22	5
values[0x1]	21676381	1			T1	14		T2	517		T22	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31086064	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

47094306

1

T1

7

T2

1260

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	231575	1			T2	12		T4	22		T5	2
valid_sources[0x01]	234968	1			T2	10		T4	25		T5	109
valid_sources[0x02]	228984	1			T2	5		T4	18		T5	47
valid_sources[0x03]	231338	1			T2	8		T4	18		T5	27
valid_sources[0x04]	233112	1			T2	4		T22	1		T4	14
valid_sources[0x05]	235523	1			T2	5		T4	15		T5	34
valid_sources[0x06]	234192	1			T2	8		T4	26		T5	65
valid_sources[0x07]	231765	1			T2	13		T4	16		T5	45
valid_sources[0x08]	281489	1			T2	4		T4	19		T5	57
valid_sources[0x09]	233976	1			T2	9		T4	13		T5	58
valid_sources[0x0a]	294207	1			T2	6		T4	28		T6	47
valid_sources[0x0b]	290382	1			T2	4		T4	14		T5	134
valid_sources[0x0c]	229921	1			T2	14		T4	13		T5	47
valid_sources[0x0d]	2043231	1			T2	9		T4	11		T5	17
valid_sources[0x0e]	234469	1			T2	1		T4	17		T5	112
valid_sources[0x0f]	327367	1			T2	4		T4	14		T5	31
valid_sources[0x10]	2120891	1			T2	8		T4	20		T5	39
valid_sources[0x11]	234100	1			T2	9		T4	22		T6	54
valid_sources[0x12]	244438	1			T2	5		T4	24		T5	8
valid_sources[0x13]	231965	1			T2	8		T4	17		T5	3
valid_sources[0x14]	233255	1			T2	6		T4	16		T5	144
valid_sources[0x15]	232202	1			T2	5		T4	14		T5	197
valid_sources[0x16]	232100	1			T2	11		T4	19		T5	39
valid_sources[0x17]	231385	1			T2	7		T4	15		T5	52
valid_sources[0x18]	326364	1			T2	8		T24	9		T4	11
valid_sources[0x19]	232432	1			T2	6		T4	13		T5	20
valid_sources[0x1a]	275537	1			T2	6		T4	16		T5	46
valid_sources[0x1b]	232801	1			T2	3		T4	22		T5	66
valid_sources[0x1c]	233668	1			T2	9		T4	21		T5	115
valid_sources[0x1d]	522966	1			T2	4		T22	1		T4	14
valid_sources[0x1e]	670161	1			T2	11		T4	15		T6	44
valid_sources[0x1f]	474470	1			T2	16		T22	1		T4	23
valid_sources[0x20]	233148	1			T2	10		T4	16		T5	153
valid_sources[0x21]	294692	1			T2	6		T4	23		T5	84
valid_sources[0x22]	834586	1			T2	10		T4	8		T5	216
valid_sources[0x23]	230070	1			T2	11		T4	18		T5	41
valid_sources[0x24]	252207	1			T2	3		T4	20		T5	9
valid_sources[0x25]	241084	1			T2	5		T4	18		T5	90
valid_sources[0x26]	326275	1			T2	9		T4	27		T6	50
valid_sources[0x27]	231970	1			T2	11		T4	22		T5	152
valid_sources[0x28]	272889	1			T1	1		T2	9		T4	23
valid_sources[0x29]	266486	1			T2	10		T4	12		T5	8
valid_sources[0x2a]	230604	1			T2	10		T4	15		T5	104
valid_sources[0x2b]	279213	1			T2	2		T4	15		T5	27
valid_sources[0x2c]	284565	1			T2	6		T4	25		T5	7
valid_sources[0x2d]	250140	1			T2	10		T4	20		T5	29
valid_sources[0x2e]	280113	1			T2	6		T4	16		T5	137
valid_sources[0x2f]	233484	1			T2	6		T4	12		T6	52
valid_sources[0x30]	385120	1			T1	1		T2	10		T4	19
valid_sources[0x31]	302065	1			T2	10		T4	25		T6	48
valid_sources[0x32]	228446	1			T2	4		T4	18		T5	74
valid_sources[0x33]	231054	1			T2	6		T4	15		T6	52
valid_sources[0x34]	231441	1			T2	6		T22	2		T4	21
valid_sources[0x35]	301262	1			T2	3		T4	16		T6	45
valid_sources[0x36]	233691	1			T2	10		T4	23		T6	69
valid_sources[0x37]	232282	1			T2	6		T4	11		T5	64
valid_sources[0x38]	230744	1			T1	2		T2	9		T4	20
valid_sources[0x39]	262471	1			T2	6		T4	13		T6	63
valid_sources[0x3a]	246156	1			T2	7		T4	11		T5	2
valid_sources[0x3b]	279489	1			T2	6		T4	15		T5	16
valid_sources[0x3c]	275314	1			T2	10		T4	9		T5	87
valid_sources[0x3d]	238853	1			T2	3		T4	18		T6	44
valid_sources[0x3e]	229643	1			T2	3		T4	13		T6	55
valid_sources[0x3f]	234867	1			T2	8		T4	12		T6	45
valid_sources[0x40]	234738	1			T2	7		T4	13		T5	4
valid_sources[0x41]	229842	1			T2	8		T22	2		T4	19
valid_sources[0x42]	307016	1			T2	7		T4	16		T5	10
valid_sources[0x43]	230996	1			T2	6		T4	19		T5	4
valid_sources[0x44]	230610	1			T2	6		T4	12		T5	177
valid_sources[0x45]	236262	1			T2	13		T4	17		T5	98
valid_sources[0x46]	300601	1			T2	7		T4	14		T5	68
valid_sources[0x47]	245043	1			T1	2		T2	6		T4	13
valid_sources[0x48]	232650	1			T2	9		T4	21		T5	51
valid_sources[0x49]	235050	1			T2	7		T4	13		T6	36
valid_sources[0x4a]	2138547	1			T2	10		T22	1		T4	12
valid_sources[0x4b]	232594	1			T2	4		T4	14		T5	16
valid_sources[0x4c]	229832	1			T2	6		T4	15		T5	17
valid_sources[0x4d]	232063	1			T2	13		T4	18		T5	24
valid_sources[0x4e]	241614	1			T2	10		T4	18		T5	24
valid_sources[0x4f]	230643	1			T2	5		T4	23		T5	109
valid_sources[0x50]	353030	1			T2	3		T4	15		T5	111
valid_sources[0x51]	275590	1			T2	5		T4	16		T5	20
valid_sources[0x52]	236362	1			T2	10		T4	18		T5	39
valid_sources[0x53]	257246	1			T2	5		T4	18		T5	8
valid_sources[0x54]	322119	1			T1	1		T2	9		T4	16
valid_sources[0x55]	233396	1			T2	4		T4	16		T5	70
valid_sources[0x56]	247857	1			T2	4		T4	15		T5	17
valid_sources[0x57]	230327	1			T2	6		T4	14		T6	46
valid_sources[0x58]	232922	1			T2	5		T22	1		T4	18
valid_sources[0x59]	231451	1			T2	2		T4	25		T5	8
valid_sources[0x5a]	336224	1			T2	9		T22	1		T4	12
valid_sources[0x5b]	230225	1			T2	10		T4	18		T5	34
valid_sources[0x5c]	231602	1			T1	2		T2	7		T4	8
valid_sources[0x5d]	232106	1			T2	5		T4	22		T6	57
valid_sources[0x5e]	257848	1			T1	1		T2	8		T4	14
valid_sources[0x5f]	230783	1			T1	2		T2	4		T4	8
valid_sources[0x60]	231803	1			T2	7		T4	16		T6	51
valid_sources[0x61]	233940	1			T2	6		T4	27		T5	26
valid_sources[0x62]	230773	1			T2	8		T4	12		T5	50
valid_sources[0x63]	236028	1			T2	12		T4	20		T6	64
valid_sources[0x64]	231531	1			T2	7		T4	15		T6	38
valid_sources[0x65]	268685	1			T2	6		T4	25		T5	38
valid_sources[0x66]	238164	1			T2	9		T4	8		T5	23
valid_sources[0x67]	249529	1			T2	14		T4	10		T5	139
valid_sources[0x68]	231504	1			T2	14		T4	9		T6	58
valid_sources[0x69]	235085	1			T2	10		T4	26		T5	23
valid_sources[0x6a]	233768	1			T2	5		T4	11		T5	52
valid_sources[0x6b]	234328	1			T2	7		T4	17		T5	60
valid_sources[0x6c]	232821	1			T2	4		T4	14		T5	37
valid_sources[0x6d]	275465	1			T2	12		T4	13		T5	94
valid_sources[0x6e]	247610	1			T2	15		T4	17		T5	59
valid_sources[0x6f]	889748	1			T2	9		T23	1		T4	12
valid_sources[0x70]	338178	1			T2	6		T4	19		T5	58
valid_sources[0x71]	334400	1			T2	10		T4	18		T5	65
valid_sources[0x72]	230494	1			T2	7		T4	12		T5	3
valid_sources[0x73]	230931	1			T2	11		T4	23		T6	45
valid_sources[0x74]	238862	1			T2	8		T22	1		T4	11
valid_sources[0x75]	254078	1			T2	4		T4	24		T5	38
valid_sources[0x76]	236584	1			T2	9		T4	17		T5	5
valid_sources[0x77]	232278	1			T2	7		T4	16		T5	12
valid_sources[0x78]	234331	1			T2	7		T4	21		T5	54
valid_sources[0x79]	231294	1			T2	5		T4	16		T5	15
valid_sources[0x7a]	1090861	1			T2	5		T4	14		T6	48
valid_sources[0x7b]	234951	1			T2	4		T4	18		T5	1
valid_sources[0x7c]	367709	1			T2	7		T4	18		T5	37
valid_sources[0x7d]	232334	1			T2	8		T4	17		T5	36
valid_sources[0x7e]	234314	1			T2	8		T4	16		T6	62
valid_sources[0x7f]	230830	1			T2	6		T4	12		T6	50
valid_sources[0x80]	1098789	1			T2	8		T4	16		T5	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18446858

1

T2

501

T3

1

T22

1

values[0x0]

all_enables

biggest_size

10460946

1

T1

2

T2

275

T22

1

values[0x1]

all_enables

biggest_size

8932346

1

T1

1

T2

246

T22

1