Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

41961037

1

T1

22

T2

945

T18

1

full_word

37945271

1

T1

3

T2

1022

T3

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	79905968	1			T1	25		T2	1967		T3	1
auto[TlIntgErrCmd]	116	1			T63	7		T64	3		T65	6
auto[TlIntgErrData]	124	1			T63	2		T64	9		T65	1
auto[TlIntgErrBoth]	100	1			T63	1		T64	8		T65	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37892620

1

T1

1

T2

1008

T3

1

auto[1]

42013688

1

T1

24

T2

959

T22

11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	19404879	1			T1	1		T2	507		T18	1
auto[TlIntgErrNone]	partial	auto[1]	22555851	1			T1	21		T2	438		T22	9
auto[TlIntgErrNone]	full_word	auto[0]	18487574	1			T2	501		T3	1		T22	1
auto[TlIntgErrNone]	full_word	auto[1]	19457664	1			T1	3		T2	521		T22	2
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T63	3		T64	1		T65	3
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T63	3		T64	2		T65	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T63	1		T65	1		T142	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T140	1		T144	1		T142	1
auto[TlIntgErrData]	partial	auto[0]	62	1			T64	6		T140	4		T144	3
auto[TlIntgErrData]	partial	auto[1]	52	1			T64	1		T65	1		T140	4
auto[TlIntgErrData]	full_word	auto[0]	7	1			T64	1		T140	2		T143	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T63	2		T64	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T63	1		T64	5		T65	2
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T64	3		T65	1		T140	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T145	2		T146	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T140	1		T142	2		T143	1