Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	478297226	939886	0	0
intr_enable_rd_A	478297226	2543	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478297226	939886	0	0
T15	0	9969	0	0
T16	0	8735	0	0
T17	339125	6083	0	0
T19	175615	0	0	0
T34	223152	0	0	0
T35	267639	0	0	0
T36	165215	0	0	0
T37	219369	0	0	0
T38	19727	0	0	0
T39	223925	0	0	0
T63	0	3	0	0
T64	0	3	0	0
T68	0	21465	0	0
T69	0	903	0	0
T70	0	383	0	0
T71	0	17	0	0
T72	0	4	0	0
T73	1249	0	0	0
T74	224056	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478297226	2543	0	0
T16	183401	63	0	0
T67	0	9	0	0
T75	0	14	0	0
T76	0	34	0	0
T77	0	35	0	0
T78	0	41	0	0
T79	0	51	0	0
T80	0	73	0	0
T81	0	82	0	0
T82	0	79	0	0
T83	40102	0	0	0
T84	275671	0	0	0
T85	972	0	0	0
T86	589914	0	0	0
T87	147859	0	0	0
T88	145521	0	0	0
T89	377369	0	0	0
T90	136291	0	0	0
T91	133060	0	0	0