Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17918867	1			T4	1296		T5	3454		T6	2156
all_values[1]	17918867	1			T4	1296		T5	3454		T6	2156
all_values[2]	17918867	1			T4	1296		T5	3454		T6	2156

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

282076

1

T4

60

T5

685

T6

108

auto[1]

53474525

1

T4

3828

T5

9677

T6

6360

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45766703

1

T4

3588

T5

9058

T6

5734

auto[1]

7989898

1

T4

300

T5

1304

T6

734

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	115446	1			T5	685		T28	4		T26	2808
all_values[0]	auto[0]	auto[1]	278	1			T28	3		T15	2		T16	2
all_values[0]	auto[1]	auto[0]	17784015	1			T4	1276		T5	2765		T6	2128
all_values[0]	auto[1]	auto[1]	19128	1			T4	20		T5	4		T6	28
all_values[1]	auto[0]	auto[0]	79260	1			T6	54		T28	3		T12	42
all_values[1]	auto[0]	auto[1]	175	1			T19	3		T73	3		T142	1
all_values[1]	auto[1]	auto[0]	17839165	1			T4	1296		T5	3454		T6	2102
all_values[1]	auto[1]	auto[1]	267	1			T28	1		T24	1		T143	8
all_values[2]	auto[0]	auto[0]	40468	1			T4	60		T6	54		T8	1
all_values[2]	auto[0]	auto[1]	46449	1			T8	3		T25	2897		T28	2
all_values[2]	auto[1]	auto[0]	9908349	1			T4	956		T5	2154		T6	1396
all_values[2]	auto[1]	auto[1]	7923601	1			T4	280		T5	1300		T6	706