Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

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Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119736

1

T4

18

T5

10

T6

42

auto[1]

135156

1

T4

12

T5

4

T6

30

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	97432	1			T5	6		T7	10		T9	14
len_1026_2046	5716	1			T8	2		T10	2		T12	28
len_514_1022	2877	1			T8	5		T10	1		T12	14
len_2_510	3598	1			T6	1		T8	1		T12	17
len_2056	184	1			T8	3		T156	4		T18	2
len_2048	316	1			T6	2		T8	5		T12	1
len_2040	292	1			T4	3		T6	4		T156	1
len_1032	185	1			T4	1		T6	3		T8	5
len_1024	1859	1			T6	7		T11	1		T71	69
len_1016	164	1			T6	1		T8	1		T156	2
len_520	185	1			T6	4		T8	2		T156	4
len_512	371	1			T4	1		T6	5		T8	1
len_504	168	1			T4	2		T6	2		T18	2
len_8	1180	1			T157	4		T135	2		T20	1
len_0	12919	1			T4	8		T5	1		T6	7

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

131

1

T54

1

T14

3

T52

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	47453	1			T5	4		T7	8		T9	6
auto[0]	len_1026_2046	2739	1			T12	18		T11	41		T13	14
auto[0]	len_514_1022	1651	1			T8	3		T10	1		T12	10
auto[0]	len_2_510	2047	1			T6	1		T12	4		T11	6
auto[0]	len_2056	100	1			T156	2		T18	1		T40	3
auto[0]	len_2048	160	1			T6	1		T8	2		T12	1
auto[0]	len_2040	216	1			T4	1		T6	3		T156	1
auto[0]	len_1032	100	1			T4	1		T6	3		T8	3
auto[0]	len_1024	321	1			T6	4		T11	1		T13	1
auto[0]	len_1016	110	1			T156	2		T40	2		T158	2
auto[0]	len_520	104	1			T8	2		T156	3		T18	2
auto[0]	len_512	222	1			T6	4		T8	1		T12	2
auto[0]	len_504	89	1			T4	2		T6	2		T18	1
auto[0]	len_8	37	1			T135	2		T159	17		T160	1
auto[0]	len_0	4519	1			T4	5		T5	1		T6	3
auto[1]	len_2050_plus	49979	1			T5	2		T7	2		T9	8
auto[1]	len_1026_2046	2977	1			T8	2		T10	2		T12	10
auto[1]	len_514_1022	1226	1			T8	2		T12	4		T11	1
auto[1]	len_2_510	1551	1			T8	1		T12	13		T11	1
auto[1]	len_2056	84	1			T8	3		T156	2		T18	1
auto[1]	len_2048	156	1			T6	1		T8	3		T18	1
auto[1]	len_2040	76	1			T4	2		T6	1		T18	1
auto[1]	len_1032	85	1			T8	2		T155	1		T40	1
auto[1]	len_1024	1538	1			T6	3		T71	69		T156	1
auto[1]	len_1016	54	1			T6	1		T8	1		T158	2
auto[1]	len_520	81	1			T6	4		T156	1		T18	2
auto[1]	len_512	149	1			T4	1		T6	1		T12	1
auto[1]	len_504	79	1			T18	1		T40	2		T158	2
auto[1]	len_8	1143	1			T157	4		T20	1		T161	2
auto[1]	len_0	8400	1			T4	3		T6	4		T8	7

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

63

1

T162

1

T163

1

T105

2

auto[1]

len_upper

68

1

T54

1

T14

3

T52

2