Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4512569

1

T4

236

T5

676

T6

621

auto[1]

2891439

1

T4

237

T5

1050

T6

457

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2892859

1

T4

312

T5

849

T6

568

auto[1]

4511149

1

T4

161

T5

877

T6

510

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3191525

1

T4

240

T5

1202

T6

613

auto[1]

4212483

1

T4

233

T5

524

T6

465

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4539487

1

T4

240

T5

152

T6

445

auto[1]

2864521

1

T4

233

T5

1574

T6

633

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6797837	1			T4	390		T5	1685		T6	1058
fifo_depth[1]	109369	1			T4	17		T5	21		T6	15
fifo_depth[2]	77020	1			T4	13		T5	13		T6	4
fifo_depth[3]	57912	1			T4	13		T5	6		T7	2
fifo_depth[4]	52479	1			T4	13		T5	1		T6	1
fifo_depth[5]	41538	1			T4	9		T8	14		T9	1
fifo_depth[6]	33718	1			T4	7		T8	9		T26	25
fifo_depth[7]	22212	1			T4	4		T8	8		T26	10

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

606171

1

T4

83

T5

41

T6

20

auto[1]

6797837

1

T4

390

T5

1685

T6

1058

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7394093

1

T4

473

T5

1726

T6

1078

auto[1]

9915

1

T11

72

T18

206

T24

131

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

25961

1

T4

11

T6

1

T12

9

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

31149

1

T7

2

T12

2

T13

17

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

31364

1

T4

8

T7

3

T12

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

23400

1

T4

4

T7

10

T8

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

107510

1

T5

4

T6

2

T9

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

33754

1

T6

1

T9

1

T10

59

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

29331

1

T4

8

T7

3

T8

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

32013

1

T5

15

T6

1

T9

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

34753

1

T4

8

T8

14

T9

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

35729

1

T4

44

T5

22

T6

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

38146

1

T6

6

T7

10

T13

23

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

36834

1

T8

20

T10

159

T17

36

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

42189

1

T8

8

T12

9

T11

165

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

31922

1

T8

7

T54

1

T18

463

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

32109

1

T6

1

T8

28

T17

10

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

40007

1

T6

1

T8

11

T27

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

156727

1

T4

35

T6

190

T9

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

169701

1

T6

65

T7

79

T8

63

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

158805

1

T4

70

T6

1

T7

298

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

181520

1

T4

37

T5

397

T6

16

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1737667

1

T4

21

T5

148

T6

39

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

159593

1

T4

16

T6

156

T8

68

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

152817

1

T4

29

T7

511

T8

115

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

160213

1

T4

1

T5

638

T6

141

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

496088

1

T4

7

T6

34

T8

85

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

475106

1

T4

68

T5

430

T6

97

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

475325

1

T4

20

T6

73

T7

193

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

522251

1

T6

78

T7

22

T8

51

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

525916

1

T6

14

T8

59

T9

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

448804

1

T4

26

T5

72

T6

15

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

494779

1

T4

23

T6

84

T8

56

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

482525

1

T4

37

T6

55

T8

86

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

181700

1

T4

46

T6

191

T9

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

200342

1

T6

65

T7

81

T8

63

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

189831

1

T4

78

T6

1

T7

301

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

204270

1

T4

41

T5

397

T6

16

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1844847

1

T4

21

T5

152

T6

41

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

191709

1

T4

16

T6

157

T8

68

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

181604

1

T4

37

T7

514

T8

121

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

191300

1

T4

1

T5

653

T6

142

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

530705

1

T4

15

T6

34

T8

99

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

510115

1

T4

112

T5

452

T6

104

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

511813

1

T4

20

T6

79

T7

203

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

558912

1

T6

78

T7

22

T8

71

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

567856

1

T6

14

T8

67

T9

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

480613

1

T4

26

T5

72

T6

15

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

526315

1

T4

23

T6

85

T8

84

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

522161

1

T4

37

T6

56

T8

97

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

988

1

T24

5

T90

41

T165

69

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

508

1

T18

24

T57

8

T90

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

338

1

T11

1

T18

9

T103

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

650

1

T16

46

T143

7

T103

37

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

330

1

T11

28

T24

55

T103

23

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1638

1

T18

26

T24

35

T166

500

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

544

1

T143

13

T103

11

T57

151

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

926

1

T11

41

T24

24

T143

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

136

1

T166

1

T143

6

T167

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

720

1

T18

146

T143

122

T165

162

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1658

1

T166

4

T167

28

T141

1382

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

173

1

T168

3

T167

5

T144

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

249

1

T11

1

T24

11

T16

14

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

113

1

T24

1

T143

7

T103

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

573

1

T18

1

T16

72

T103

5

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

371

1

T11

1

T143

45

T57

13

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

156727

1

T4

35

T6

190

T9

1

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

169701

1

T6

65

T7

79

T8

63

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

158805

1

T4

70

T6

1

T7

298

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

181520

1

T4

37

T5

397

T6

16

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1737667

1

T4

21

T5

148

T6

39

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

159593

1

T4

16

T6

156

T8

68

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

152817

1

T4

29

T7

511

T8

115

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

160213

1

T4

1

T5

638

T6

141

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

496088

1

T4

7

T6

34

T8

85

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

475106

1

T4

68

T5

430

T6

97

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

475325

1

T4

20

T6

73

T7

193

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

522251

1

T6

78

T7

22

T8

51

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

525916

1

T6

14

T8

59

T9

1

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

448804

1

T4

26

T5

72

T6

15

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

494779

1

T4

23

T6

84

T8

56

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

482525

1

T4

37

T6

55

T8

86

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3269

1

T4

3

T6

1

T13

13

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3062

1

T7

2

T12

2

T13

4

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3344

1

T4

2

T7

3

T12

1

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3498

1

T4

1

T7

7

T8

3

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

36407

1

T5

1

T10

9

T12

22

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3484

1

T6

1

T9

1

T10

3

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

2886

1

T4

1

T7

1

T8

2

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3338

1

T5

6

T6

1

T10

1

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

5743

1

T8

3

T26

38

T10

1

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

5323

1

T4

10

T5

14

T6

6

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

6233

1

T6

4

T7

8

T13

6

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

6211

1

T8

3

T10

29

T17

23

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

8781

1

T8

1

T12

3

T11

1

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

5848

1

T8

1

T18

2

T24

3

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

5573

1

T6

1

T8

4

T17

6

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

6369

1

T6

1

T27

1

T156

2

fifo_depth[2]

auto[0]

auto[0]

auto[0]

auto[0]

2223

1

T4

2

T12

1

T13

42

fifo_depth[2]

auto[0]

auto[0]

auto[0]

auto[1]

2132

1

T13

2

T156

1

T18

2

fifo_depth[2]

auto[0]

auto[0]

auto[1]

auto[0]

2666

1

T4

1

T12

2

T11

5

fifo_depth[2]

auto[0]

auto[0]

auto[1]

auto[1]

2535

1

T7

3

T8

2

T10

45

fifo_depth[2]

auto[0]

auto[1]

auto[0]

auto[0]

20806

1

T5

1

T6

2

T10

9

fifo_depth[2]

auto[0]

auto[1]

auto[0]

auto[1]

2670

1

T10

8

T12

8

T11

9

fifo_depth[2]

auto[0]

auto[1]

auto[1]

auto[0]

2322

1

T4

3

T7

2

T8

2

fifo_depth[2]

auto[0]

auto[1]

auto[1]

auto[1]

2713

1

T5

7

T11

12

T13

2

fifo_depth[2]

auto[1]

auto[0]

auto[0]

auto[0]

4585

1

T4

1

T8

2

T26

47

fifo_depth[2]

auto[1]

auto[0]

auto[0]

auto[1]

4286

1

T4

6

T5

5

T10

17

fifo_depth[2]

auto[1]

auto[0]

auto[1]

auto[0]

5215

1

T6

2

T13

4

T40

1

fifo_depth[2]

auto[1]

auto[0]

auto[1]

auto[1]

4943

1

T8

3

T10

25

T17

7

fifo_depth[2]

auto[1]

auto[1]

auto[0]

auto[0]

6111

1

T8

1

T12

2

T11

2

fifo_depth[2]

auto[1]

auto[1]

auto[0]

auto[1]

4598

1

T8

2

T18

2

T14

1

fifo_depth[2]

auto[1]

auto[1]

auto[1]

auto[0]

4242

1

T8

5

T17

2

T18

5

fifo_depth[2]

auto[1]

auto[1]

auto[1]

auto[1]

4973

1

T11

4

T17

5

T18

4

fifo_depth[3]

auto[0]

auto[0]

auto[0]

auto[0]

1770

1

T4

2

T13

1

T29

1

fifo_depth[3]

auto[0]

auto[0]

auto[0]

auto[1]

1498

1

T13

3

T18

3

T24

5

fifo_depth[3]

auto[0]

auto[0]

auto[1]

auto[0]

2217

1

T4

1

T12

1

T11

3

fifo_depth[3]

auto[0]

auto[0]

auto[1]

auto[1]

2116

1

T4

1

T8

1

T10

51

fifo_depth[3]

auto[0]

auto[1]

auto[0]

auto[0]

13802

1

T5

1

T10

8

T11

2

fifo_depth[3]

auto[0]

auto[1]

auto[0]

auto[1]

1956

1

T10

10

T12

1

T11

9

fifo_depth[3]

auto[0]

auto[1]

auto[1]

auto[0]

1707

1

T10

9

T156

1

T18

1

fifo_depth[3]

auto[0]

auto[1]

auto[1]

auto[1]

1993

1

T5

2

T10

2

T11

1

fifo_depth[3]

auto[1]

auto[0]

auto[0]

auto[0]

3944

1

T4

1

T8

2

T26

44

fifo_depth[3]

auto[1]

auto[0]

auto[0]

auto[1]

3435

1

T4

8

T5

3

T10

18

fifo_depth[3]

auto[1]

auto[0]

auto[1]

auto[0]

4084

1

T7

2

T13

4

T156

1

fifo_depth[3]

auto[1]

auto[0]

auto[1]

auto[1]

3813

1

T8

2

T10

33

T17

3

fifo_depth[3]

auto[1]

auto[1]

auto[0]

auto[0]

4561

1

T8

1

T12

2

T11

1

fifo_depth[3]

auto[1]

auto[1]

auto[0]

auto[1]

3701

1

T8

1

T24

6

T38

1

fifo_depth[3]

auto[1]

auto[1]

auto[1]

auto[0]

3258

1

T8

8

T17

1

T18

10

fifo_depth[3]

auto[1]

auto[1]

auto[1]

auto[1]

4057

1

T8

1

T156

1

T17

1

fifo_depth[4]

auto[0]

auto[0]

auto[0]

auto[0]

1667

1

T4

1

T12

8

T13

25

fifo_depth[4]

auto[0]

auto[0]

auto[0]

auto[1]

1489

1

T13

5

T18

4

T24

5

fifo_depth[4]

auto[0]

auto[0]

auto[1]

auto[0]

2222

1

T4

2

T12

1

T11

5

fifo_depth[4]

auto[0]

auto[0]

auto[1]

auto[1]

2103

1

T4

1

T10

41

T156

2

fifo_depth[4]

auto[0]

auto[1]

auto[0]

auto[0]

9703

1

T5

1

T10

11

T11

1

fifo_depth[4]

auto[0]

auto[1]

auto[0]

auto[1]

1980

1

T10

8

T12

5

T11

9

fifo_depth[4]

auto[0]

auto[1]

auto[1]

auto[0]

1770

1

T4

2

T8

1

T10

14

fifo_depth[4]

auto[0]

auto[1]

auto[1]

auto[1]

2188

1

T11

22

T13

3

T156

2

fifo_depth[4]

auto[1]

auto[0]

auto[0]

auto[0]

3834

1

T4

2

T8

1

T26

38

fifo_depth[4]

auto[1]

auto[0]

auto[0]

auto[1]

3503

1

T4

5

T6

1

T10

21

fifo_depth[4]

auto[1]

auto[0]

auto[1]

auto[0]

3942

1

T13

3

T156

1

T169

7

fifo_depth[4]

auto[1]

auto[0]

auto[1]

auto[1]

3451

1

T8

1

T10

22

T17

3

fifo_depth[4]

auto[1]

auto[1]

auto[0]

auto[0]

4091

1

T8

1

T11

3

T71

6

fifo_depth[4]

auto[1]

auto[1]

auto[0]

auto[1]

3483

1

T8

2

T18

11

T24

40

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[0]

3056

1

T8

3

T18

7

T24

7

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[1]

3997

1

T8

2

T11

4

T156

2

fifo_depth[5]

auto[0]

auto[0]

auto[0]

auto[0]

1325

1

T4

2

T55

2

T170

1

fifo_depth[5]

auto[0]

auto[0]

auto[0]

auto[1]

1198

1

T13

2

T18

4

T24

4

fifo_depth[5]

auto[0]

auto[0]

auto[1]

auto[0]

1666

1

T4

2

T11

18

T24

11

fifo_depth[5]

auto[0]

auto[0]

auto[1]

auto[1]

1503

1

T8

2

T10

28

T156

3

fifo_depth[5]

auto[0]

auto[1]

auto[0]

auto[0]

6968

1

T10

6

T11

2

T156

1

fifo_depth[5]

auto[0]

auto[1]

auto[0]

auto[1]

1464

1

T10

6

T12

1

T11

8

fifo_depth[5]

auto[0]

auto[1]

auto[1]

auto[0]

1294

1

T4

1

T8

1

T10

7

fifo_depth[5]

auto[0]

auto[1]

auto[1]

auto[1]

1540

1

T11

64

T156

1

T24

4

fifo_depth[5]

auto[1]

auto[0]

auto[0]

auto[0]

3110

1

T4

2

T8

1

T9

1

fifo_depth[5]

auto[1]

auto[0]

auto[0]

auto[1]

2833

1

T4

2

T10

15

T18

1

fifo_depth[5]

auto[1]

auto[0]

auto[1]

auto[0]

3213

1

T13

3

T169

4

T166

12

fifo_depth[5]

auto[1]

auto[0]

auto[1]

auto[1]

3009

1

T8

2

T10

24

T18

1

fifo_depth[5]

auto[1]

auto[1]

auto[0]

auto[0]

3464

1

T8

2

T12

1

T11

1

fifo_depth[5]

auto[1]

auto[1]

auto[0]

auto[1]

2835

1

T8

1

T18

8

T24

10

fifo_depth[5]

auto[1]

auto[1]

auto[1]

auto[0]

2637

1

T8

3

T17

1

T18

10

fifo_depth[5]

auto[1]

auto[1]

auto[1]

auto[1]

3479

1

T8

2

T18

3

T16

1

fifo_depth[6]

auto[0]

auto[0]

auto[0]

auto[0]

1107

1

T4

1

T55

3

T51

15

fifo_depth[6]

auto[0]

auto[0]

auto[0]

auto[1]

1159

1

T156

3

T18

6

T24

7

fifo_depth[6]

auto[0]

auto[0]

auto[1]

auto[0]

1467

1

T11

4

T18

12

T24

114

fifo_depth[6]

auto[0]

auto[0]

auto[1]

auto[1]

1245

1

T4

1

T10

18

T156

2

fifo_depth[6]

auto[0]

auto[1]

auto[0]

auto[0]

4907

1

T10

4

T11

3

T156

3

fifo_depth[6]

auto[0]

auto[1]

auto[0]

auto[1]

1233

1

T10

8

T11

10

T18

3

fifo_depth[6]

auto[0]

auto[1]

auto[1]

auto[0]

947

1

T4

1

T10

10

T11

1

fifo_depth[6]

auto[0]

auto[1]

auto[1]

auto[1]

1322

1

T10

1

T11

22

T13

1

fifo_depth[6]

auto[1]

auto[0]

auto[0]

auto[0]

2482

1

T4

1

T8

2

T26

25

fifo_depth[6]

auto[1]

auto[0]

auto[0]

auto[1]

2429

1

T4

3

T10

16

T18

8

fifo_depth[6]

auto[1]

auto[0]

auto[1]

auto[0]

2736

1

T13

2

T169

5

T55

2

fifo_depth[6]

auto[1]

auto[0]

auto[1]

auto[1]

2495

1

T8

3

T10

14

T16

82

fifo_depth[6]

auto[1]

auto[1]

auto[0]

auto[0]

2851

1

T12

1

T11

3

T13

1

fifo_depth[6]

auto[1]

auto[1]

auto[0]

auto[1]

2455

1

T54

1

T18

42

T14

1

fifo_depth[6]

auto[1]

auto[1]

auto[1]

auto[0]

2103

1

T8

2

T18

10

T24

7

fifo_depth[6]

auto[1]

auto[1]

auto[1]

auto[1]

2780

1

T8

2

T11

4

T156

1

fifo_depth[7]

auto[0]

auto[0]

auto[0]

auto[0]

815

1

T55

3

T51

6

T63

1

fifo_depth[7]

auto[0]

auto[0]

auto[0]

auto[1]

797

1

T13

1

T18

5

T24

8

fifo_depth[7]

auto[0]

auto[0]

auto[1]

auto[0]

833

1

T11

19

T18

1

T24

16

fifo_depth[7]

auto[0]

auto[0]

auto[1]

auto[1]

756

1

T8

1

T10

10

T156

1

fifo_depth[7]

auto[0]

auto[1]

auto[0]

auto[0]

2894

1

T10

1

T16

4

T171

2

fifo_depth[7]

auto[0]

auto[1]

auto[0]

auto[1]

850

1

T10

6

T11

8

T18

6

fifo_depth[7]

auto[0]

auto[1]

auto[1]

auto[0]

751

1

T10

5

T11

6

T54

1

fifo_depth[7]

auto[0]

auto[1]

auto[1]

auto[1]

962

1

T11

64

T13

1

T24

3

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[0]

1627

1

T26

10

T10

1

T156

2

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[1]

1600

1

T4

4

T10

9

T16

7

fifo_depth[7]

auto[1]

auto[0]

auto[1]

auto[0]

1716

1

T13

1

T156

1

T169

3

fifo_depth[7]

auto[1]

auto[0]

auto[1]

auto[1]

1654

1

T8

3

T10

8

T16

22

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[0]

2008

1

T8

1

T11

3

T172

1

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[1]

1482

1

T18

37

T24

10

T169

1

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[0]

1558

1

T8

2

T18

17

T24

9

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[1]

1909

1

T8

1

T156

1

T54

1